diff options
Diffstat (limited to 'drivers/gpu/drm/i915/display/intel_color.c')
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_color.c | 1265 |
1 files changed, 1033 insertions, 232 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c index 250e83f1f5ac..8d97c299e657 100644 --- a/drivers/gpu/drm/i915/display/intel_color.c +++ b/drivers/gpu/drm/i915/display/intel_color.c @@ -53,7 +53,18 @@ struct intel_color_funcs { * involved with the same commit. */ void (*load_luts)(const struct intel_crtc_state *crtc_state); + /* + * Read out the LUTs from the hardware into the software state. + * Used by eg. the hardware state checker. + */ void (*read_luts)(struct intel_crtc_state *crtc_state); + /* + * Compare the LUTs + */ + bool (*lut_equal)(const struct intel_crtc_state *crtc_state, + const struct drm_property_blob *blob1, + const struct drm_property_blob *blob2, + bool is_pre_csc_lut); }; #define CTM_COEFF_SIGN (1ULL << 63) @@ -143,15 +154,7 @@ static const u16 ilk_csc_postoff_rgb_to_ycbcr[3] = { static bool lut_is_legacy(const struct drm_property_blob *lut) { - return drm_color_lut_size(lut) == LEGACY_LUT_LENGTH; -} - -static bool crtc_state_is_legacy_gamma(const struct intel_crtc_state *crtc_state) -{ - return !crtc_state->hw.degamma_lut && - !crtc_state->hw.ctm && - crtc_state->hw.gamma_lut && - lut_is_legacy(crtc_state->hw.gamma_lut); + return lut && drm_color_lut_size(lut) == LEGACY_LUT_LENGTH; } /* @@ -246,17 +249,44 @@ static void icl_update_output_csc(struct intel_crtc *crtc, intel_de_write_fw(i915, PIPE_CSC_OUTPUT_POSTOFF_LO(pipe), postoff[2]); } -static bool ilk_csc_limited_range(const struct intel_crtc_state *crtc_state) +static bool ilk_limited_range(const struct intel_crtc_state *crtc_state) { struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); - /* - * FIXME if there's a gamma LUT after the CSC, we should - * do the range compression using the gamma LUT instead. - */ - return crtc_state->limited_color_range && - (IS_HASWELL(i915) || IS_BROADWELL(i915) || - IS_DISPLAY_VER(i915, 9, 10)); + /* icl+ have dedicated output CSC */ + if (DISPLAY_VER(i915) >= 11) + return false; + + /* pre-hsw have PIPECONF_COLOR_RANGE_SELECT */ + if (DISPLAY_VER(i915) < 7 || IS_IVYBRIDGE(i915)) + return false; + + return crtc_state->limited_color_range; +} + +static bool ilk_lut_limited_range(const struct intel_crtc_state *crtc_state) +{ + struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); + + if (!ilk_limited_range(crtc_state)) + return false; + + if (crtc_state->c8_planes) + return false; + + if (DISPLAY_VER(i915) == 10) + return crtc_state->hw.gamma_lut; + else + return crtc_state->hw.gamma_lut && + (crtc_state->hw.degamma_lut || crtc_state->hw.ctm); +} + +static bool ilk_csc_limited_range(const struct intel_crtc_state *crtc_state) +{ + if (!ilk_limited_range(crtc_state)) + return false; + + return !ilk_lut_limited_range(crtc_state); } static void ilk_csc_convert_ctm(const struct intel_crtc_state *crtc_state, @@ -437,6 +467,79 @@ static void i9xx_lut_8_pack(struct drm_color_lut *entry, u32 val) entry->blue = intel_color_lut_pack(REG_FIELD_GET(PALETTE_BLUE_MASK, val), 8); } +/* i8xx/i9xx+ 10bit slope format "even DW" (low 8 bits) */ +static u32 _i9xx_lut_10_ldw(u16 a) +{ + return drm_color_lut_extract(a, 10) & 0xff; +} + +static u32 i9xx_lut_10_ldw(const struct drm_color_lut *color) +{ + return REG_FIELD_PREP(PALETTE_RED_MASK, _i9xx_lut_10_ldw(color[0].red)) | + REG_FIELD_PREP(PALETTE_GREEN_MASK, _i9xx_lut_10_ldw(color[0].green)) | + REG_FIELD_PREP(PALETTE_BLUE_MASK, _i9xx_lut_10_ldw(color[0].blue)); +} + +/* i8xx/i9xx+ 10bit slope format "odd DW" (high 2 bits + slope) */ +static u32 _i9xx_lut_10_udw(u16 a, u16 b) +{ + unsigned int mantissa, exponent; + + a = drm_color_lut_extract(a, 10); + b = drm_color_lut_extract(b, 10); + + /* b = a + 8 * m * 2 ^ -e */ + mantissa = clamp(b - a, 0, 0x7f); + exponent = 3; + while (mantissa > 0xf) { + mantissa >>= 1; + exponent--; + } + + return (exponent << 6) | + (mantissa << 2) | + (a >> 8); +} + +static u32 i9xx_lut_10_udw(const struct drm_color_lut *color) +{ + return REG_FIELD_PREP(PALETTE_RED_MASK, _i9xx_lut_10_udw(color[0].red, color[1].red)) | + REG_FIELD_PREP(PALETTE_GREEN_MASK, _i9xx_lut_10_udw(color[0].green, color[1].green)) | + REG_FIELD_PREP(PALETTE_BLUE_MASK, _i9xx_lut_10_udw(color[0].blue, color[1].blue)); +} + +static void i9xx_lut_10_pack(struct drm_color_lut *color, + u32 ldw, u32 udw) +{ + u16 red = REG_FIELD_GET(PALETTE_10BIT_RED_LDW_MASK, ldw) | + REG_FIELD_GET(PALETTE_10BIT_RED_UDW_MASK, udw) << 8; + u16 green = REG_FIELD_GET(PALETTE_10BIT_GREEN_LDW_MASK, ldw) | + REG_FIELD_GET(PALETTE_10BIT_GREEN_UDW_MASK, udw) << 8; + u16 blue = REG_FIELD_GET(PALETTE_10BIT_BLUE_LDW_MASK, ldw) | + REG_FIELD_GET(PALETTE_10BIT_BLUE_UDW_MASK, udw) << 8; + + color->red = intel_color_lut_pack(red, 10); + color->green = intel_color_lut_pack(green, 10); + color->blue = intel_color_lut_pack(blue, 10); +} + +static void i9xx_lut_10_pack_slope(struct drm_color_lut *color, + u32 ldw, u32 udw) +{ + int r_exp = REG_FIELD_GET(PALETTE_10BIT_RED_EXP_MASK, udw); + int r_mant = REG_FIELD_GET(PALETTE_10BIT_RED_MANT_MASK, udw); + int g_exp = REG_FIELD_GET(PALETTE_10BIT_GREEN_EXP_MASK, udw); + int g_mant = REG_FIELD_GET(PALETTE_10BIT_GREEN_MANT_MASK, udw); + int b_exp = REG_FIELD_GET(PALETTE_10BIT_BLUE_EXP_MASK, udw); + int b_mant = REG_FIELD_GET(PALETTE_10BIT_BLUE_MANT_MASK, udw); + + i9xx_lut_10_pack(color, ldw, udw); + + color->red += r_mant << (3 - r_exp); + color->green += g_mant << (3 - g_exp); + color->blue += b_mant << (3 - b_exp); +} + /* i965+ "10.6" bit interpolated format "even DW" (low 8 bits) */ static u32 i965_lut_10p6_ldw(const struct drm_color_lut *color) { @@ -600,9 +703,18 @@ create_linear_lut(struct drm_i915_private *i915, int lut_size) return blob; } +static u16 lut_limited_range(unsigned int value) +{ + unsigned int min = 16 << 8; + unsigned int max = 235 << 8; + + return value * (max - min) / 0xffff + min; +} + static struct drm_property_blob * create_resized_lut(struct drm_i915_private *i915, - const struct drm_property_blob *blob_in, int lut_out_size) + const struct drm_property_blob *blob_in, int lut_out_size, + bool limited_color_range) { int i, lut_in_size = drm_color_lut_size(blob_in); struct drm_property_blob *blob_out; @@ -618,8 +730,18 @@ create_resized_lut(struct drm_i915_private *i915, lut_in = blob_in->data; lut_out = blob_out->data; - for (i = 0; i < lut_out_size; i++) - lut_out[i] = lut_in[i * (lut_in_size - 1) / (lut_out_size - 1)]; + for (i = 0; i < lut_out_size; i++) { + const struct drm_color_lut *entry = + &lut_in[i * (lut_in_size - 1) / (lut_out_size - 1)]; + + if (limited_color_range) { + lut_out[i].red = lut_limited_range(entry->red); + lut_out[i].green = lut_limited_range(entry->green); + lut_out[i].blue = lut_limited_range(entry->blue); + } else { + lut_out[i] = *entry; + } + } return blob_out; } @@ -642,12 +764,38 @@ static void i9xx_load_lut_8(struct intel_crtc *crtc, i9xx_lut_8(&lut[i])); } +static void i9xx_load_lut_10(struct intel_crtc *crtc, + const struct drm_property_blob *blob) +{ + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + const struct drm_color_lut *lut = blob->data; + int i, lut_size = drm_color_lut_size(blob); + enum pipe pipe = crtc->pipe; + + for (i = 0; i < lut_size - 1; i++) { + intel_de_write_fw(dev_priv, PALETTE(pipe, 2 * i + 0), + i9xx_lut_10_ldw(&lut[i])); + intel_de_write_fw(dev_priv, PALETTE(pipe, 2 * i + 1), + i9xx_lut_10_udw(&lut[i])); + } +} + static void i9xx_load_luts(const struct intel_crtc_state *crtc_state) { struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); const struct drm_property_blob *post_csc_lut = crtc_state->post_csc_lut; - i9xx_load_lut_8(crtc, post_csc_lut); + switch (crtc_state->gamma_mode) { + case GAMMA_MODE_MODE_8BIT: + i9xx_load_lut_8(crtc, post_csc_lut); + break; + case GAMMA_MODE_MODE_10BIT: + i9xx_load_lut_10(crtc, post_csc_lut); + break; + default: + MISSING_CASE(crtc_state->gamma_mode); + break; + } } static void i965_load_lut_10p6(struct intel_crtc *crtc, @@ -675,16 +823,34 @@ static void i965_load_luts(const struct intel_crtc_state *crtc_state) struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); const struct drm_property_blob *post_csc_lut = crtc_state->post_csc_lut; - if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT) + switch (crtc_state->gamma_mode) { + case GAMMA_MODE_MODE_8BIT: i9xx_load_lut_8(crtc, post_csc_lut); - else + break; + case GAMMA_MODE_MODE_10BIT: i965_load_lut_10p6(crtc, post_csc_lut); + break; + default: + MISSING_CASE(crtc_state->gamma_mode); + break; + } } -static void ilk_load_lut_8(struct intel_crtc *crtc, +static void ilk_lut_write(const struct intel_crtc_state *crtc_state, + i915_reg_t reg, u32 val) +{ + struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); + + if (crtc_state->dsb) + intel_dsb_reg_write(crtc_state->dsb, reg, val); + else + intel_de_write_fw(i915, reg, val); +} + +static void ilk_load_lut_8(const struct intel_crtc_state *crtc_state, const struct drm_property_blob *blob) { - struct drm_i915_private *i915 = to_i915(crtc->base.dev); + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); const struct drm_color_lut *lut; enum pipe pipe = crtc->pipe; int i; @@ -695,36 +861,35 @@ static void ilk_load_lut_8(struct intel_crtc *crtc, lut = blob->data; for (i = 0; i < 256; i++) - intel_de_write_fw(i915, LGC_PALETTE(pipe, i), - i9xx_lut_8(&lut[i])); + ilk_lut_write(crtc_state, LGC_PALETTE(pipe, i), + i9xx_lut_8(&lut[i])); } -static void ilk_load_lut_10(struct intel_crtc *crtc, +static void ilk_load_lut_10(const struct intel_crtc_state *crtc_state, const struct drm_property_blob *blob) { - struct drm_i915_private *i915 = to_i915(crtc->base.dev); + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); const struct drm_color_lut *lut = blob->data; int i, lut_size = drm_color_lut_size(blob); enum pipe pipe = crtc->pipe; for (i = 0; i < lut_size; i++) - intel_de_write_fw(i915, PREC_PALETTE(pipe, i), - ilk_lut_10(&lut[i])); + ilk_lut_write(crtc_state, PREC_PALETTE(pipe, i), + ilk_lut_10(&lut[i])); } static void ilk_load_luts(const struct intel_crtc_state *crtc_state) { - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); const struct drm_property_blob *post_csc_lut = crtc_state->post_csc_lut; const struct drm_property_blob *pre_csc_lut = crtc_state->pre_csc_lut; const struct drm_property_blob *blob = post_csc_lut ?: pre_csc_lut; switch (crtc_state->gamma_mode) { case GAMMA_MODE_MODE_8BIT: - ilk_load_lut_8(crtc, blob); + ilk_load_lut_8(crtc_state, blob); break; case GAMMA_MODE_MODE_10BIT: - ilk_load_lut_10(crtc, blob); + ilk_load_lut_10(crtc_state, blob); break; default: MISSING_CASE(crtc_state->gamma_mode); @@ -745,50 +910,56 @@ static int ivb_lut_10_size(u32 prec_index) * "Restriction : Index auto increment mode is not * supported and must not be enabled." */ -static void ivb_load_lut_10(struct intel_crtc *crtc, +static void ivb_load_lut_10(const struct intel_crtc_state *crtc_state, const struct drm_property_blob *blob, u32 prec_index) { - struct drm_i915_private *i915 = to_i915(crtc->base.dev); + const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); const struct drm_color_lut *lut = blob->data; int i, lut_size = drm_color_lut_size(blob); enum pipe pipe = crtc->pipe; for (i = 0; i < lut_size; i++) { - intel_de_write_fw(i915, PREC_PAL_INDEX(pipe), prec_index++); - intel_de_write_fw(i915, PREC_PAL_DATA(pipe), - ilk_lut_10(&lut[i])); + ilk_lut_write(crtc_state, PREC_PAL_INDEX(pipe), + prec_index + i); + ilk_lut_write(crtc_state, PREC_PAL_DATA(pipe), + ilk_lut_10(&lut[i])); } /* * Reset the index, otherwise it prevents the legacy palette to be * written properly. */ - intel_de_write_fw(i915, PREC_PAL_INDEX(pipe), 0); + ilk_lut_write(crtc_state, PREC_PAL_INDEX(pipe), + PAL_PREC_INDEX_VALUE(0)); } /* On BDW+ the index auto increment mode actually works */ -static void bdw_load_lut_10(struct intel_crtc *crtc, +static void bdw_load_lut_10(const struct intel_crtc_state *crtc_state, const struct drm_property_blob *blob, u32 prec_index) { - struct drm_i915_private *i915 = to_i915(crtc->base.dev); + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); const struct drm_color_lut *lut = blob->data; int i, lut_size = drm_color_lut_size(blob); enum pipe pipe = crtc->pipe; - intel_de_write_fw(i915, PREC_PAL_INDEX(pipe), - prec_index | PAL_PREC_AUTO_INCREMENT); + ilk_lut_write(crtc_state, PREC_PAL_INDEX(pipe), + prec_index); + ilk_lut_write(crtc_state, PREC_PAL_INDEX(pipe), + PAL_PREC_AUTO_INCREMENT | + prec_index); for (i = 0; i < lut_size; i++) - intel_de_write_fw(i915, PREC_PAL_DATA(pipe), - ilk_lut_10(&lut[i])); + ilk_lut_write(crtc_state, PREC_PAL_DATA(pipe), + ilk_lut_10(&lut[i])); /* * Reset the index, otherwise it prevents the legacy palette to be * written properly. */ - intel_de_write_fw(i915, PREC_PAL_INDEX(pipe), 0); + ilk_lut_write(crtc_state, PREC_PAL_INDEX(pipe), + PAL_PREC_INDEX_VALUE(0)); } static void ivb_load_lut_ext_max(const struct intel_crtc_state *crtc_state) @@ -797,9 +968,9 @@ static void ivb_load_lut_ext_max(const struct intel_crtc_state *crtc_state) enum pipe pipe = crtc->pipe; /* Program the max register to clamp values > 1.0. */ - intel_dsb_reg_write(crtc_state, PREC_PAL_EXT_GC_MAX(pipe, 0), 1 << 16); - intel_dsb_reg_write(crtc_state, PREC_PAL_EXT_GC_MAX(pipe, 1), 1 << 16); - intel_dsb_reg_write(crtc_state, PREC_PAL_EXT_GC_MAX(pipe, 2), 1 << 16); + ilk_lut_write(crtc_state, PREC_PAL_EXT_GC_MAX(pipe, 0), 1 << 16); + ilk_lut_write(crtc_state, PREC_PAL_EXT_GC_MAX(pipe, 1), 1 << 16); + ilk_lut_write(crtc_state, PREC_PAL_EXT_GC_MAX(pipe, 2), 1 << 16); } static void glk_load_lut_ext2_max(const struct intel_crtc_state *crtc_state) @@ -808,31 +979,30 @@ static void glk_load_lut_ext2_max(const struct intel_crtc_state *crtc_state) enum pipe pipe = crtc->pipe; /* Program the max register to clamp values > 1.0. */ - intel_dsb_reg_write(crtc_state, PREC_PAL_EXT2_GC_MAX(pipe, 0), 1 << 16); - intel_dsb_reg_write(crtc_state, PREC_PAL_EXT2_GC_MAX(pipe, 1), 1 << 16); - intel_dsb_reg_write(crtc_state, PREC_PAL_EXT2_GC_MAX(pipe, 2), 1 << 16); + ilk_lut_write(crtc_state, PREC_PAL_EXT2_GC_MAX(pipe, 0), 1 << 16); + ilk_lut_write(crtc_state, PREC_PAL_EXT2_GC_MAX(pipe, 1), 1 << 16); + ilk_lut_write(crtc_state, PREC_PAL_EXT2_GC_MAX(pipe, 2), 1 << 16); } static void ivb_load_luts(const struct intel_crtc_state *crtc_state) { - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); const struct drm_property_blob *post_csc_lut = crtc_state->post_csc_lut; const struct drm_property_blob *pre_csc_lut = crtc_state->pre_csc_lut; const struct drm_property_blob *blob = post_csc_lut ?: pre_csc_lut; switch (crtc_state->gamma_mode) { case GAMMA_MODE_MODE_8BIT: - ilk_load_lut_8(crtc, blob); + ilk_load_lut_8(crtc_state, blob); break; case GAMMA_MODE_MODE_SPLIT: - ivb_load_lut_10(crtc, pre_csc_lut, PAL_PREC_SPLIT_MODE | + ivb_load_lut_10(crtc_state, pre_csc_lut, PAL_PREC_SPLIT_MODE | PAL_PREC_INDEX_VALUE(0)); ivb_load_lut_ext_max(crtc_state); - ivb_load_lut_10(crtc, post_csc_lut, PAL_PREC_SPLIT_MODE | + ivb_load_lut_10(crtc_state, post_csc_lut, PAL_PREC_SPLIT_MODE | PAL_PREC_INDEX_VALUE(512)); break; case GAMMA_MODE_MODE_10BIT: - ivb_load_lut_10(crtc, blob, + ivb_load_lut_10(crtc_state, blob, PAL_PREC_INDEX_VALUE(0)); ivb_load_lut_ext_max(crtc_state); break; @@ -844,25 +1014,23 @@ static void ivb_load_luts(const struct intel_crtc_state *crtc_state) static void bdw_load_luts(const struct intel_crtc_state *crtc_state) { - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); const struct drm_property_blob *post_csc_lut = crtc_state->post_csc_lut; const struct drm_property_blob *pre_csc_lut = crtc_state->pre_csc_lut; const struct drm_property_blob *blob = post_csc_lut ?: pre_csc_lut; switch (crtc_state->gamma_mode) { case GAMMA_MODE_MODE_8BIT: - ilk_load_lut_8(crtc, blob); + ilk_load_lut_8(crtc_state, blob); break; case GAMMA_MODE_MODE_SPLIT: - bdw_load_lut_10(crtc, pre_csc_lut, PAL_PREC_SPLIT_MODE | + bdw_load_lut_10(crtc_state, pre_csc_lut, PAL_PREC_SPLIT_MODE | PAL_PREC_INDEX_VALUE(0)); ivb_load_lut_ext_max(crtc_state); - bdw_load_lut_10(crtc, post_csc_lut, PAL_PREC_SPLIT_MODE | + bdw_load_lut_10(crtc_state, post_csc_lut, PAL_PREC_SPLIT_MODE | PAL_PREC_INDEX_VALUE(512)); break; case GAMMA_MODE_MODE_10BIT: - - bdw_load_lut_10(crtc, blob, + bdw_load_lut_10(crtc_state, blob, PAL_PREC_INDEX_VALUE(0)); ivb_load_lut_ext_max(crtc_state); break; @@ -894,9 +1062,11 @@ static void glk_load_degamma_lut(const struct intel_crtc_state *crtc_state, * ignore the index bits, so we need to reset it to index 0 * separately. */ - intel_de_write_fw(i915, PRE_CSC_GAMC_INDEX(pipe), 0); - intel_de_write_fw(i915, PRE_CSC_GAMC_INDEX(pipe), - PRE_CSC_GAMC_AUTO_INCREMENT); + ilk_lut_write(crtc_state, PRE_CSC_GAMC_INDEX(pipe), + PRE_CSC_GAMC_INDEX_VALUE(0)); + ilk_lut_write(crtc_state, PRE_CSC_GAMC_INDEX(pipe), + PRE_CSC_GAMC_AUTO_INCREMENT | + PRE_CSC_GAMC_INDEX_VALUE(0)); for (i = 0; i < lut_size; i++) { /* @@ -912,32 +1082,31 @@ static void glk_load_degamma_lut(const struct intel_crtc_state *crtc_state, * ToDo: Extend to max 7.0. Enable 32 bit input value * as compared to just 16 to achieve this. */ - intel_de_write_fw(i915, PRE_CSC_GAMC_DATA(pipe), - lut[i].green); + ilk_lut_write(crtc_state, PRE_CSC_GAMC_DATA(pipe), + lut[i].green); } /* Clamp values > 1.0. */ while (i++ < glk_degamma_lut_size(i915)) - intel_de_write_fw(i915, PRE_CSC_GAMC_DATA(pipe), 1 << 16); + ilk_lut_write(crtc_state, PRE_CSC_GAMC_DATA(pipe), 1 << 16); - intel_de_write_fw(i915, PRE_CSC_GAMC_INDEX(pipe), 0); + ilk_lut_write(crtc_state, PRE_CSC_GAMC_INDEX(pipe), 0); } static void glk_load_luts(const struct intel_crtc_state *crtc_state) { const struct drm_property_blob *pre_csc_lut = crtc_state->pre_csc_lut; const struct drm_property_blob *post_csc_lut = crtc_state->post_csc_lut; - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); if (pre_csc_lut) glk_load_degamma_lut(crtc_state, pre_csc_lut); switch (crtc_state->gamma_mode) { case GAMMA_MODE_MODE_8BIT: - ilk_load_lut_8(crtc, post_csc_lut); + ilk_load_lut_8(crtc_state, post_csc_lut); break; case GAMMA_MODE_MODE_10BIT: - bdw_load_lut_10(crtc, post_csc_lut, PAL_PREC_INDEX_VALUE(0)); + bdw_load_lut_10(crtc_state, post_csc_lut, PAL_PREC_INDEX_VALUE(0)); ivb_load_lut_ext_max(crtc_state); glk_load_lut_ext2_max(crtc_state); break; @@ -955,9 +1124,9 @@ ivb_load_lut_max(const struct intel_crtc_state *crtc_state, enum pipe pipe = crtc->pipe; /* FIXME LUT entries are 16 bit only, so we can prog 0xFFFF max */ - intel_dsb_reg_write(crtc_state, PREC_PAL_GC_MAX(pipe, 0), color->red); - intel_dsb_reg_write(crtc_state, PREC_PAL_GC_MAX(pipe, 1), color->green); - intel_dsb_reg_write(crtc_state, PREC_PAL_GC_MAX(pipe, 2), color->blue); + ilk_lut_write(crtc_state, PREC_PAL_GC_MAX(pipe, 0), color->red); + ilk_lut_write(crtc_state, PREC_PAL_GC_MAX(pipe, 1), color->green); + ilk_lut_write(crtc_state, PREC_PAL_GC_MAX(pipe, 2), color->blue); } static void @@ -976,17 +1145,23 @@ icl_program_gamma_superfine_segment(const struct intel_crtc_state *crtc_state) * 9 entries, corresponding to values 0, 1/(8 * 128 * 256), * 2/(8 * 128 * 256) ... 8/(8 * 128 * 256). */ - intel_dsb_reg_write(crtc_state, PREC_PAL_MULTI_SEG_INDEX(pipe), - PAL_PREC_AUTO_INCREMENT); + ilk_lut_write(crtc_state, PREC_PAL_MULTI_SEG_INDEX(pipe), + PAL_PREC_MULTI_SEG_INDEX_VALUE(0)); + ilk_lut_write(crtc_state, PREC_PAL_MULTI_SEG_INDEX(pipe), + PAL_PREC_AUTO_INCREMENT | + PAL_PREC_MULTI_SEG_INDEX_VALUE(0)); for (i = 0; i < 9; i++) { const struct drm_color_lut *entry = &lut[i]; - intel_dsb_indexed_reg_write(crtc_state, PREC_PAL_MULTI_SEG_DATA(pipe), - ilk_lut_12p4_ldw(entry)); - intel_dsb_indexed_reg_write(crtc_state, PREC_PAL_MULTI_SEG_DATA(pipe), - ilk_lut_12p4_udw(entry)); + ilk_lut_write(crtc_state, PREC_PAL_MULTI_SEG_DATA(pipe), + ilk_lut_12p4_ldw(entry)); + ilk_lut_write(crtc_state, PREC_PAL_MULTI_SEG_DATA(pipe), + ilk_lut_12p4_udw(entry)); } + + ilk_lut_write(crtc_state, PREC_PAL_MULTI_SEG_INDEX(pipe), + PAL_PREC_MULTI_SEG_INDEX_VALUE(0)); } static void @@ -1009,14 +1184,19 @@ icl_program_gamma_multi_segment(const struct intel_crtc_state *crtc_state) * PAL_PREC_INDEX[0] and PAL_PREC_INDEX[1] map to seg2[1], * seg2[0] being unused by the hardware. */ - intel_dsb_reg_write(crtc_state, PREC_PAL_INDEX(pipe), - PAL_PREC_AUTO_INCREMENT); + ilk_lut_write(crtc_state, PREC_PAL_INDEX(pipe), + PAL_PREC_INDEX_VALUE(0)); + ilk_lut_write(crtc_state, PREC_PAL_INDEX(pipe), + PAL_PREC_AUTO_INCREMENT | + PAL_PREC_INDEX_VALUE(0)); + for (i = 1; i < 257; i++) { entry = &lut[i * 8]; - intel_dsb_indexed_reg_write(crtc_state, PREC_PAL_DATA(pipe), - ilk_lut_12p4_ldw(entry)); - intel_dsb_indexed_reg_write(crtc_state, PREC_PAL_DATA(pipe), - ilk_lut_12p4_udw(entry)); + + ilk_lut_write(crtc_state, PREC_PAL_DATA(pipe), + ilk_lut_12p4_ldw(entry)); + ilk_lut_write(crtc_state, PREC_PAL_DATA(pipe), + ilk_lut_12p4_udw(entry)); } /* @@ -1033,12 +1213,16 @@ icl_program_gamma_multi_segment(const struct intel_crtc_state *crtc_state) */ for (i = 0; i < 256; i++) { entry = &lut[i * 8 * 128]; - intel_dsb_indexed_reg_write(crtc_state, PREC_PAL_DATA(pipe), - ilk_lut_12p4_ldw(entry)); - intel_dsb_indexed_reg_write(crtc_state, PREC_PAL_DATA(pipe), - ilk_lut_12p4_udw(entry)); + + ilk_lut_write(crtc_state, PREC_PAL_DATA(pipe), + ilk_lut_12p4_ldw(entry)); + ilk_lut_write(crtc_state, PREC_PAL_DATA(pipe), + ilk_lut_12p4_udw(entry)); } + ilk_lut_write(crtc_state, PREC_PAL_INDEX(pipe), + PAL_PREC_INDEX_VALUE(0)); + /* The last entry in the LUT is to be programmed in GCMAX */ entry = &lut[256 * 8 * 128]; ivb_load_lut_max(crtc_state, entry); @@ -1048,23 +1232,22 @@ static void icl_load_luts(const struct intel_crtc_state *crtc_state) { const struct drm_property_blob *pre_csc_lut = crtc_state->pre_csc_lut; const struct drm_property_blob *post_csc_lut = crtc_state->post_csc_lut; - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); if (pre_csc_lut) glk_load_degamma_lut(crtc_state, pre_csc_lut); switch (crtc_state->gamma_mode & GAMMA_MODE_MODE_MASK) { case GAMMA_MODE_MODE_8BIT: - ilk_load_lut_8(crtc, post_csc_lut); + ilk_load_lut_8(crtc_state, post_csc_lut); break; - case GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED: + case GAMMA_MODE_MODE_12BIT_MULTI_SEG: icl_program_gamma_superfine_segment(crtc_state); icl_program_gamma_multi_segment(crtc_state); ivb_load_lut_ext_max(crtc_state); glk_load_lut_ext2_max(crtc_state); break; case GAMMA_MODE_MODE_10BIT: - bdw_load_lut_10(crtc, post_csc_lut, PAL_PREC_INDEX_VALUE(0)); + bdw_load_lut_10(crtc_state, post_csc_lut, PAL_PREC_INDEX_VALUE(0)); ivb_load_lut_ext_max(crtc_state); glk_load_lut_ext2_max(crtc_state); break; @@ -1073,7 +1256,8 @@ static void icl_load_luts(const struct intel_crtc_state *crtc_state) break; } - intel_dsb_commit(crtc_state); + if (crtc_state->dsb) + intel_dsb_commit(crtc_state->dsb); } static u32 chv_cgm_degamma_ldw(const struct drm_color_lut *color) @@ -1087,6 +1271,13 @@ static u32 chv_cgm_degamma_udw(const struct drm_color_lut *color) return REG_FIELD_PREP(CGM_PIPE_DEGAMMA_RED_UDW_MASK, drm_color_lut_extract(color->red, 14)); } +static void chv_cgm_degamma_pack(struct drm_color_lut *entry, u32 ldw, u32 udw) +{ + entry->green = intel_color_lut_pack(REG_FIELD_GET(CGM_PIPE_DEGAMMA_GREEN_LDW_MASK, ldw), 14); + entry->blue = intel_color_lut_pack(REG_FIELD_GET(CGM_PIPE_DEGAMMA_BLUE_LDW_MASK, ldw), 14); + entry->red = intel_color_lut_pack(REG_FIELD_GET(CGM_PIPE_DEGAMMA_RED_UDW_MASK, udw), 14); +} + static void chv_load_cgm_degamma(struct intel_crtc *crtc, const struct drm_property_blob *blob) { @@ -1182,6 +1373,25 @@ void intel_color_commit_arm(const struct intel_crtc_state *crtc_state) i915->display.funcs.color->color_commit_arm(crtc_state); } +void intel_color_prepare_commit(struct intel_crtc_state *crtc_state) +{ + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); + + /* FIXME DSB has issues loading LUTs, disable it for now */ + return; + + crtc_state->dsb = intel_dsb_prepare(crtc, 1024); +} + +void intel_color_cleanup_commit(struct intel_crtc_state *crtc_state) +{ + if (!crtc_state->dsb) + return; + + intel_dsb_cleanup(crtc_state->dsb); + crtc_state->dsb = NULL; +} + static bool intel_can_preload_luts(const struct intel_crtc_state *new_crtc_state) { struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); @@ -1224,8 +1434,25 @@ void intel_color_get_config(struct intel_crtc_state *crtc_state) { struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); - if (i915->display.funcs.color->read_luts) - i915->display.funcs.color->read_luts(crtc_state); + i915->display.funcs.color->read_luts(crtc_state); +} + +bool intel_color_lut_equal(const struct intel_crtc_state *crtc_state, + const struct drm_property_blob *blob1, + const struct drm_property_blob *blob2, + bool is_pre_csc_lut) +{ + struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); + + /* + * FIXME c8_planes readout missing thus + * .read_luts() doesn't read out post_csc_lut. + */ + if (!is_pre_csc_lut && crtc_state->c8_planes) + return true; + + return i915->display.funcs.color->lut_equal(crtc_state, blob1, blob2, + is_pre_csc_lut); } static bool need_plane_update(struct intel_plane *plane, @@ -1282,6 +1509,42 @@ intel_color_add_affected_planes(struct intel_crtc_state *new_crtc_state) return 0; } +static u32 intel_gamma_lut_tests(const struct intel_crtc_state *crtc_state) +{ + struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); + const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut; + + if (lut_is_legacy(gamma_lut)) + return 0; + + return INTEL_INFO(i915)->display.color.gamma_lut_tests; +} + +static u32 intel_degamma_lut_tests(const struct intel_crtc_state *crtc_state) +{ + struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); + + return INTEL_INFO(i915)->display.color.degamma_lut_tests; +} + +static int intel_gamma_lut_size(const struct intel_crtc_state *crtc_state) +{ + struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); + const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut; + + if (lut_is_legacy(gamma_lut)) + return LEGACY_LUT_LENGTH; + + return INTEL_INFO(i915)->display.color.gamma_lut_size; +} + +static u32 intel_degamma_lut_size(const struct intel_crtc_state *crtc_state) +{ + struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); + + return INTEL_INFO(i915)->display.color.degamma_lut_size; +} + static int check_lut_size(const struct drm_property_blob *lut, int expected) { int len; @@ -1299,29 +1562,23 @@ static int check_lut_size(const struct drm_property_blob *lut, int expected) return 0; } -static int check_luts(const struct intel_crtc_state *crtc_state) +static int _check_luts(const struct intel_crtc_state *crtc_state, + u32 degamma_tests, u32 gamma_tests) { struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut; const struct drm_property_blob *degamma_lut = crtc_state->hw.degamma_lut; int gamma_length, degamma_length; - u32 gamma_tests, degamma_tests; - - /* Always allow legacy gamma LUT with no further checking. */ - if (crtc_state_is_legacy_gamma(crtc_state)) - return 0; /* C8 relies on its palette being stored in the legacy LUT */ - if (crtc_state->c8_planes) { + if (crtc_state->c8_planes && !lut_is_legacy(crtc_state->hw.gamma_lut)) { drm_dbg_kms(&i915->drm, "C8 pixelformat requires the legacy LUT\n"); return -EINVAL; } - degamma_length = INTEL_INFO(i915)->display.color.degamma_lut_size; - gamma_length = INTEL_INFO(i915)->display.color.gamma_lut_size; - degamma_tests = INTEL_INFO(i915)->display.color.degamma_lut_tests; - gamma_tests = INTEL_INFO(i915)->display.color.gamma_lut_tests; + degamma_length = intel_degamma_lut_size(crtc_state); + gamma_length = intel_gamma_lut_size(crtc_state); if (check_lut_size(degamma_lut, degamma_length) || check_lut_size(gamma_lut, gamma_length)) @@ -1334,13 +1591,44 @@ static int check_luts(const struct intel_crtc_state *crtc_state) return 0; } +static int check_luts(const struct intel_crtc_state *crtc_state) +{ + return _check_luts(crtc_state, + intel_degamma_lut_tests(crtc_state), + intel_gamma_lut_tests(crtc_state)); +} + static u32 i9xx_gamma_mode(struct intel_crtc_state *crtc_state) { if (!crtc_state->gamma_enable || - crtc_state_is_legacy_gamma(crtc_state)) + lut_is_legacy(crtc_state->hw.gamma_lut)) return GAMMA_MODE_MODE_8BIT; else - return GAMMA_MODE_MODE_10BIT; /* i965+ only */ + return GAMMA_MODE_MODE_10BIT; +} + +static int i9xx_lut_10_diff(u16 a, u16 b) +{ + return drm_color_lut_extract(a, 10) - + drm_color_lut_extract(b, 10); +} + +static int i9xx_check_lut_10(struct drm_i915_private *dev_priv, + const struct drm_property_blob *blob) +{ + const struct drm_color_lut *lut = blob->data; + int lut_size = drm_color_lut_size(blob); + const struct drm_color_lut *a = &lut[lut_size - 2]; + const struct drm_color_lut *b = &lut[lut_size - 1]; + + if (i9xx_lut_10_diff(b->red, a->red) > 0x7f || + i9xx_lut_10_diff(b->green, a->green) > 0x7f || + i9xx_lut_10_diff(b->blue, a->blue) > 0x7f) { + drm_dbg_kms(&dev_priv->drm, "Last gamma LUT entry exceeds max slope\n"); + return -EINVAL; + } + + return 0; } void intel_color_assert_luts(const struct intel_crtc_state *crtc_state) @@ -1355,15 +1643,19 @@ void intel_color_assert_luts(const struct intel_crtc_state *crtc_state) crtc_state->post_csc_lut != crtc_state->hw.gamma_lut); } else if (DISPLAY_VER(i915) == 10) { drm_WARN_ON(&i915->drm, + crtc_state->post_csc_lut == crtc_state->hw.gamma_lut && crtc_state->pre_csc_lut != crtc_state->hw.degamma_lut && crtc_state->pre_csc_lut != i915->display.color.glk_linear_degamma_lut); drm_WARN_ON(&i915->drm, + !ilk_lut_limited_range(crtc_state) && + crtc_state->post_csc_lut != NULL && crtc_state->post_csc_lut != crtc_state->hw.gamma_lut); } else if (crtc_state->gamma_mode != GAMMA_MODE_MODE_SPLIT) { drm_WARN_ON(&i915->drm, crtc_state->pre_csc_lut != crtc_state->hw.degamma_lut && crtc_state->pre_csc_lut != crtc_state->hw.gamma_lut); drm_WARN_ON(&i915->drm, + !ilk_lut_limited_range(crtc_state) && crtc_state->post_csc_lut != crtc_state->hw.degamma_lut && crtc_state->post_csc_lut != crtc_state->hw.gamma_lut); } @@ -1379,6 +1671,7 @@ static void intel_assign_luts(struct intel_crtc_state *crtc_state) static int i9xx_color_check(struct intel_crtc_state *crtc_state) { + struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); int ret; ret = check_luts(crtc_state); @@ -1391,6 +1684,13 @@ static int i9xx_color_check(struct intel_crtc_state *crtc_state) crtc_state->gamma_mode = i9xx_gamma_mode(crtc_state); + if (DISPLAY_VER(i915) < 4 && + crtc_state->gamma_mode == GAMMA_MODE_MODE_10BIT) { + ret = i9xx_check_lut_10(i915, crtc_state->hw.gamma_lut); + if (ret) + return ret; + } + ret = intel_color_add_affected_planes(crtc_state); if (ret) return ret; @@ -1406,14 +1706,12 @@ static u32 chv_cgm_mode(const struct intel_crtc_state *crtc_state) { u32 cgm_mode = 0; - if (crtc_state_is_legacy_gamma(crtc_state)) - return 0; - if (crtc_state->hw.degamma_lut) cgm_mode |= CGM_PIPE_MODE_DEGAMMA; if (crtc_state->hw.ctm) cgm_mode |= CGM_PIPE_MODE_CSC; - if (crtc_state->hw.gamma_lut) + if (crtc_state->hw.gamma_lut && + !lut_is_legacy(crtc_state->hw.gamma_lut)) cgm_mode |= CGM_PIPE_MODE_GAMMA; return cgm_mode; @@ -1440,7 +1738,7 @@ static int chv_color_check(struct intel_crtc_state *crtc_state) * Otherwise we bypass it and use the CGM gamma instead. */ crtc_state->gamma_enable = - crtc_state_is_legacy_gamma(crtc_state) && + lut_is_legacy(crtc_state->hw.gamma_lut) && !crtc_state->c8_planes; crtc_state->gamma_mode = GAMMA_MODE_MODE_8BIT; @@ -1475,7 +1773,7 @@ static bool ilk_csc_enable(const struct intel_crtc_state *crtc_state) static u32 ilk_gamma_mode(const struct intel_crtc_state *crtc_state) { if (!crtc_state->gamma_enable || - crtc_state_is_legacy_gamma(crtc_state)) + lut_is_legacy(crtc_state->hw.gamma_lut)) return GAMMA_MODE_MODE_8BIT; else return GAMMA_MODE_MODE_10BIT; @@ -1499,8 +1797,28 @@ static u32 ilk_csc_mode(const struct intel_crtc_state *crtc_state) CSC_POSITION_BEFORE_GAMMA; } -static void ilk_assign_luts(struct intel_crtc_state *crtc_state) +static int ilk_assign_luts(struct intel_crtc_state *crtc_state) { + struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); + + if (ilk_lut_limited_range(crtc_state)) { + struct drm_property_blob *gamma_lut; + + gamma_lut = create_resized_lut(i915, crtc_state->hw.gamma_lut, + drm_color_lut_size(crtc_state->hw.gamma_lut), + true); + if (IS_ERR(gamma_lut)) + return PTR_ERR(gamma_lut); + + drm_property_replace_blob(&crtc_state->post_csc_lut, gamma_lut); + + drm_property_blob_put(gamma_lut); + + drm_property_replace_blob(&crtc_state->pre_csc_lut, crtc_state->hw.degamma_lut); + + return 0; + } + if (crtc_state->hw.degamma_lut || crtc_state->csc_mode & CSC_POSITION_BEFORE_GAMMA) { drm_property_replace_blob(&crtc_state->pre_csc_lut, @@ -1513,6 +1831,8 @@ static void ilk_assign_luts(struct intel_crtc_state *crtc_state) drm_property_replace_blob(&crtc_state->post_csc_lut, NULL); } + + return 0; } static int ilk_color_check(struct intel_crtc_state *crtc_state) @@ -1549,7 +1869,9 @@ static int ilk_color_check(struct intel_crtc_state *crtc_state) if (ret) return ret; - ilk_assign_luts(crtc_state); + ret = ilk_assign_luts(crtc_state); + if (ret) + return ret; crtc_state->preload_luts = intel_can_preload_luts(crtc_state); @@ -1585,19 +1907,19 @@ static int ivb_assign_luts(struct intel_crtc_state *crtc_state) struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); struct drm_property_blob *degamma_lut, *gamma_lut; - if (crtc_state->gamma_mode != GAMMA_MODE_MODE_SPLIT) { - ilk_assign_luts(crtc_state); - return 0; - } + if (crtc_state->gamma_mode != GAMMA_MODE_MODE_SPLIT) + return ilk_assign_luts(crtc_state); drm_WARN_ON(&i915->drm, drm_color_lut_size(crtc_state->hw.degamma_lut) != 1024); drm_WARN_ON(&i915->drm, drm_color_lut_size(crtc_state->hw.gamma_lut) != 1024); - degamma_lut = create_resized_lut(i915, crtc_state->hw.degamma_lut, 512); + degamma_lut = create_resized_lut(i915, crtc_state->hw.degamma_lut, 512, + false); if (IS_ERR(degamma_lut)) return PTR_ERR(degamma_lut); - gamma_lut = create_resized_lut(i915, crtc_state->hw.gamma_lut, 512); + gamma_lut = create_resized_lut(i915, crtc_state->hw.gamma_lut, 512, + ilk_lut_limited_range(crtc_state)); if (IS_ERR(gamma_lut)) { drm_property_blob_put(degamma_lut); return PTR_ERR(gamma_lut); @@ -1621,6 +1943,12 @@ static int ivb_color_check(struct intel_crtc_state *crtc_state) if (ret) return ret; + if (crtc_state->c8_planes && crtc_state->hw.degamma_lut) { + drm_dbg_kms(&i915->drm, + "C8 pixelformat and degamma together are not possible\n"); + return -EINVAL; + } + if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB && crtc_state->hw.ctm) { drm_dbg_kms(&i915->drm, @@ -1659,17 +1987,57 @@ static int ivb_color_check(struct intel_crtc_state *crtc_state) static u32 glk_gamma_mode(const struct intel_crtc_state *crtc_state) { if (!crtc_state->gamma_enable || - crtc_state_is_legacy_gamma(crtc_state)) + lut_is_legacy(crtc_state->hw.gamma_lut)) return GAMMA_MODE_MODE_8BIT; else return GAMMA_MODE_MODE_10BIT; } -static void glk_assign_luts(struct intel_crtc_state *crtc_state) +static bool glk_use_pre_csc_lut_for_gamma(const struct intel_crtc_state *crtc_state) +{ + return crtc_state->hw.gamma_lut && + !crtc_state->c8_planes && + crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB; +} + +static int glk_assign_luts(struct intel_crtc_state *crtc_state) { struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); - intel_assign_luts(crtc_state); + if (glk_use_pre_csc_lut_for_gamma(crtc_state)) { + struct drm_property_blob *gamma_lut; + + gamma_lut = create_resized_lut(i915, crtc_state->hw.gamma_lut, + INTEL_INFO(i915)->display.color.degamma_lut_size, + false); + if (IS_ERR(gamma_lut)) + return PTR_ERR(gamma_lut); + + drm_property_replace_blob(&crtc_state->pre_csc_lut, gamma_lut); + drm_property_replace_blob(&crtc_state->post_csc_lut, NULL); + + drm_property_blob_put(gamma_lut); + + return 0; + } + + if (ilk_lut_limited_range(crtc_state)) { + struct drm_property_blob *gamma_lut; + + gamma_lut = create_resized_lut(i915, crtc_state->hw.gamma_lut, + drm_color_lut_size(crtc_state->hw.gamma_lut), + true); + if (IS_ERR(gamma_lut)) + return PTR_ERR(gamma_lut); + + drm_property_replace_blob(&crtc_state->post_csc_lut, gamma_lut); + + drm_property_blob_put(gamma_lut); + } else { + drm_property_replace_blob(&crtc_state->post_csc_lut, crtc_state->hw.gamma_lut); + } + + drm_property_replace_blob(&crtc_state->pre_csc_lut, crtc_state->hw.degamma_lut); /* * On GLK+ both pipe CSC and degamma LUT are controlled @@ -1680,6 +2048,19 @@ static void glk_assign_luts(struct intel_crtc_state *crtc_state) if (crtc_state->csc_enable && !crtc_state->pre_csc_lut) drm_property_replace_blob(&crtc_state->pre_csc_lut, i915->display.color.glk_linear_degamma_lut); + + return 0; +} + +static int glk_check_luts(const struct intel_crtc_state *crtc_state) +{ + u32 degamma_tests = intel_degamma_lut_tests(crtc_state); + u32 gamma_tests = intel_gamma_lut_tests(crtc_state); + + if (glk_use_pre_csc_lut_for_gamma(crtc_state)) + gamma_tests |= degamma_tests; + + return _check_luts(crtc_state, degamma_tests, gamma_tests); } static int glk_color_check(struct intel_crtc_state *crtc_state) @@ -1687,7 +2068,7 @@ static int glk_color_check(struct intel_crtc_state *crtc_state) struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); int ret; - ret = check_luts(crtc_state); + ret = glk_check_luts(crtc_state); if (ret) return ret; @@ -1706,14 +2087,16 @@ static int glk_color_check(struct intel_crtc_state *crtc_state) } crtc_state->gamma_enable = + !glk_use_pre_csc_lut_for_gamma(crtc_state) && crtc_state->hw.gamma_lut && !crtc_state->c8_planes; /* On GLK+ degamma LUT is controlled by csc_enable */ crtc_state->csc_enable = + glk_use_pre_csc_lut_for_gamma(crtc_state) || crtc_state->hw.degamma_lut || crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB || - crtc_state->hw.ctm || crtc_state->limited_color_range; + crtc_state->hw.ctm || ilk_csc_limited_range(crtc_state); crtc_state->gamma_mode = glk_gamma_mode(crtc_state); @@ -1723,7 +2106,9 @@ static int glk_color_check(struct intel_crtc_state *crtc_state) if (ret) return ret; - glk_assign_luts(crtc_state); + ret = glk_assign_luts(crtc_state); + if (ret) + return ret; crtc_state->preload_luts = intel_can_preload_luts(crtc_state); @@ -1744,7 +2129,7 @@ static u32 icl_gamma_mode(const struct intel_crtc_state *crtc_state) gamma_mode |= POST_CSC_GAMMA_ENABLE; if (!crtc_state->hw.gamma_lut || - crtc_state_is_legacy_gamma(crtc_state)) + lut_is_legacy(crtc_state->hw.gamma_lut)) gamma_mode |= GAMMA_MODE_MODE_8BIT; /* * Enable 10bit gamma for D13 @@ -1754,7 +2139,7 @@ static u32 icl_gamma_mode(const struct intel_crtc_state *crtc_state) else if (DISPLAY_VER(i915) >= 13) gamma_mode |= GAMMA_MODE_MODE_10BIT; else - gamma_mode |= GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED; + gamma_mode |= GAMMA_MODE_MODE_12BIT_MULTI_SEG; return gamma_mode; } @@ -1792,68 +2177,153 @@ static int icl_color_check(struct intel_crtc_state *crtc_state) return 0; } -static int i9xx_gamma_precision(const struct intel_crtc_state *crtc_state) +static int i9xx_post_csc_lut_precision(const struct intel_crtc_state *crtc_state) { - if (!crtc_state->gamma_enable) + if (!crtc_state->gamma_enable && !crtc_state->c8_planes) return 0; switch (crtc_state->gamma_mode) { case GAMMA_MODE_MODE_8BIT: return 8; case GAMMA_MODE_MODE_10BIT: - return 16; + return 10; default: MISSING_CASE(crtc_state->gamma_mode); return 0; } } -static int ilk_gamma_precision(const struct intel_crtc_state *crtc_state) +static int i9xx_pre_csc_lut_precision(const struct intel_crtc_state *crtc_state) { - if (!crtc_state->gamma_enable) - return 0; + return 0; +} - if ((crtc_state->csc_mode & CSC_POSITION_BEFORE_GAMMA) == 0) +static int i965_post_csc_lut_precision(const struct intel_crtc_state *crtc_state) +{ + if (!crtc_state->gamma_enable && !crtc_state->c8_planes) return 0; switch (crtc_state->gamma_mode) { case GAMMA_MODE_MODE_8BIT: return 8; case GAMMA_MODE_MODE_10BIT: - return 10; + return 16; default: MISSING_CASE(crtc_state->gamma_mode); return 0; } } -static int chv_gamma_precision(const struct intel_crtc_state *crtc_state) +static int ilk_gamma_mode_precision(u32 gamma_mode) { - if (crtc_state->cgm_mode & CGM_PIPE_MODE_GAMMA) + switch (gamma_mode) { + case GAMMA_MODE_MODE_8BIT: + return 8; + case GAMMA_MODE_MODE_10BIT: return 10; - else - return i9xx_gamma_precision(crtc_state); + default: + MISSING_CASE(gamma_mode); + return 0; + } +} + +static bool ilk_has_post_csc_lut(const struct intel_crtc_state *crtc_state) +{ + if (crtc_state->c8_planes) + return true; + + return crtc_state->gamma_enable && + (crtc_state->csc_mode & CSC_POSITION_BEFORE_GAMMA) != 0; +} + +static bool ilk_has_pre_csc_lut(const struct intel_crtc_state *crtc_state) +{ + return crtc_state->gamma_enable && + (crtc_state->csc_mode & CSC_POSITION_BEFORE_GAMMA) == 0; } -static int glk_gamma_precision(const struct intel_crtc_state *crtc_state) +static int ilk_post_csc_lut_precision(const struct intel_crtc_state *crtc_state) { - if (!crtc_state->gamma_enable) + if (!ilk_has_post_csc_lut(crtc_state)) return 0; - switch (crtc_state->gamma_mode) { - case GAMMA_MODE_MODE_8BIT: - return 8; - case GAMMA_MODE_MODE_10BIT: + return ilk_gamma_mode_precision(crtc_state->gamma_mode); +} + +static int ilk_pre_csc_lut_precision(const struct intel_crtc_state *crtc_state) +{ + if (!ilk_has_pre_csc_lut(crtc_state)) + return 0; + + return ilk_gamma_mode_precision(crtc_state->gamma_mode); +} + +static int ivb_post_csc_lut_precision(const struct intel_crtc_state *crtc_state) +{ + if (crtc_state->gamma_enable && + crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT) return 10; - default: - MISSING_CASE(crtc_state->gamma_mode); + + return ilk_post_csc_lut_precision(crtc_state); +} + +static int ivb_pre_csc_lut_precision(const struct intel_crtc_state *crtc_state) +{ + if (crtc_state->gamma_enable && + crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT) + return 10; + + return ilk_pre_csc_lut_precision(crtc_state); +} + +static int chv_post_csc_lut_precision(const struct intel_crtc_state *crtc_state) +{ + if (crtc_state->cgm_mode & CGM_PIPE_MODE_GAMMA) + return 10; + + return i965_post_csc_lut_precision(crtc_state); +} + +static int chv_pre_csc_lut_precision(const struct intel_crtc_state *crtc_state) +{ + if (crtc_state->cgm_mode & CGM_PIPE_MODE_DEGAMMA) + return 14; + + return 0; +} + +static int glk_post_csc_lut_precision(const struct intel_crtc_state *crtc_state) +{ + if (!crtc_state->gamma_enable && !crtc_state->c8_planes) return 0; - } + + return ilk_gamma_mode_precision(crtc_state->gamma_mode); } -static int icl_gamma_precision(const struct intel_crtc_state *crtc_state) +static int glk_pre_csc_lut_precision(const struct intel_crtc_state *crtc_state) { - if ((crtc_state->gamma_mode & POST_CSC_GAMMA_ENABLE) == 0) + if (!crtc_state->csc_enable) + return 0; + + return 16; +} + +static bool icl_has_post_csc_lut(const struct intel_crtc_state *crtc_state) +{ + if (crtc_state->c8_planes) + return true; + + return crtc_state->gamma_mode & POST_CSC_GAMMA_ENABLE; +} + +static bool icl_has_pre_csc_lut(const struct intel_crtc_state *crtc_state) +{ + return crtc_state->gamma_mode & PRE_CSC_GAMMA_ENABLE; +} + +static int icl_post_csc_lut_precision(const struct intel_crtc_state *crtc_state) +{ + if (!icl_has_post_csc_lut(crtc_state)) return 0; switch (crtc_state->gamma_mode & GAMMA_MODE_MODE_MASK) { @@ -1861,7 +2331,7 @@ static int icl_gamma_precision(const struct intel_crtc_state *crtc_state) return 8; case GAMMA_MODE_MODE_10BIT: return 10; - case GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED: + case GAMMA_MODE_MODE_12BIT_MULTI_SEG: return 16; default: MISSING_CASE(crtc_state->gamma_mode); @@ -1869,26 +2339,12 @@ static int icl_gamma_precision(const struct intel_crtc_state *crtc_state) } } -int intel_color_get_gamma_bit_precision(const struct intel_crtc_state *crtc_state) +static int icl_pre_csc_lut_precision(const struct intel_crtc_state *crtc_state) { - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - struct drm_i915_private *i915 = to_i915(crtc->base.dev); - - if (HAS_GMCH(i915)) { - if (IS_CHERRYVIEW(i915)) - return chv_gamma_precision(crtc_state); - else - return i9xx_gamma_precision(crtc_state); - } else { - if (DISPLAY_VER(i915) >= 11) - return icl_gamma_precision(crtc_state); - else if (DISPLAY_VER(i915) == 10) - return glk_gamma_precision(crtc_state); - else if (IS_IRONLAKE(i915)) - return ilk_gamma_precision(crtc_state); - } + if (!icl_has_pre_csc_lut(crtc_state)) + return 0; - return 0; + return 16; } static bool err_check(struct drm_color_lut *lut1, @@ -1899,9 +2355,9 @@ static bool err_check(struct drm_color_lut *lut1, ((abs((long)lut2->green - lut1->green)) <= err); } -static bool intel_color_lut_entries_equal(struct drm_color_lut *lut1, - struct drm_color_lut *lut2, - int lut_size, u32 err) +static bool intel_lut_entries_equal(struct drm_color_lut *lut1, + struct drm_color_lut *lut2, + int lut_size, u32 err) { int i; @@ -1913,9 +2369,9 @@ static bool intel_color_lut_entries_equal(struct drm_color_lut *lut1, return true; } -bool intel_color_lut_equal(struct drm_property_blob *blob1, - struct drm_property_blob *blob2, - u32 gamma_mode, u32 bit_precision) +static bool intel_lut_equal(const struct drm_property_blob *blob1, + const struct drm_property_blob *blob2, + int check_size, int precision) { struct drm_color_lut *lut1, *lut2; int lut_size1, lut_size2; @@ -1924,40 +2380,134 @@ bool intel_color_lut_equal(struct drm_property_blob *blob1, if (!blob1 != !blob2) return false; + if (!blob1 != !precision) + return false; + if (!blob1) return true; lut_size1 = drm_color_lut_size(blob1); lut_size2 = drm_color_lut_size(blob2); - /* check sw and hw lut size */ if (lut_size1 != lut_size2) return false; + if (check_size > lut_size1) + return false; + lut1 = blob1->data; lut2 = blob2->data; - err = 0xffff >> bit_precision; + err = 0xffff >> precision; - /* check sw and hw lut entry to be equal */ - switch (gamma_mode & GAMMA_MODE_MODE_MASK) { - case GAMMA_MODE_MODE_8BIT: - case GAMMA_MODE_MODE_10BIT: - if (!intel_color_lut_entries_equal(lut1, lut2, - lut_size2, err)) - return false; - break; - case GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED: - if (!intel_color_lut_entries_equal(lut1, lut2, - 9, err)) - return false; - break; - default: - MISSING_CASE(gamma_mode); - return false; - } + if (!check_size) + check_size = lut_size1; - return true; + return intel_lut_entries_equal(lut1, lut2, check_size, err); +} + +static bool i9xx_lut_equal(const struct intel_crtc_state *crtc_state, + const struct drm_property_blob *blob1, + const struct drm_property_blob *blob2, + bool is_pre_csc_lut) +{ + int check_size = 0; + + if (is_pre_csc_lut) + return intel_lut_equal(blob1, blob2, 0, + i9xx_pre_csc_lut_precision(crtc_state)); + + /* 10bit mode last entry is implicit, just skip it */ + if (crtc_state->gamma_mode == GAMMA_MODE_MODE_10BIT) + check_size = 128; + + return intel_lut_equal(blob1, blob2, check_size, + i9xx_post_csc_lut_precision(crtc_state)); +} + +static bool i965_lut_equal(const struct intel_crtc_state *crtc_state, + const struct drm_property_blob *blob1, + const struct drm_property_blob *blob2, + bool is_pre_csc_lut) +{ + if (is_pre_csc_lut) + return intel_lut_equal(blob1, blob2, 0, + i9xx_pre_csc_lut_precision(crtc_state)); + else + return intel_lut_equal(blob1, blob2, 0, + i965_post_csc_lut_precision(crtc_state)); +} + +static bool chv_lut_equal(const struct intel_crtc_state *crtc_state, + const struct drm_property_blob *blob1, + const struct drm_property_blob *blob2, + bool is_pre_csc_lut) +{ + if (is_pre_csc_lut) + return intel_lut_equal(blob1, blob2, 0, + chv_pre_csc_lut_precision(crtc_state)); + else + return intel_lut_equal(blob1, blob2, 0, + chv_post_csc_lut_precision(crtc_state)); +} + +static bool ilk_lut_equal(const struct intel_crtc_state *crtc_state, + const struct drm_property_blob *blob1, + const struct drm_property_blob *blob2, + bool is_pre_csc_lut) +{ + if (is_pre_csc_lut) + return intel_lut_equal(blob1, blob2, 0, + ilk_pre_csc_lut_precision(crtc_state)); + else + return intel_lut_equal(blob1, blob2, 0, + ilk_post_csc_lut_precision(crtc_state)); +} + +static bool ivb_lut_equal(const struct intel_crtc_state *crtc_state, + const struct drm_property_blob *blob1, + const struct drm_property_blob *blob2, + bool is_pre_csc_lut) +{ + if (is_pre_csc_lut) + return intel_lut_equal(blob1, blob2, 0, + ivb_pre_csc_lut_precision(crtc_state)); + else + return intel_lut_equal(blob1, blob2, 0, + ivb_post_csc_lut_precision(crtc_state)); +} + +static bool glk_lut_equal(const struct intel_crtc_state *crtc_state, + const struct drm_property_blob *blob1, + const struct drm_property_blob *blob2, + bool is_pre_csc_lut) +{ + if (is_pre_csc_lut) + return intel_lut_equal(blob1, blob2, 0, + glk_pre_csc_lut_precision(crtc_state)); + else + return intel_lut_equal(blob1, blob2, 0, + glk_post_csc_lut_precision(crtc_state)); +} + +static bool icl_lut_equal(const struct intel_crtc_state *crtc_state, + const struct drm_property_blob *blob1, + const struct drm_property_blob *blob2, + bool is_pre_csc_lut) +{ + int check_size = 0; + + if (is_pre_csc_lut) + return intel_lut_equal(blob1, blob2, 0, + icl_pre_csc_lut_precision(crtc_state)); + + /* hw readout broken except for the super fine segment :( */ + if ((crtc_state->gamma_mode & GAMMA_MODE_MODE_MASK) == + GAMMA_MODE_MODE_12BIT_MULTI_SEG) + check_size = 9; + + return intel_lut_equal(blob1, blob2, check_size, + icl_post_csc_lut_precision(crtc_state)); } static struct drm_property_blob *i9xx_read_lut_8(struct intel_crtc *crtc) @@ -1985,14 +2535,53 @@ static struct drm_property_blob *i9xx_read_lut_8(struct intel_crtc *crtc) return blob; } +static struct drm_property_blob *i9xx_read_lut_10(struct intel_crtc *crtc) +{ + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + u32 lut_size = INTEL_INFO(dev_priv)->display.color.gamma_lut_size; + enum pipe pipe = crtc->pipe; + struct drm_property_blob *blob; + struct drm_color_lut *lut; + u32 ldw, udw; + int i; + + blob = drm_property_create_blob(&dev_priv->drm, + lut_size * sizeof(lut[0]), NULL); + if (IS_ERR(blob)) + return NULL; + + lut = blob->data; + + for (i = 0; i < lut_size - 1; i++) { + ldw = intel_de_read_fw(dev_priv, PALETTE(pipe, 2 * i + 0)); + udw = intel_de_read_fw(dev_priv, PALETTE(pipe, 2 * i + 1)); + + i9xx_lut_10_pack(&lut[i], ldw, udw); + } + + i9xx_lut_10_pack_slope(&lut[i], ldw, udw); + + return blob; +} + static void i9xx_read_luts(struct intel_crtc_state *crtc_state) { struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - if (!crtc_state->gamma_enable) + if (!crtc_state->gamma_enable && !crtc_state->c8_planes) return; - crtc_state->post_csc_lut = i9xx_read_lut_8(crtc); + switch (crtc_state->gamma_mode) { + case GAMMA_MODE_MODE_8BIT: + crtc_state->post_csc_lut = i9xx_read_lut_8(crtc); + break; + case GAMMA_MODE_MODE_10BIT: + crtc_state->post_csc_lut = i9xx_read_lut_10(crtc); + break; + default: + MISSING_CASE(crtc_state->gamma_mode); + break; + } } static struct drm_property_blob *i965_read_lut_10p6(struct intel_crtc *crtc) @@ -2029,13 +2618,46 @@ static void i965_read_luts(struct intel_crtc_state *crtc_state) { struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - if (!crtc_state->gamma_enable) + if (!crtc_state->gamma_enable && !crtc_state->c8_planes) return; - if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT) + switch (crtc_state->gamma_mode) { + case GAMMA_MODE_MODE_8BIT: crtc_state->post_csc_lut = i9xx_read_lut_8(crtc); - else + break; + case GAMMA_MODE_MODE_10BIT: crtc_state->post_csc_lut = i965_read_lut_10p6(crtc); + break; + default: + MISSING_CASE(crtc_state->gamma_mode); + break; + } +} + +static struct drm_property_blob *chv_read_cgm_degamma(struct intel_crtc *crtc) +{ + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + int i, lut_size = INTEL_INFO(dev_priv)->display.color.degamma_lut_size; + enum pipe pipe = crtc->pipe; + struct drm_property_blob *blob; + struct drm_color_lut *lut; + + blob = drm_property_create_blob(&dev_priv->drm, + sizeof(lut[0]) * lut_size, + NULL); + if (IS_ERR(blob)) + return NULL; + + lut = blob->data; + + for (i = 0; i < lut_size; i++) { + u32 ldw = intel_de_read_fw(dev_priv, CGM_PIPE_DEGAMMA(pipe, i, 0)); + u32 udw = intel_de_read_fw(dev_priv, CGM_PIPE_DEGAMMA(pipe, i, 1)); + + chv_cgm_degamma_pack(&lut[i], ldw, udw); + } + + return blob; } static struct drm_property_blob *chv_read_cgm_gamma(struct intel_crtc *crtc) @@ -2068,6 +2690,9 @@ static void chv_read_luts(struct intel_crtc_state *crtc_state) { struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); + if (crtc_state->cgm_mode & CGM_PIPE_MODE_DEGAMMA) + crtc_state->pre_csc_lut = chv_read_cgm_degamma(crtc); + if (crtc_state->cgm_mode & CGM_PIPE_MODE_GAMMA) crtc_state->post_csc_lut = chv_read_cgm_gamma(crtc); else @@ -2127,19 +2752,88 @@ static struct drm_property_blob *ilk_read_lut_10(struct intel_crtc *crtc) static void ilk_read_luts(struct intel_crtc_state *crtc_state) { struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); + struct drm_property_blob **blob = + ilk_has_post_csc_lut(crtc_state) ? + &crtc_state->post_csc_lut : &crtc_state->pre_csc_lut; - if (!crtc_state->gamma_enable) + if (!crtc_state->gamma_enable && !crtc_state->c8_planes) return; - if ((crtc_state->csc_mode & CSC_POSITION_BEFORE_GAMMA) == 0) + switch (crtc_state->gamma_mode) { + case GAMMA_MODE_MODE_8BIT: + *blob = ilk_read_lut_8(crtc); + break; + case GAMMA_MODE_MODE_10BIT: + *blob = ilk_read_lut_10(crtc); + break; + default: + MISSING_CASE(crtc_state->gamma_mode); + break; + } +} + +/* + * IVB/HSW Bspec / PAL_PREC_INDEX: + * "Restriction : Index auto increment mode is not + * supported and must not be enabled." + */ +static struct drm_property_blob *ivb_read_lut_10(struct intel_crtc *crtc, + u32 prec_index) +{ + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + int i, lut_size = ivb_lut_10_size(prec_index); + enum pipe pipe = crtc->pipe; + struct drm_property_blob *blob; + struct drm_color_lut *lut; + + blob = drm_property_create_blob(&dev_priv->drm, + sizeof(lut[0]) * lut_size, + NULL); + if (IS_ERR(blob)) + return NULL; + + lut = blob->data; + + for (i = 0; i < lut_size; i++) { + u32 val; + + intel_de_write_fw(dev_priv, PREC_PAL_INDEX(pipe), + prec_index + i); + val = intel_de_read_fw(dev_priv, PREC_PAL_DATA(pipe)); + + ilk_lut_10_pack(&lut[i], val); + } + + intel_de_write_fw(dev_priv, PREC_PAL_INDEX(pipe), + PAL_PREC_INDEX_VALUE(0)); + + return blob; +} + +static void ivb_read_luts(struct intel_crtc_state *crtc_state) +{ + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); + struct drm_property_blob **blob = + ilk_has_post_csc_lut(crtc_state) ? + &crtc_state->post_csc_lut : &crtc_state->pre_csc_lut; + + if (!crtc_state->gamma_enable && !crtc_state->c8_planes) return; switch (crtc_state->gamma_mode) { case GAMMA_MODE_MODE_8BIT: - crtc_state->post_csc_lut = ilk_read_lut_8(crtc); + *blob = ilk_read_lut_8(crtc); + break; + case GAMMA_MODE_MODE_SPLIT: + crtc_state->pre_csc_lut = + ivb_read_lut_10(crtc, PAL_PREC_SPLIT_MODE | + PAL_PREC_INDEX_VALUE(0)); + crtc_state->post_csc_lut = + ivb_read_lut_10(crtc, PAL_PREC_SPLIT_MODE | + PAL_PREC_INDEX_VALUE(512)); break; case GAMMA_MODE_MODE_10BIT: - crtc_state->post_csc_lut = ilk_read_lut_10(crtc); + *blob = ivb_read_lut_10(crtc, PAL_PREC_INDEX_VALUE(0)); break; default: MISSING_CASE(crtc_state->gamma_mode); @@ -2152,14 +2846,11 @@ static struct drm_property_blob *bdw_read_lut_10(struct intel_crtc *crtc, u32 prec_index) { struct drm_i915_private *i915 = to_i915(crtc->base.dev); - int i, hw_lut_size = ivb_lut_10_size(prec_index); - int lut_size = INTEL_INFO(i915)->display.color.gamma_lut_size; + int i, lut_size = ivb_lut_10_size(prec_index); enum pipe pipe = crtc->pipe; struct drm_property_blob *blob; struct drm_color_lut *lut; - drm_WARN_ON(&i915->drm, lut_size != hw_lut_size); - blob = drm_property_create_blob(&i915->drm, sizeof(lut[0]) * lut_size, NULL); @@ -2169,7 +2860,10 @@ static struct drm_property_blob *bdw_read_lut_10(struct intel_crtc *crtc, lut = blob->data; intel_de_write_fw(i915, PREC_PAL_INDEX(pipe), - prec_index | PAL_PREC_AUTO_INCREMENT); + prec_index); + intel_de_write_fw(i915, PREC_PAL_INDEX(pipe), + PAL_PREC_AUTO_INCREMENT | + prec_index); for (i = 0; i < lut_size; i++) { u32 val = intel_de_read_fw(i915, PREC_PAL_DATA(pipe)); @@ -2177,7 +2871,80 @@ static struct drm_property_blob *bdw_read_lut_10(struct intel_crtc *crtc, ilk_lut_10_pack(&lut[i], val); } - intel_de_write_fw(i915, PREC_PAL_INDEX(pipe), 0); + intel_de_write_fw(i915, PREC_PAL_INDEX(pipe), + PAL_PREC_INDEX_VALUE(0)); + + return blob; +} + +static void bdw_read_luts(struct intel_crtc_state *crtc_state) +{ + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); + struct drm_property_blob **blob = + ilk_has_post_csc_lut(crtc_state) ? + &crtc_state->post_csc_lut : &crtc_state->pre_csc_lut; + + if (!crtc_state->gamma_enable && !crtc_state->c8_planes) + return; + + switch (crtc_state->gamma_mode) { + case GAMMA_MODE_MODE_8BIT: + *blob = ilk_read_lut_8(crtc); + break; + case GAMMA_MODE_MODE_SPLIT: + crtc_state->pre_csc_lut = + bdw_read_lut_10(crtc, PAL_PREC_SPLIT_MODE | + PAL_PREC_INDEX_VALUE(0)); + crtc_state->post_csc_lut = + bdw_read_lut_10(crtc, PAL_PREC_SPLIT_MODE | + PAL_PREC_INDEX_VALUE(512)); + break; + case GAMMA_MODE_MODE_10BIT: + *blob = bdw_read_lut_10(crtc, PAL_PREC_INDEX_VALUE(0)); + break; + default: + MISSING_CASE(crtc_state->gamma_mode); + break; + } +} + +static struct drm_property_blob *glk_read_degamma_lut(struct intel_crtc *crtc) +{ + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + int i, lut_size = INTEL_INFO(dev_priv)->display.color.degamma_lut_size; + enum pipe pipe = crtc->pipe; + struct drm_property_blob *blob; + struct drm_color_lut *lut; + + blob = drm_property_create_blob(&dev_priv->drm, + sizeof(lut[0]) * lut_size, + NULL); + if (IS_ERR(blob)) + return NULL; + + lut = blob->data; + + /* + * When setting the auto-increment bit, the hardware seems to + * ignore the index bits, so we need to reset it to index 0 + * separately. + */ + intel_de_write_fw(dev_priv, PRE_CSC_GAMC_INDEX(pipe), + PRE_CSC_GAMC_INDEX_VALUE(0)); + intel_de_write_fw(dev_priv, PRE_CSC_GAMC_INDEX(pipe), + PRE_CSC_GAMC_AUTO_INCREMENT | + PRE_CSC_GAMC_INDEX_VALUE(0)); + + for (i = 0; i < lut_size; i++) { + u32 val = intel_de_read_fw(dev_priv, PRE_CSC_GAMC_DATA(pipe)); + + lut[i].red = val; + lut[i].green = val; + lut[i].blue = val; + } + + intel_de_write_fw(dev_priv, PRE_CSC_GAMC_INDEX(pipe), + PRE_CSC_GAMC_INDEX_VALUE(0)); return blob; } @@ -2186,7 +2953,10 @@ static void glk_read_luts(struct intel_crtc_state *crtc_state) { struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - if (!crtc_state->gamma_enable) + if (crtc_state->csc_enable) + crtc_state->pre_csc_lut = glk_read_degamma_lut(crtc); + + if (!crtc_state->gamma_enable && !crtc_state->c8_planes) return; switch (crtc_state->gamma_mode) { @@ -2220,7 +2990,10 @@ icl_read_lut_multi_segment(struct intel_crtc *crtc) lut = blob->data; intel_de_write_fw(i915, PREC_PAL_MULTI_SEG_INDEX(pipe), - PAL_PREC_AUTO_INCREMENT); + PAL_PREC_MULTI_SEG_INDEX_VALUE(0)); + intel_de_write_fw(i915, PREC_PAL_MULTI_SEG_INDEX(pipe), + PAL_PREC_MULTI_SEG_AUTO_INCREMENT | + PAL_PREC_MULTI_SEG_INDEX_VALUE(0)); for (i = 0; i < 9; i++) { u32 ldw = intel_de_read_fw(i915, PREC_PAL_MULTI_SEG_DATA(pipe)); @@ -2229,7 +3002,8 @@ icl_read_lut_multi_segment(struct intel_crtc *crtc) ilk_lut_12p4_pack(&lut[i], ldw, udw); } - intel_de_write_fw(i915, PREC_PAL_MULTI_SEG_INDEX(pipe), 0); + intel_de_write_fw(i915, PREC_PAL_MULTI_SEG_INDEX(pipe), + PAL_PREC_MULTI_SEG_INDEX_VALUE(0)); /* * FIXME readouts from PAL_PREC_DATA register aren't giving @@ -2244,7 +3018,10 @@ static void icl_read_luts(struct intel_crtc_state *crtc_state) { struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - if ((crtc_state->gamma_mode & POST_CSC_GAMMA_ENABLE) == 0) + if (icl_has_pre_csc_lut(crtc_state)) + crtc_state->pre_csc_lut = glk_read_degamma_lut(crtc); + + if (!icl_has_post_csc_lut(crtc_state)) return; switch (crtc_state->gamma_mode & GAMMA_MODE_MODE_MASK) { @@ -2254,7 +3031,7 @@ static void icl_read_luts(struct intel_crtc_state *crtc_state) case GAMMA_MODE_MODE_10BIT: crtc_state->post_csc_lut = bdw_read_lut_10(crtc, PAL_PREC_INDEX_VALUE(0)); break; - case GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED: + case GAMMA_MODE_MODE_12BIT_MULTI_SEG: crtc_state->post_csc_lut = icl_read_lut_multi_segment(crtc); break; default: @@ -2268,6 +3045,7 @@ static const struct intel_color_funcs chv_color_funcs = { .color_commit_arm = i9xx_color_commit_arm, .load_luts = chv_load_luts, .read_luts = chv_read_luts, + .lut_equal = chv_lut_equal, }; static const struct intel_color_funcs i965_color_funcs = { @@ -2275,6 +3053,7 @@ static const struct intel_color_funcs i965_color_funcs = { .color_commit_arm = i9xx_color_commit_arm, .load_luts = i965_load_luts, .read_luts = i965_read_luts, + .lut_equal = i965_lut_equal, }; static const struct intel_color_funcs i9xx_color_funcs = { @@ -2282,6 +3061,7 @@ static const struct intel_color_funcs i9xx_color_funcs = { .color_commit_arm = i9xx_color_commit_arm, .load_luts = i9xx_load_luts, .read_luts = i9xx_read_luts, + .lut_equal = i9xx_lut_equal, }; static const struct intel_color_funcs icl_color_funcs = { @@ -2290,6 +3070,7 @@ static const struct intel_color_funcs icl_color_funcs = { .color_commit_arm = skl_color_commit_arm, .load_luts = icl_load_luts, .read_luts = icl_read_luts, + .lut_equal = icl_lut_equal, }; static const struct intel_color_funcs glk_color_funcs = { @@ -2298,6 +3079,7 @@ static const struct intel_color_funcs glk_color_funcs = { .color_commit_arm = skl_color_commit_arm, .load_luts = glk_load_luts, .read_luts = glk_read_luts, + .lut_equal = glk_lut_equal, }; static const struct intel_color_funcs skl_color_funcs = { @@ -2305,7 +3087,8 @@ static const struct intel_color_funcs skl_color_funcs = { .color_commit_noarm = ilk_color_commit_noarm, .color_commit_arm = skl_color_commit_arm, .load_luts = bdw_load_luts, - .read_luts = NULL, + .read_luts = bdw_read_luts, + .lut_equal = ivb_lut_equal, }; static const struct intel_color_funcs bdw_color_funcs = { @@ -2313,7 +3096,8 @@ static const struct intel_color_funcs bdw_color_funcs = { .color_commit_noarm = ilk_color_commit_noarm, .color_commit_arm = hsw_color_commit_arm, .load_luts = bdw_load_luts, - .read_luts = NULL, + .read_luts = bdw_read_luts, + .lut_equal = ivb_lut_equal, }; static const struct intel_color_funcs hsw_color_funcs = { @@ -2321,7 +3105,8 @@ static const struct intel_color_funcs hsw_color_funcs = { .color_commit_noarm = ilk_color_commit_noarm, .color_commit_arm = hsw_color_commit_arm, .load_luts = ivb_load_luts, - .read_luts = NULL, + .read_luts = ivb_read_luts, + .lut_equal = ivb_lut_equal, }; static const struct intel_color_funcs ivb_color_funcs = { @@ -2329,7 +3114,8 @@ static const struct intel_color_funcs ivb_color_funcs = { .color_commit_noarm = ilk_color_commit_noarm, .color_commit_arm = ilk_color_commit_arm, .load_luts = ivb_load_luts, - .read_luts = NULL, + .read_luts = ivb_read_luts, + .lut_equal = ivb_lut_equal, }; static const struct intel_color_funcs ilk_color_funcs = { @@ -2338,19 +3124,34 @@ static const struct intel_color_funcs ilk_color_funcs = { .color_commit_arm = ilk_color_commit_arm, .load_luts = ilk_load_luts, .read_luts = ilk_read_luts, + .lut_equal = ilk_lut_equal, }; void intel_color_crtc_init(struct intel_crtc *crtc) { struct drm_i915_private *i915 = to_i915(crtc->base.dev); - bool has_ctm = INTEL_INFO(i915)->display.color.degamma_lut_size != 0; + int degamma_lut_size, gamma_lut_size; + bool has_ctm; drm_mode_crtc_set_gamma_size(&crtc->base, 256); - drm_crtc_enable_color_mgmt(&crtc->base, - INTEL_INFO(i915)->display.color.degamma_lut_size, - has_ctm, - INTEL_INFO(i915)->display.color.gamma_lut_size); + gamma_lut_size = INTEL_INFO(i915)->display.color.gamma_lut_size; + degamma_lut_size = INTEL_INFO(i915)->display.color.degamma_lut_size; + has_ctm = degamma_lut_size != 0; + + /* + * "DPALETTE_A: NOTE: The 8-bit (non-10-bit) mode is the + * only mode supported by Alviso and Grantsdale." + * + * Actually looks like this affects all of gen3. + * Confirmed on alv,cst,pnv. Mobile gen2 parts (alm,mgm) + * are confirmed not to suffer from this restriction. + */ + if (DISPLAY_VER(i915) == 3 && crtc->pipe == PIPE_A) + gamma_lut_size = 256; + + drm_crtc_enable_color_mgmt(&crtc->base, degamma_lut_size, + has_ctm, gamma_lut_size); } int intel_color_init(struct drm_i915_private *i915) |