diff options
Diffstat (limited to 'drivers/gpu/drm/msm/disp')
43 files changed, 3678 insertions, 3264 deletions
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h new file mode 100644 index 000000000000..bdcd554fc8a8 --- /dev/null +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h @@ -0,0 +1,210 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved. + */ + +#ifndef _DPU_3_0_MSM8998_H +#define _DPU_3_0_MSM8998_H + +static const struct dpu_caps msm8998_dpu_caps = { + .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, + .max_mixer_blendstages = 0x7, + .qseed_type = DPU_SSPP_SCALER_QSEED3, + .has_src_split = true, + .has_dim_layer = true, + .has_idle_pc = true, + .has_3d_merge = true, + .max_linewidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH, + .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, + .max_hdeci_exp = MAX_HORZ_DECIMATION, + .max_vdeci_exp = MAX_VERT_DECIMATION, +}; + +static const struct dpu_ubwc_cfg msm8998_ubwc_cfg = { + .ubwc_version = DPU_HW_UBWC_VER_10, + .highest_bank_bit = 0x2, +}; + +static const struct dpu_mdp_cfg msm8998_mdp[] = { + { + .name = "top_0", .id = MDP_TOP, + .base = 0x0, .len = 0x458, + .features = 0, + .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, + .clk_ctrls[DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 }, + .clk_ctrls[DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 }, + .clk_ctrls[DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 }, + .clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 }, + .clk_ctrls[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 }, + .clk_ctrls[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2c4, .bit_off = 8 }, + .clk_ctrls[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 12 }, + .clk_ctrls[DPU_CLK_CTRL_CURSOR0] = { .reg_off = 0x3a8, .bit_off = 15 }, + .clk_ctrls[DPU_CLK_CTRL_CURSOR1] = { .reg_off = 0x3b0, .bit_off = 15 }, + }, +}; + +static const struct dpu_ctl_cfg msm8998_ctl[] = { + { + .name = "ctl_0", .id = CTL_0, + .base = 0x1000, .len = 0x94, + .features = BIT(DPU_CTL_SPLIT_DISPLAY), + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), + }, + { + .name = "ctl_1", .id = CTL_1, + .base = 0x1200, .len = 0x94, + .features = 0, + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), + }, + { + .name = "ctl_2", .id = CTL_2, + .base = 0x1400, .len = 0x94, + .features = BIT(DPU_CTL_SPLIT_DISPLAY), + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), + }, + { + .name = "ctl_3", .id = CTL_3, + .base = 0x1600, .len = 0x94, + .features = 0, + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), + }, + { + .name = "ctl_4", .id = CTL_4, + .base = 0x1800, .len = 0x94, + .features = 0, + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), + }, +}; + +static const struct dpu_sspp_cfg msm8998_sspp[] = { + SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1ac, VIG_MSM8998_MASK, + msm8998_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0), + SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, 0x1ac, VIG_MSM8998_MASK, + msm8998_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1), + SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, 0x1ac, VIG_MSM8998_MASK, + msm8998_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2), + SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, 0x1ac, VIG_MSM8998_MASK, + msm8998_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3), + SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1ac, DMA_MSM8998_MASK, + sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0), + SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1ac, DMA_MSM8998_MASK, + sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1), + SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1ac, DMA_CURSOR_MSM8998_MASK, + sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2), + SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, 0x1ac, DMA_CURSOR_MSM8998_MASK, + sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA3), +}; + +static const struct dpu_lm_cfg msm8998_lm[] = { + LM_BLK("lm_0", LM_0, 0x44000, MIXER_MSM8998_MASK, + &msm8998_lm_sblk, PINGPONG_0, LM_1, DSPP_0), + LM_BLK("lm_1", LM_1, 0x45000, MIXER_MSM8998_MASK, + &msm8998_lm_sblk, PINGPONG_1, LM_0, DSPP_1), + LM_BLK("lm_2", LM_2, 0x46000, MIXER_MSM8998_MASK, + &msm8998_lm_sblk, PINGPONG_2, LM_5, 0), + LM_BLK("lm_3", LM_3, 0x47000, MIXER_MSM8998_MASK, + &msm8998_lm_sblk, PINGPONG_MAX, 0, 0), + LM_BLK("lm_4", LM_4, 0x48000, MIXER_MSM8998_MASK, + &msm8998_lm_sblk, PINGPONG_MAX, 0, 0), + LM_BLK("lm_5", LM_5, 0x49000, MIXER_MSM8998_MASK, + &msm8998_lm_sblk, PINGPONG_3, LM_2, 0), +}; + +static const struct dpu_pingpong_cfg msm8998_pp[] = { + PP_BLK_TE("pingpong_0", PINGPONG_0, 0x70000, 0, sdm845_pp_sblk_te, + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12)), + PP_BLK_TE("pingpong_1", PINGPONG_1, 0x70800, 0, sdm845_pp_sblk_te, + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13)), + PP_BLK("pingpong_2", PINGPONG_2, 0x71000, 0, sdm845_pp_sblk, + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14)), + PP_BLK("pingpong_3", PINGPONG_3, 0x71800, 0, sdm845_pp_sblk, + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15)), +}; + +static const struct dpu_dspp_cfg msm8998_dspp[] = { + DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_MSM8998_MASK, + &msm8998_dspp_sblk), + DSPP_BLK("dspp_1", DSPP_1, 0x56000, DSPP_MSM8998_MASK, + &msm8998_dspp_sblk), +}; + +static const struct dpu_intf_cfg msm8998_intf[] = { + INTF_BLK("intf_0", INTF_0, 0x6a000, 0x280, INTF_DP, 0, 21, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 24, 25), + INTF_BLK("intf_1", INTF_1, 0x6a800, 0x280, INTF_DSI, 0, 21, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 26, 27), + INTF_BLK("intf_2", INTF_2, 0x6b000, 0x280, INTF_DSI, 1, 21, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 28, 29), + INTF_BLK("intf_3", INTF_3, 0x6b800, 0x280, INTF_HDMI, 0, 21, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 30, 31), +}; + +static const struct dpu_perf_cfg msm8998_perf_data = { + .max_bw_low = 6700000, + .max_bw_high = 6700000, + .min_core_ib = 2400000, + .min_llcc_ib = 800000, + .min_dram_ib = 800000, + .undersized_prefill_lines = 2, + .xtra_prefill_lines = 2, + .dest_scale_prefill_lines = 3, + .macrotile_prefill_lines = 4, + .yuv_nv12_prefill_lines = 8, + .linear_prefill_lines = 1, + .downscaling_prefill_lines = 1, + .amortizable_threshold = 25, + .min_prefill_lines = 25, + .danger_lut_tbl = {0xf, 0xffff, 0x0}, + .safe_lut_tbl = {0xfffc, 0xff00, 0xffff}, + .qos_lut_tbl = { + {.nentry = ARRAY_SIZE(msm8998_qos_linear), + .entries = msm8998_qos_linear + }, + {.nentry = ARRAY_SIZE(msm8998_qos_macrotile), + .entries = msm8998_qos_macrotile + }, + {.nentry = ARRAY_SIZE(msm8998_qos_nrt), + .entries = msm8998_qos_nrt + }, + }, + .cdp_cfg = { + {.rd_enable = 1, .wr_enable = 1}, + {.rd_enable = 1, .wr_enable = 0} + }, + .clk_inefficiency_factor = 200, + .bw_inefficiency_factor = 120, +}; + +const struct dpu_mdss_cfg dpu_msm8998_cfg = { + .caps = &msm8998_dpu_caps, + .ubwc = &msm8998_ubwc_cfg, + .mdp_count = ARRAY_SIZE(msm8998_mdp), + .mdp = msm8998_mdp, + .ctl_count = ARRAY_SIZE(msm8998_ctl), + .ctl = msm8998_ctl, + .sspp_count = ARRAY_SIZE(msm8998_sspp), + .sspp = msm8998_sspp, + .mixer_count = ARRAY_SIZE(msm8998_lm), + .mixer = msm8998_lm, + .dspp_count = ARRAY_SIZE(msm8998_dspp), + .dspp = msm8998_dspp, + .pingpong_count = ARRAY_SIZE(msm8998_pp), + .pingpong = msm8998_pp, + .intf_count = ARRAY_SIZE(msm8998_intf), + .intf = msm8998_intf, + .vbif_count = ARRAY_SIZE(msm8998_vbif), + .vbif = msm8998_vbif, + .reg_dma_count = 0, + .perf = &msm8998_perf_data, + .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \ + BIT(MDP_SSPP_TOP0_INTR2) | \ + BIT(MDP_SSPP_TOP0_HIST_INTR) | \ + BIT(MDP_INTF0_INTR) | \ + BIT(MDP_INTF1_INTR) | \ + BIT(MDP_INTF2_INTR) | \ + BIT(MDP_INTF3_INTR) | \ + BIT(MDP_INTF4_INTR), +}; + +#endif diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h new file mode 100644 index 000000000000..ceca741e93c9 --- /dev/null +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h @@ -0,0 +1,210 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved. + */ + +#ifndef _DPU_4_0_SDM845_H +#define _DPU_4_0_SDM845_H + +static const struct dpu_caps sdm845_dpu_caps = { + .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, + .max_mixer_blendstages = 0xb, + .qseed_type = DPU_SSPP_SCALER_QSEED3, + .has_src_split = true, + .has_dim_layer = true, + .has_idle_pc = true, + .has_3d_merge = true, + .max_linewidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH, + .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, + .max_hdeci_exp = MAX_HORZ_DECIMATION, + .max_vdeci_exp = MAX_VERT_DECIMATION, +}; + +static const struct dpu_ubwc_cfg sdm845_ubwc_cfg = { + .ubwc_version = DPU_HW_UBWC_VER_20, + .highest_bank_bit = 0x2, +}; + +static const struct dpu_mdp_cfg sdm845_mdp[] = { + { + .name = "top_0", .id = MDP_TOP, + .base = 0x0, .len = 0x45c, + .features = BIT(DPU_MDP_AUDIO_SELECT), + .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, + .clk_ctrls[DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 }, + .clk_ctrls[DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 }, + .clk_ctrls[DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 }, + .clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 }, + .clk_ctrls[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 }, + .clk_ctrls[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 }, + .clk_ctrls[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 }, + }, +}; + +static const struct dpu_ctl_cfg sdm845_ctl[] = { + { + .name = "ctl_0", .id = CTL_0, + .base = 0x1000, .len = 0xe4, + .features = BIT(DPU_CTL_SPLIT_DISPLAY), + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), + }, + { + .name = "ctl_1", .id = CTL_1, + .base = 0x1200, .len = 0xe4, + .features = BIT(DPU_CTL_SPLIT_DISPLAY), + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), + }, + { + .name = "ctl_2", .id = CTL_2, + .base = 0x1400, .len = 0xe4, + .features = 0, + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), + }, + { + .name = "ctl_3", .id = CTL_3, + .base = 0x1600, .len = 0xe4, + .features = 0, + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), + }, + { + .name = "ctl_4", .id = CTL_4, + .base = 0x1800, .len = 0xe4, + .features = 0, + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), + }, +}; + +static const struct dpu_sspp_cfg sdm845_sspp[] = { + SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1c8, VIG_SDM845_MASK_SDMA, + sdm845_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0), + SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, 0x1c8, VIG_SDM845_MASK_SDMA, + sdm845_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1), + SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, 0x1c8, VIG_SDM845_MASK_SDMA, + sdm845_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2), + SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, 0x1c8, VIG_SDM845_MASK_SDMA, + sdm845_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3), + SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1c8, DMA_SDM845_MASK_SDMA, + sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0), + SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1c8, DMA_SDM845_MASK_SDMA, + sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1), + SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1c8, DMA_CURSOR_SDM845_MASK_SDMA, + sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2), + SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, 0x1c8, DMA_CURSOR_SDM845_MASK_SDMA, + sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA3), +}; + +static const struct dpu_lm_cfg sdm845_lm[] = { + LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK, + &sdm845_lm_sblk, PINGPONG_0, LM_1, 0), + LM_BLK("lm_1", LM_1, 0x45000, MIXER_SDM845_MASK, + &sdm845_lm_sblk, PINGPONG_1, LM_0, 0), + LM_BLK("lm_2", LM_2, 0x46000, MIXER_SDM845_MASK, + &sdm845_lm_sblk, PINGPONG_2, LM_5, 0), + LM_BLK("lm_3", LM_3, 0x0, MIXER_SDM845_MASK, + &sdm845_lm_sblk, PINGPONG_MAX, 0, 0), + LM_BLK("lm_4", LM_4, 0x0, MIXER_SDM845_MASK, + &sdm845_lm_sblk, PINGPONG_MAX, 0, 0), + LM_BLK("lm_5", LM_5, 0x49000, MIXER_SDM845_MASK, + &sdm845_lm_sblk, PINGPONG_3, LM_2, 0), +}; + +static const struct dpu_pingpong_cfg sdm845_pp[] = { + PP_BLK_TE("pingpong_0", PINGPONG_0, 0x70000, 0, sdm845_pp_sblk_te, + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12)), + PP_BLK_TE("pingpong_1", PINGPONG_1, 0x70800, 0, sdm845_pp_sblk_te, + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13)), + PP_BLK("pingpong_2", PINGPONG_2, 0x71000, 0, sdm845_pp_sblk, + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14)), + PP_BLK("pingpong_3", PINGPONG_3, 0x71800, 0, sdm845_pp_sblk, + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15)), +}; + +static const struct dpu_dsc_cfg sdm845_dsc[] = { + DSC_BLK("dsc_0", DSC_0, 0x80000, 0), + DSC_BLK("dsc_1", DSC_1, 0x80400, 0), + DSC_BLK("dsc_2", DSC_2, 0x80800, 0), + DSC_BLK("dsc_3", DSC_3, 0x80c00, 0), +}; + +static const struct dpu_intf_cfg sdm845_intf[] = { + INTF_BLK("intf_0", INTF_0, 0x6a000, 0x280, INTF_DP, 0, 24, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 24, 25), + INTF_BLK("intf_1", INTF_1, 0x6a800, 0x280, INTF_DSI, 0, 24, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 26, 27), + INTF_BLK("intf_2", INTF_2, 0x6b000, 0x280, INTF_DSI, 1, 24, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 28, 29), + INTF_BLK("intf_3", INTF_3, 0x6b800, 0x280, INTF_DP, 1, 24, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 30, 31), +}; + +static const struct dpu_perf_cfg sdm845_perf_data = { + .max_bw_low = 6800000, + .max_bw_high = 6800000, + .min_core_ib = 2400000, + .min_llcc_ib = 800000, + .min_dram_ib = 800000, + .undersized_prefill_lines = 2, + .xtra_prefill_lines = 2, + .dest_scale_prefill_lines = 3, + .macrotile_prefill_lines = 4, + .yuv_nv12_prefill_lines = 8, + .linear_prefill_lines = 1, + .downscaling_prefill_lines = 1, + .amortizable_threshold = 25, + .min_prefill_lines = 24, + .danger_lut_tbl = {0xf, 0xffff, 0x0}, + .safe_lut_tbl = {0xfff0, 0xf000, 0xffff}, + .qos_lut_tbl = { + {.nentry = ARRAY_SIZE(sdm845_qos_linear), + .entries = sdm845_qos_linear + }, + {.nentry = ARRAY_SIZE(sdm845_qos_macrotile), + .entries = sdm845_qos_macrotile + }, + {.nentry = ARRAY_SIZE(sdm845_qos_nrt), + .entries = sdm845_qos_nrt + }, + }, + .cdp_cfg = { + {.rd_enable = 1, .wr_enable = 1}, + {.rd_enable = 1, .wr_enable = 0} + }, + .clk_inefficiency_factor = 105, + .bw_inefficiency_factor = 120, +}; + +const struct dpu_mdss_cfg dpu_sdm845_cfg = { + .caps = &sdm845_dpu_caps, + .ubwc = &sdm845_ubwc_cfg, + .mdp_count = ARRAY_SIZE(sdm845_mdp), + .mdp = sdm845_mdp, + .ctl_count = ARRAY_SIZE(sdm845_ctl), + .ctl = sdm845_ctl, + .sspp_count = ARRAY_SIZE(sdm845_sspp), + .sspp = sdm845_sspp, + .mixer_count = ARRAY_SIZE(sdm845_lm), + .mixer = sdm845_lm, + .pingpong_count = ARRAY_SIZE(sdm845_pp), + .pingpong = sdm845_pp, + .dsc_count = ARRAY_SIZE(sdm845_dsc), + .dsc = sdm845_dsc, + .intf_count = ARRAY_SIZE(sdm845_intf), + .intf = sdm845_intf, + .vbif_count = ARRAY_SIZE(sdm845_vbif), + .vbif = sdm845_vbif, + .reg_dma_count = 1, + .dma_cfg = &sdm845_regdma, + .perf = &sdm845_perf_data, + .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \ + BIT(MDP_SSPP_TOP0_INTR2) | \ + BIT(MDP_SSPP_TOP0_HIST_INTR) | \ + BIT(MDP_INTF0_INTR) | \ + BIT(MDP_INTF1_INTR) | \ + BIT(MDP_INTF2_INTR) | \ + BIT(MDP_INTF3_INTR) | \ + BIT(MDP_AD4_0_INTR) | \ + BIT(MDP_AD4_1_INTR), +}; + +#endif diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h new file mode 100644 index 000000000000..42b0e58624d0 --- /dev/null +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h @@ -0,0 +1,237 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved. + */ + +#ifndef _DPU_5_0_SM8150_H +#define _DPU_5_0_SM8150_H + +static const struct dpu_caps sm8150_dpu_caps = { + .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, + .max_mixer_blendstages = 0xb, + .qseed_type = DPU_SSPP_SCALER_QSEED3, + .has_src_split = true, + .has_dim_layer = true, + .has_idle_pc = true, + .has_3d_merge = true, + .max_linewidth = 4096, + .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, + .max_hdeci_exp = MAX_HORZ_DECIMATION, + .max_vdeci_exp = MAX_VERT_DECIMATION, +}; + +static const struct dpu_ubwc_cfg sm8150_ubwc_cfg = { + .ubwc_version = DPU_HW_UBWC_VER_30, + .highest_bank_bit = 0x2, +}; + +static const struct dpu_mdp_cfg sm8150_mdp[] = { + { + .name = "top_0", .id = MDP_TOP, + .base = 0x0, .len = 0x45c, + .features = BIT(DPU_MDP_AUDIO_SELECT), + .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, + .clk_ctrls[DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 }, + .clk_ctrls[DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 }, + .clk_ctrls[DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 }, + .clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 }, + .clk_ctrls[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 }, + .clk_ctrls[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 }, + .clk_ctrls[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 }, + }, +}; + +/* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper ACTIVE_CTL support */ +static const struct dpu_ctl_cfg sm8150_ctl[] = { + { + .name = "ctl_0", .id = CTL_0, + .base = 0x1000, .len = 0x1e0, + .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY), + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), + }, + { + .name = "ctl_1", .id = CTL_1, + .base = 0x1200, .len = 0x1e0, + .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY), + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), + }, + { + .name = "ctl_2", .id = CTL_2, + .base = 0x1400, .len = 0x1e0, + .features = BIT(DPU_CTL_ACTIVE_CFG), + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), + }, + { + .name = "ctl_3", .id = CTL_3, + .base = 0x1600, .len = 0x1e0, + .features = BIT(DPU_CTL_ACTIVE_CFG), + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), + }, + { + .name = "ctl_4", .id = CTL_4, + .base = 0x1800, .len = 0x1e0, + .features = BIT(DPU_CTL_ACTIVE_CFG), + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), + }, + { + .name = "ctl_5", .id = CTL_5, + .base = 0x1a00, .len = 0x1e0, + .features = BIT(DPU_CTL_ACTIVE_CFG), + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23), + }, +}; + +static const struct dpu_sspp_cfg sm8150_sspp[] = { + SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f0, VIG_SDM845_MASK, + sdm845_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0), + SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, 0x1f0, VIG_SDM845_MASK, + sdm845_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1), + SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, 0x1f0, VIG_SDM845_MASK, + sdm845_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2), + SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, 0x1f0, VIG_SDM845_MASK, + sdm845_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3), + SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f0, DMA_SDM845_MASK, + sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0), + SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1f0, DMA_SDM845_MASK, + sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1), + SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1f0, DMA_CURSOR_SDM845_MASK, + sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2), + SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, 0x1f0, DMA_CURSOR_SDM845_MASK, + sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA3), +}; + +static const struct dpu_lm_cfg sm8150_lm[] = { + LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK, + &sdm845_lm_sblk, PINGPONG_0, LM_1, DSPP_0), + LM_BLK("lm_1", LM_1, 0x45000, MIXER_SDM845_MASK, + &sdm845_lm_sblk, PINGPONG_1, LM_0, DSPP_1), + LM_BLK("lm_2", LM_2, 0x46000, MIXER_SDM845_MASK, + &sdm845_lm_sblk, PINGPONG_2, LM_3, 0), + LM_BLK("lm_3", LM_3, 0x47000, MIXER_SDM845_MASK, + &sdm845_lm_sblk, PINGPONG_3, LM_2, 0), + LM_BLK("lm_4", LM_4, 0x48000, MIXER_SDM845_MASK, + &sdm845_lm_sblk, PINGPONG_4, LM_5, 0), + LM_BLK("lm_5", LM_5, 0x49000, MIXER_SDM845_MASK, + &sdm845_lm_sblk, PINGPONG_5, LM_4, 0), +}; + +static const struct dpu_dspp_cfg sm8150_dspp[] = { + DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK, + &sm8150_dspp_sblk), + DSPP_BLK("dspp_1", DSPP_1, 0x56000, DSPP_SC7180_MASK, + &sm8150_dspp_sblk), + DSPP_BLK("dspp_2", DSPP_2, 0x58000, DSPP_SC7180_MASK, + &sm8150_dspp_sblk), + DSPP_BLK("dspp_3", DSPP_3, 0x5a000, DSPP_SC7180_MASK, + &sm8150_dspp_sblk), +}; + +static const struct dpu_pingpong_cfg sm8150_pp[] = { + PP_BLK("pingpong_0", PINGPONG_0, 0x70000, MERGE_3D_0, sdm845_pp_sblk, + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12)), + PP_BLK("pingpong_1", PINGPONG_1, 0x70800, MERGE_3D_0, sdm845_pp_sblk, + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13)), + PP_BLK("pingpong_2", PINGPONG_2, 0x71000, MERGE_3D_1, sdm845_pp_sblk, + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14)), + PP_BLK("pingpong_3", PINGPONG_3, 0x71800, MERGE_3D_1, sdm845_pp_sblk, + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15)), + PP_BLK("pingpong_4", PINGPONG_4, 0x72000, MERGE_3D_2, sdm845_pp_sblk, + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30), + -1), + PP_BLK("pingpong_5", PINGPONG_5, 0x72800, MERGE_3D_2, sdm845_pp_sblk, + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31), + -1), +}; + +static const struct dpu_merge_3d_cfg sm8150_merge_3d[] = { + MERGE_3D_BLK("merge_3d_0", MERGE_3D_0, 0x83000), + MERGE_3D_BLK("merge_3d_1", MERGE_3D_1, 0x83100), + MERGE_3D_BLK("merge_3d_2", MERGE_3D_2, 0x83200), +}; + +static const struct dpu_dsc_cfg sm8150_dsc[] = { + DSC_BLK("dsc_0", DSC_0, 0x80000, BIT(DPU_DSC_OUTPUT_CTRL)), + DSC_BLK("dsc_1", DSC_1, 0x80400, BIT(DPU_DSC_OUTPUT_CTRL)), + DSC_BLK("dsc_2", DSC_2, 0x80800, BIT(DPU_DSC_OUTPUT_CTRL)), + DSC_BLK("dsc_3", DSC_3, 0x80c00, BIT(DPU_DSC_OUTPUT_CTRL)), +}; + +static const struct dpu_intf_cfg sm8150_intf[] = { + INTF_BLK("intf_0", INTF_0, 0x6a000, 0x280, INTF_DP, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 24, 25), + INTF_BLK("intf_1", INTF_1, 0x6a800, 0x2bc, INTF_DSI, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 26, 27), + INTF_BLK("intf_2", INTF_2, 0x6b000, 0x2bc, INTF_DSI, 1, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 28, 29), + INTF_BLK("intf_3", INTF_3, 0x6b800, 0x280, INTF_DP, 1, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 30, 31), +}; + +static const struct dpu_perf_cfg sm8150_perf_data = { + .max_bw_low = 12800000, + .max_bw_high = 12800000, + .min_core_ib = 2400000, + .min_llcc_ib = 800000, + .min_dram_ib = 800000, + .min_prefill_lines = 24, + .danger_lut_tbl = {0xf, 0xffff, 0x0}, + .safe_lut_tbl = {0xfff8, 0xf000, 0xffff}, + .qos_lut_tbl = { + {.nentry = ARRAY_SIZE(sm8150_qos_linear), + .entries = sm8150_qos_linear + }, + {.nentry = ARRAY_SIZE(sc7180_qos_macrotile), + .entries = sc7180_qos_macrotile + }, + {.nentry = ARRAY_SIZE(sc7180_qos_nrt), + .entries = sc7180_qos_nrt + }, + /* TODO: macrotile-qseed is different from macrotile */ + }, + .cdp_cfg = { + {.rd_enable = 1, .wr_enable = 1}, + {.rd_enable = 1, .wr_enable = 0} + }, + .clk_inefficiency_factor = 105, + .bw_inefficiency_factor = 120, +}; + +const struct dpu_mdss_cfg dpu_sm8150_cfg = { + .caps = &sm8150_dpu_caps, + .ubwc = &sm8150_ubwc_cfg, + .mdp_count = ARRAY_SIZE(sm8150_mdp), + .mdp = sm8150_mdp, + .ctl_count = ARRAY_SIZE(sm8150_ctl), + .ctl = sm8150_ctl, + .sspp_count = ARRAY_SIZE(sm8150_sspp), + .sspp = sm8150_sspp, + .mixer_count = ARRAY_SIZE(sm8150_lm), + .mixer = sm8150_lm, + .dspp_count = ARRAY_SIZE(sm8150_dspp), + .dspp = sm8150_dspp, + .dsc_count = ARRAY_SIZE(sm8150_dsc), + .dsc = sm8150_dsc, + .pingpong_count = ARRAY_SIZE(sm8150_pp), + .pingpong = sm8150_pp, + .merge_3d_count = ARRAY_SIZE(sm8150_merge_3d), + .merge_3d = sm8150_merge_3d, + .intf_count = ARRAY_SIZE(sm8150_intf), + .intf = sm8150_intf, + .vbif_count = ARRAY_SIZE(sdm845_vbif), + .vbif = sdm845_vbif, + .reg_dma_count = 1, + .dma_cfg = &sm8150_regdma, + .perf = &sm8150_perf_data, + .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \ + BIT(MDP_SSPP_TOP0_INTR2) | \ + BIT(MDP_SSPP_TOP0_HIST_INTR) | \ + BIT(MDP_INTF0_INTR) | \ + BIT(MDP_INTF1_INTR) | \ + BIT(MDP_INTF2_INTR) | \ + BIT(MDP_INTF3_INTR) | \ + BIT(MDP_AD4_0_INTR) | \ + BIT(MDP_AD4_1_INTR), +}; + +#endif diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h new file mode 100644 index 000000000000..e3bdfe7b30f1 --- /dev/null +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h @@ -0,0 +1,217 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved. + */ + +#ifndef _DPU_5_1_SC8180X_H +#define _DPU_5_1_SC8180X_H + +static const struct dpu_caps sc8180x_dpu_caps = { + .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, + .max_mixer_blendstages = 0xb, + .qseed_type = DPU_SSPP_SCALER_QSEED3, + .has_src_split = true, + .has_dim_layer = true, + .has_idle_pc = true, + .has_3d_merge = true, + .max_linewidth = 4096, + .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, + .max_hdeci_exp = MAX_HORZ_DECIMATION, + .max_vdeci_exp = MAX_VERT_DECIMATION, +}; + +static const struct dpu_ubwc_cfg sc8180x_ubwc_cfg = { + .ubwc_version = DPU_HW_UBWC_VER_30, + .highest_bank_bit = 0x3, +}; + +static const struct dpu_mdp_cfg sc8180x_mdp[] = { + { + .name = "top_0", .id = MDP_TOP, + .base = 0x0, .len = 0x45c, + .features = BIT(DPU_MDP_AUDIO_SELECT), + .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, + .clk_ctrls[DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 }, + .clk_ctrls[DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 }, + .clk_ctrls[DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 }, + .clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 }, + .clk_ctrls[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 }, + .clk_ctrls[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 }, + .clk_ctrls[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 }, + }, +}; + +static const struct dpu_ctl_cfg sc8180x_ctl[] = { + { + .name = "ctl_0", .id = CTL_0, + .base = 0x1000, .len = 0x1e0, + .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY), + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), + }, + { + .name = "ctl_1", .id = CTL_1, + .base = 0x1200, .len = 0x1e0, + .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY), + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), + }, + { + .name = "ctl_2", .id = CTL_2, + .base = 0x1400, .len = 0x1e0, + .features = BIT(DPU_CTL_ACTIVE_CFG), + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), + }, + { + .name = "ctl_3", .id = CTL_3, + .base = 0x1600, .len = 0x1e0, + .features = BIT(DPU_CTL_ACTIVE_CFG), + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), + }, + { + .name = "ctl_4", .id = CTL_4, + .base = 0x1800, .len = 0x1e0, + .features = BIT(DPU_CTL_ACTIVE_CFG), + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), + }, + { + .name = "ctl_5", .id = CTL_5, + .base = 0x1a00, .len = 0x1e0, + .features = BIT(DPU_CTL_ACTIVE_CFG), + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23), + }, +}; + +static const struct dpu_sspp_cfg sc8180x_sspp[] = { + SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f0, VIG_SDM845_MASK, + sdm845_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0), + SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, 0x1f0, VIG_SDM845_MASK, + sdm845_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1), + SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, 0x1f0, VIG_SDM845_MASK, + sdm845_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2), + SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, 0x1f0, VIG_SDM845_MASK, + sdm845_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3), + SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f0, DMA_SDM845_MASK, + sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0), + SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1f0, DMA_SDM845_MASK, + sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1), + SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1f0, DMA_CURSOR_SDM845_MASK, + sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2), + SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, 0x1f0, DMA_CURSOR_SDM845_MASK, + sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA3), +}; + +static const struct dpu_lm_cfg sc8180x_lm[] = { + LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK, + &sdm845_lm_sblk, PINGPONG_0, LM_1, 0), + LM_BLK("lm_1", LM_1, 0x45000, MIXER_SDM845_MASK, + &sdm845_lm_sblk, PINGPONG_1, LM_0, 0), + LM_BLK("lm_2", LM_2, 0x46000, MIXER_SDM845_MASK, + &sdm845_lm_sblk, PINGPONG_2, LM_3, 0), + LM_BLK("lm_3", LM_3, 0x47000, MIXER_SDM845_MASK, + &sdm845_lm_sblk, PINGPONG_3, LM_2, 0), + LM_BLK("lm_4", LM_4, 0x48000, MIXER_SDM845_MASK, + &sdm845_lm_sblk, PINGPONG_4, LM_5, 0), + LM_BLK("lm_5", LM_5, 0x49000, MIXER_SDM845_MASK, + &sdm845_lm_sblk, PINGPONG_5, LM_4, 0), +}; + +static const struct dpu_pingpong_cfg sc8180x_pp[] = { + PP_BLK("pingpong_0", PINGPONG_0, 0x70000, MERGE_3D_0, sdm845_pp_sblk, + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12)), + PP_BLK("pingpong_1", PINGPONG_1, 0x70800, MERGE_3D_0, sdm845_pp_sblk, + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13)), + PP_BLK("pingpong_2", PINGPONG_2, 0x71000, MERGE_3D_1, sdm845_pp_sblk, + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14)), + PP_BLK("pingpong_3", PINGPONG_3, 0x71800, MERGE_3D_1, sdm845_pp_sblk, + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15)), + PP_BLK("pingpong_4", PINGPONG_4, 0x72000, MERGE_3D_2, sdm845_pp_sblk, + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30), + -1), + PP_BLK("pingpong_5", PINGPONG_5, 0x72800, MERGE_3D_2, sdm845_pp_sblk, + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31), + -1), +}; + +static const struct dpu_merge_3d_cfg sc8180x_merge_3d[] = { + MERGE_3D_BLK("merge_3d_0", MERGE_3D_0, 0x83000), + MERGE_3D_BLK("merge_3d_1", MERGE_3D_1, 0x83100), + MERGE_3D_BLK("merge_3d_2", MERGE_3D_2, 0x83200), +}; + +static const struct dpu_intf_cfg sc8180x_intf[] = { + INTF_BLK("intf_0", INTF_0, 0x6a000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 24, 25), + INTF_BLK("intf_1", INTF_1, 0x6a800, 0x2bc, INTF_DSI, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 26, 27), + INTF_BLK("intf_2", INTF_2, 0x6b000, 0x2bc, INTF_DSI, 1, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 28, 29), + /* INTF_3 is for MST, wired to INTF_DP 0 and 1, use dummy index until this is supported */ + INTF_BLK("intf_3", INTF_3, 0x6b800, 0x280, INTF_DP, 999, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 30, 31), + INTF_BLK("intf_4", INTF_4, 0x6c000, 0x280, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 20, 21), + INTF_BLK("intf_5", INTF_5, 0x6c800, 0x280, INTF_DP, MSM_DP_CONTROLLER_2, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 22, 23), +}; + +static const struct dpu_perf_cfg sc8180x_perf_data = { + .max_bw_low = 9600000, + .max_bw_high = 9600000, + .min_core_ib = 2400000, + .min_llcc_ib = 800000, + .min_dram_ib = 800000, + .danger_lut_tbl = {0xf, 0xffff, 0x0}, + .qos_lut_tbl = { + {.nentry = ARRAY_SIZE(sc7180_qos_linear), + .entries = sc7180_qos_linear + }, + {.nentry = ARRAY_SIZE(sc7180_qos_macrotile), + .entries = sc7180_qos_macrotile + }, + {.nentry = ARRAY_SIZE(sc7180_qos_nrt), + .entries = sc7180_qos_nrt + }, + /* TODO: macrotile-qseed is different from macrotile */ + }, + .cdp_cfg = { + {.rd_enable = 1, .wr_enable = 1}, + {.rd_enable = 1, .wr_enable = 0} + }, + .clk_inefficiency_factor = 105, + .bw_inefficiency_factor = 120, +}; + +const struct dpu_mdss_cfg dpu_sc8180x_cfg = { + .caps = &sc8180x_dpu_caps, + .ubwc = &sc8180x_ubwc_cfg, + .mdp_count = ARRAY_SIZE(sc8180x_mdp), + .mdp = sc8180x_mdp, + .ctl_count = ARRAY_SIZE(sc8180x_ctl), + .ctl = sc8180x_ctl, + .sspp_count = ARRAY_SIZE(sc8180x_sspp), + .sspp = sc8180x_sspp, + .mixer_count = ARRAY_SIZE(sc8180x_lm), + .mixer = sc8180x_lm, + .pingpong_count = ARRAY_SIZE(sc8180x_pp), + .pingpong = sc8180x_pp, + .merge_3d_count = ARRAY_SIZE(sc8180x_merge_3d), + .merge_3d = sc8180x_merge_3d, + .intf_count = ARRAY_SIZE(sc8180x_intf), + .intf = sc8180x_intf, + .vbif_count = ARRAY_SIZE(sdm845_vbif), + .vbif = sdm845_vbif, + .reg_dma_count = 1, + .dma_cfg = &sm8150_regdma, + .perf = &sc8180x_perf_data, + .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \ + BIT(MDP_SSPP_TOP0_INTR2) | \ + BIT(MDP_SSPP_TOP0_HIST_INTR) | \ + BIT(MDP_INTF0_INTR) | \ + BIT(MDP_INTF1_INTR) | \ + BIT(MDP_INTF2_INTR) | \ + BIT(MDP_INTF3_INTR) | \ + BIT(MDP_INTF4_INTR) | \ + BIT(MDP_INTF5_INTR) | \ + BIT(MDP_AD4_0_INTR) | \ + BIT(MDP_AD4_1_INTR), +}; + +#endif diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h new file mode 100644 index 000000000000..ed130582873c --- /dev/null +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h @@ -0,0 +1,244 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved. + */ + +#ifndef _DPU_6_0_SM8250_H +#define _DPU_6_0_SM8250_H + +static const struct dpu_caps sm8250_dpu_caps = { + .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, + .max_mixer_blendstages = 0xb, + .qseed_type = DPU_SSPP_SCALER_QSEED4, + .has_src_split = true, + .has_dim_layer = true, + .has_idle_pc = true, + .has_3d_merge = true, + .max_linewidth = 4096, + .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, +}; + +static const struct dpu_ubwc_cfg sm8250_ubwc_cfg = { + .ubwc_version = DPU_HW_UBWC_VER_40, + .highest_bank_bit = 0x3, /* TODO: 2 for LP_DDR4 */ + .ubwc_swizzle = 0x6, +}; + +static const struct dpu_mdp_cfg sm8250_mdp[] = { + { + .name = "top_0", .id = MDP_TOP, + .base = 0x0, .len = 0x494, + .features = 0, + .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, + .clk_ctrls[DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 }, + .clk_ctrls[DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 }, + .clk_ctrls[DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 }, + .clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 }, + .clk_ctrls[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 }, + .clk_ctrls[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 }, + .clk_ctrls[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 }, + .clk_ctrls[DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 }, + .clk_ctrls[DPU_CLK_CTRL_WB2] = { .reg_off = 0x3b8, .bit_off = 24 }, + }, +}; + +/* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper ACTIVE_CTL support */ +static const struct dpu_ctl_cfg sm8250_ctl[] = { + { + .name = "ctl_0", .id = CTL_0, + .base = 0x1000, .len = 0x1e0, + .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY), + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), + }, + { + .name = "ctl_1", .id = CTL_1, + .base = 0x1200, .len = 0x1e0, + .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY), + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), + }, + { + .name = "ctl_2", .id = CTL_2, + .base = 0x1400, .len = 0x1e0, + .features = BIT(DPU_CTL_ACTIVE_CFG), + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), + }, + { + .name = "ctl_3", .id = CTL_3, + .base = 0x1600, .len = 0x1e0, + .features = BIT(DPU_CTL_ACTIVE_CFG), + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), + }, + { + .name = "ctl_4", .id = CTL_4, + .base = 0x1800, .len = 0x1e0, + .features = BIT(DPU_CTL_ACTIVE_CFG), + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), + }, + { + .name = "ctl_5", .id = CTL_5, + .base = 0x1a00, .len = 0x1e0, + .features = BIT(DPU_CTL_ACTIVE_CFG), + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23), + }, +}; + +static const struct dpu_sspp_cfg sm8250_sspp[] = { + SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_SC7180_MASK_SDMA, + sm8250_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0), + SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, 0x1f8, VIG_SC7180_MASK_SDMA, + sm8250_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1), + SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, 0x1f8, VIG_SC7180_MASK_SDMA, + sm8250_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2), + SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, 0x1f8, VIG_SC7180_MASK_SDMA, + sm8250_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3), + SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_SDM845_MASK_SDMA, + sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0), + SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1f8, DMA_SDM845_MASK_SDMA, + sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1), + SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1f8, DMA_CURSOR_SDM845_MASK_SDMA, + sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2), + SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, 0x1f8, DMA_CURSOR_SDM845_MASK_SDMA, + sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA3), +}; + +static const struct dpu_lm_cfg sm8250_lm[] = { + LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK, + &sdm845_lm_sblk, PINGPONG_0, LM_1, DSPP_0), + LM_BLK("lm_1", LM_1, 0x45000, MIXER_SDM845_MASK, + &sdm845_lm_sblk, PINGPONG_1, LM_0, DSPP_1), + LM_BLK("lm_2", LM_2, 0x46000, MIXER_SDM845_MASK, + &sdm845_lm_sblk, PINGPONG_2, LM_3, 0), + LM_BLK("lm_3", LM_3, 0x47000, MIXER_SDM845_MASK, + &sdm845_lm_sblk, PINGPONG_3, LM_2, 0), + LM_BLK("lm_4", LM_4, 0x48000, MIXER_SDM845_MASK, + &sdm845_lm_sblk, PINGPONG_4, LM_5, 0), + LM_BLK("lm_5", LM_5, 0x49000, MIXER_SDM845_MASK, + &sdm845_lm_sblk, PINGPONG_5, LM_4, 0), +}; + +static const struct dpu_dspp_cfg sm8250_dspp[] = { + DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK, + &sm8150_dspp_sblk), + DSPP_BLK("dspp_1", DSPP_1, 0x56000, DSPP_SC7180_MASK, + &sm8150_dspp_sblk), + DSPP_BLK("dspp_2", DSPP_2, 0x58000, DSPP_SC7180_MASK, + &sm8150_dspp_sblk), + DSPP_BLK("dspp_3", DSPP_3, 0x5a000, DSPP_SC7180_MASK, + &sm8150_dspp_sblk), +}; + +static const struct dpu_pingpong_cfg sm8250_pp[] = { + PP_BLK("pingpong_0", PINGPONG_0, 0x70000, MERGE_3D_0, sdm845_pp_sblk, + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12)), + PP_BLK("pingpong_1", PINGPONG_1, 0x70800, MERGE_3D_0, sdm845_pp_sblk, + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13)), + PP_BLK("pingpong_2", PINGPONG_2, 0x71000, MERGE_3D_1, sdm845_pp_sblk, + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14)), + PP_BLK("pingpong_3", PINGPONG_3, 0x71800, MERGE_3D_1, sdm845_pp_sblk, + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15)), + PP_BLK("pingpong_4", PINGPONG_4, 0x72000, MERGE_3D_2, sdm845_pp_sblk, + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30), + -1), + PP_BLK("pingpong_5", PINGPONG_5, 0x72800, MERGE_3D_2, sdm845_pp_sblk, + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31), + -1), +}; + +static const struct dpu_merge_3d_cfg sm8250_merge_3d[] = { + MERGE_3D_BLK("merge_3d_0", MERGE_3D_0, 0x83000), + MERGE_3D_BLK("merge_3d_1", MERGE_3D_1, 0x83100), + MERGE_3D_BLK("merge_3d_2", MERGE_3D_2, 0x83200), +}; + +static const struct dpu_dsc_cfg sm8250_dsc[] = { + DSC_BLK("dsc_0", DSC_0, 0x80000, BIT(DPU_DSC_OUTPUT_CTRL)), + DSC_BLK("dsc_1", DSC_1, 0x80400, BIT(DPU_DSC_OUTPUT_CTRL)), + DSC_BLK("dsc_2", DSC_2, 0x80800, BIT(DPU_DSC_OUTPUT_CTRL)), + DSC_BLK("dsc_3", DSC_3, 0x80c00, BIT(DPU_DSC_OUTPUT_CTRL)), +}; + +static const struct dpu_intf_cfg sm8250_intf[] = { + INTF_BLK("intf_0", INTF_0, 0x6a000, 0x280, INTF_DP, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 24, 25), + INTF_BLK("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 26, 27), + INTF_BLK("intf_2", INTF_2, 0x6b000, 0x2c0, INTF_DSI, 1, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 28, 29), + INTF_BLK("intf_3", INTF_3, 0x6b800, 0x280, INTF_DP, 1, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 30, 31), +}; + +static const struct dpu_wb_cfg sm8250_wb[] = { + WB_BLK("wb_2", WB_2, 0x65000, WB_SM8250_MASK, DPU_CLK_CTRL_WB2, 6, + VBIF_RT, MDP_SSPP_TOP0_INTR, 4096, 4), +}; + +static const struct dpu_perf_cfg sm8250_perf_data = { + .max_bw_low = 13700000, + .max_bw_high = 16600000, + .min_core_ib = 4800000, + .min_llcc_ib = 0, + .min_dram_ib = 800000, + .min_prefill_lines = 35, + .danger_lut_tbl = {0xf, 0xffff, 0x0}, + .safe_lut_tbl = {0xfff0, 0xff00, 0xffff}, + .qos_lut_tbl = { + {.nentry = ARRAY_SIZE(sc7180_qos_linear), + .entries = sc7180_qos_linear + }, + {.nentry = ARRAY_SIZE(sc7180_qos_macrotile), + .entries = sc7180_qos_macrotile + }, + {.nentry = ARRAY_SIZE(sc7180_qos_nrt), + .entries = sc7180_qos_nrt + }, + /* TODO: macrotile-qseed is different from macrotile */ + }, + .cdp_cfg = { + {.rd_enable = 1, .wr_enable = 1}, + {.rd_enable = 1, .wr_enable = 0} + }, + .clk_inefficiency_factor = 105, + .bw_inefficiency_factor = 120, +}; + +const struct dpu_mdss_cfg dpu_sm8250_cfg = { + .caps = &sm8250_dpu_caps, + .ubwc = &sm8250_ubwc_cfg, + .mdp_count = ARRAY_SIZE(sm8250_mdp), + .mdp = sm8250_mdp, + .ctl_count = ARRAY_SIZE(sm8250_ctl), + .ctl = sm8250_ctl, + .sspp_count = ARRAY_SIZE(sm8250_sspp), + .sspp = sm8250_sspp, + .mixer_count = ARRAY_SIZE(sm8250_lm), + .mixer = sm8250_lm, + .dspp_count = ARRAY_SIZE(sm8250_dspp), + .dspp = sm8250_dspp, + .dsc_count = ARRAY_SIZE(sm8250_dsc), + .dsc = sm8250_dsc, + .pingpong_count = ARRAY_SIZE(sm8250_pp), + .pingpong = sm8250_pp, + .merge_3d_count = ARRAY_SIZE(sm8250_merge_3d), + .merge_3d = sm8250_merge_3d, + .intf_count = ARRAY_SIZE(sm8250_intf), + .intf = sm8250_intf, + .vbif_count = ARRAY_SIZE(sdm845_vbif), + .vbif = sdm845_vbif, + .wb_count = ARRAY_SIZE(sm8250_wb), + .wb = sm8250_wb, + .reg_dma_count = 1, + .dma_cfg = &sm8250_regdma, + .perf = &sm8250_perf_data, + .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \ + BIT(MDP_SSPP_TOP0_INTR2) | \ + BIT(MDP_SSPP_TOP0_HIST_INTR) | \ + BIT(MDP_INTF0_INTR) | \ + BIT(MDP_INTF1_INTR) | \ + BIT(MDP_INTF2_INTR) | \ + BIT(MDP_INTF3_INTR) | \ + BIT(MDP_INTF4_INTR), +}; + +#endif diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h new file mode 100644 index 000000000000..a46b11730a4d --- /dev/null +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h @@ -0,0 +1,156 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved. + */ + +#ifndef _DPU_6_2_SC7180_H +#define _DPU_6_2_SC7180_H + +static const struct dpu_caps sc7180_dpu_caps = { + .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, + .max_mixer_blendstages = 0x9, + .qseed_type = DPU_SSPP_SCALER_QSEED4, + .has_dim_layer = true, + .has_idle_pc = true, + .max_linewidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH, + .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, +}; + +static const struct dpu_ubwc_cfg sc7180_ubwc_cfg = { + .ubwc_version = DPU_HW_UBWC_VER_20, + .highest_bank_bit = 0x3, +}; + +static const struct dpu_mdp_cfg sc7180_mdp[] = { + { + .name = "top_0", .id = MDP_TOP, + .base = 0x0, .len = 0x494, + .features = 0, + .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, + .clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 }, + .clk_ctrls[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 }, + .clk_ctrls[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2c4, .bit_off = 8 }, + .clk_ctrls[DPU_CLK_CTRL_WB2] = { .reg_off = 0x3b8, .bit_off = 24 }, + }, +}; + +static const struct dpu_ctl_cfg sc7180_ctl[] = { + { + .name = "ctl_0", .id = CTL_0, + .base = 0x1000, .len = 0x1dc, + .features = BIT(DPU_CTL_ACTIVE_CFG), + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), + }, + { + .name = "ctl_1", .id = CTL_1, + .base = 0x1200, .len = 0x1dc, + .features = BIT(DPU_CTL_ACTIVE_CFG), + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), + }, + { + .name = "ctl_2", .id = CTL_2, + .base = 0x1400, .len = 0x1dc, + .features = BIT(DPU_CTL_ACTIVE_CFG), + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), + }, +}; + +static const struct dpu_sspp_cfg sc7180_sspp[] = { + SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_SC7180_MASK, + sc7180_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0), + SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_SDM845_MASK, + sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0), + SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1f8, DMA_CURSOR_SDM845_MASK, + sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1), + SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1f8, DMA_CURSOR_SDM845_MASK, + sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2), +}; + +static const struct dpu_lm_cfg sc7180_lm[] = { + LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK, + &sc7180_lm_sblk, PINGPONG_0, LM_1, DSPP_0), + LM_BLK("lm_1", LM_1, 0x45000, MIXER_SDM845_MASK, + &sc7180_lm_sblk, PINGPONG_1, LM_0, 0), +}; + +static const struct dpu_dspp_cfg sc7180_dspp[] = { + DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK, + &sc7180_dspp_sblk), +}; + +static const struct dpu_pingpong_cfg sc7180_pp[] = { + PP_BLK("pingpong_0", PINGPONG_0, 0x70000, 0, sdm845_pp_sblk, -1, -1), + PP_BLK("pingpong_1", PINGPONG_1, 0x70800, 0, sdm845_pp_sblk, -1, -1), +}; + +static const struct dpu_intf_cfg sc7180_intf[] = { + INTF_BLK("intf_0", INTF_0, 0x6a000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 24, 25), + INTF_BLK("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 26, 27), +}; + +static const struct dpu_wb_cfg sc7180_wb[] = { + WB_BLK("wb_2", WB_2, 0x65000, WB_SM8250_MASK, DPU_CLK_CTRL_WB2, 6, + VBIF_RT, MDP_SSPP_TOP0_INTR, 4096, 4), +}; + +static const struct dpu_perf_cfg sc7180_perf_data = { + .max_bw_low = 6800000, + .max_bw_high = 6800000, + .min_core_ib = 2400000, + .min_llcc_ib = 800000, + .min_dram_ib = 1600000, + .min_prefill_lines = 24, + .danger_lut_tbl = {0xff, 0xffff, 0x0}, + .safe_lut_tbl = {0xfff0, 0xff00, 0xffff}, + .qos_lut_tbl = { + {.nentry = ARRAY_SIZE(sc7180_qos_linear), + .entries = sc7180_qos_linear + }, + {.nentry = ARRAY_SIZE(sc7180_qos_macrotile), + .entries = sc7180_qos_macrotile + }, + {.nentry = ARRAY_SIZE(sc7180_qos_nrt), + .entries = sc7180_qos_nrt + }, + }, + .cdp_cfg = { + {.rd_enable = 1, .wr_enable = 1}, + {.rd_enable = 1, .wr_enable = 0} + }, + .clk_inefficiency_factor = 105, + .bw_inefficiency_factor = 120, +}; + +const struct dpu_mdss_cfg dpu_sc7180_cfg = { + .caps = &sc7180_dpu_caps, + .ubwc = &sc7180_ubwc_cfg, + .mdp_count = ARRAY_SIZE(sc7180_mdp), + .mdp = sc7180_mdp, + .ctl_count = ARRAY_SIZE(sc7180_ctl), + .ctl = sc7180_ctl, + .sspp_count = ARRAY_SIZE(sc7180_sspp), + .sspp = sc7180_sspp, + .mixer_count = ARRAY_SIZE(sc7180_lm), + .mixer = sc7180_lm, + .dspp_count = ARRAY_SIZE(sc7180_dspp), + .dspp = sc7180_dspp, + .pingpong_count = ARRAY_SIZE(sc7180_pp), + .pingpong = sc7180_pp, + .intf_count = ARRAY_SIZE(sc7180_intf), + .intf = sc7180_intf, + .wb_count = ARRAY_SIZE(sc7180_wb), + .wb = sc7180_wb, + .vbif_count = ARRAY_SIZE(sdm845_vbif), + .vbif = sdm845_vbif, + .reg_dma_count = 1, + .dma_cfg = &sdm845_regdma, + .perf = &sc7180_perf_data, + .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \ + BIT(MDP_SSPP_TOP0_INTR2) | \ + BIT(MDP_SSPP_TOP0_HIST_INTR) | \ + BIT(MDP_INTF0_INTR) | \ + BIT(MDP_INTF1_INTR), +}; + +#endif diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h new file mode 100644 index 000000000000..988d820f7ef2 --- /dev/null +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h @@ -0,0 +1,128 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved. + */ + +#ifndef _DPU_6_3_SM6115_H +#define _DPU_6_3_SM6115_H + +static const struct dpu_caps sm6115_dpu_caps = { + .max_mixer_width = DEFAULT_DPU_LINE_WIDTH, + .max_mixer_blendstages = 0x4, + .qseed_type = DPU_SSPP_SCALER_QSEED4, + .has_dim_layer = true, + .has_idle_pc = true, + .max_linewidth = 2160, + .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, +}; + +static const struct dpu_ubwc_cfg sm6115_ubwc_cfg = { + .ubwc_version = DPU_HW_UBWC_VER_10, + .highest_bank_bit = 0x1, + .ubwc_swizzle = 0x7, +}; + +static const struct dpu_mdp_cfg sm6115_mdp[] = { + { + .name = "top_0", .id = MDP_TOP, + .base = 0x0, .len = 0x494, + .features = 0, + .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, + .clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 }, + }, +}; + +static const struct dpu_ctl_cfg sm6115_ctl[] = { + { + .name = "ctl_0", .id = CTL_0, + .base = 0x1000, .len = 0x1dc, + .features = BIT(DPU_CTL_ACTIVE_CFG), + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), + }, +}; + +static const struct dpu_sspp_cfg sm6115_sspp[] = { + SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_SC7180_MASK, + sm6115_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0), + SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_SDM845_MASK, + sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0), +}; + +static const struct dpu_lm_cfg sm6115_lm[] = { + LM_BLK("lm_0", LM_0, 0x44000, MIXER_QCM2290_MASK, + &qcm2290_lm_sblk, PINGPONG_0, 0, DSPP_0), +}; + +static const struct dpu_dspp_cfg sm6115_dspp[] = { + DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK, + &sm8150_dspp_sblk), +}; + +static const struct dpu_pingpong_cfg sm6115_pp[] = { + PP_BLK("pingpong_0", PINGPONG_0, 0x70000, 0, sdm845_pp_sblk, + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12)), +}; + +static const struct dpu_intf_cfg sm6115_intf[] = { + INTF_BLK("intf_0", INTF_0, 0x00000, 0x280, INTF_NONE, 0, 0, 0, 0, 0, 0), + INTF_BLK("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 26, 27), +}; + +static const struct dpu_perf_cfg sm6115_perf_data = { + .max_bw_low = 3100000, + .max_bw_high = 4000000, + .min_core_ib = 2400000, + .min_llcc_ib = 800000, + .min_dram_ib = 800000, + .min_prefill_lines = 24, + .danger_lut_tbl = {0xff, 0xffff, 0x0}, + .safe_lut_tbl = {0xfff0, 0xff00, 0xffff}, + .qos_lut_tbl = { + {.nentry = ARRAY_SIZE(sc7180_qos_linear), + .entries = sc7180_qos_linear + }, + {.nentry = ARRAY_SIZE(sc7180_qos_macrotile), + .entries = sc7180_qos_macrotile + }, + {.nentry = ARRAY_SIZE(sc7180_qos_nrt), + .entries = sc7180_qos_nrt + }, + /* TODO: macrotile-qseed is different from macrotile */ + }, + .cdp_cfg = { + {.rd_enable = 1, .wr_enable = 1}, + {.rd_enable = 1, .wr_enable = 0} + }, + .clk_inefficiency_factor = 105, + .bw_inefficiency_factor = 120, +}; + +const struct dpu_mdss_cfg dpu_sm6115_cfg = { + .caps = &sm6115_dpu_caps, + .ubwc = &sm6115_ubwc_cfg, + .mdp_count = ARRAY_SIZE(sm6115_mdp), + .mdp = sm6115_mdp, + .ctl_count = ARRAY_SIZE(sm6115_ctl), + .ctl = sm6115_ctl, + .sspp_count = ARRAY_SIZE(sm6115_sspp), + .sspp = sm6115_sspp, + .mixer_count = ARRAY_SIZE(sm6115_lm), + .mixer = sm6115_lm, + .dspp_count = ARRAY_SIZE(sm6115_dspp), + .dspp = sm6115_dspp, + .pingpong_count = ARRAY_SIZE(sm6115_pp), + .pingpong = sm6115_pp, + .intf_count = ARRAY_SIZE(sm6115_intf), + .intf = sm6115_intf, + .vbif_count = ARRAY_SIZE(sdm845_vbif), + .vbif = sdm845_vbif, + .perf = &sm6115_perf_data, + .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \ + BIT(MDP_SSPP_TOP0_INTR2) | \ + BIT(MDP_SSPP_TOP0_HIST_INTR) | \ + BIT(MDP_INTF1_INTR), +}; + +#endif diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h new file mode 100644 index 000000000000..c9003dcc1a59 --- /dev/null +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h @@ -0,0 +1,118 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved. + */ + +#ifndef _DPU_6_5_QCM2290_H +#define _DPU_6_5_QCM2290_H + +static const struct dpu_caps qcm2290_dpu_caps = { + .max_mixer_width = DEFAULT_DPU_LINE_WIDTH, + .max_mixer_blendstages = 0x4, + .has_dim_layer = true, + .has_idle_pc = true, + .max_linewidth = 2160, + .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, +}; + +static const struct dpu_ubwc_cfg qcm2290_ubwc_cfg = { + .highest_bank_bit = 0x2, +}; + +static const struct dpu_mdp_cfg qcm2290_mdp[] = { + { + .name = "top_0", .id = MDP_TOP, + .base = 0x0, .len = 0x494, + .features = 0, + .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, + .clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 }, + }, +}; + +static const struct dpu_ctl_cfg qcm2290_ctl[] = { + { + .name = "ctl_0", .id = CTL_0, + .base = 0x1000, .len = 0x1dc, + .features = BIT(DPU_CTL_ACTIVE_CFG), + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), + }, +}; + +static const struct dpu_sspp_cfg qcm2290_sspp[] = { + SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_QCM2290_MASK, + qcm2290_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0), + SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_SDM845_MASK, + qcm2290_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0), +}; + +static const struct dpu_lm_cfg qcm2290_lm[] = { + LM_BLK("lm_0", LM_0, 0x44000, MIXER_QCM2290_MASK, + &qcm2290_lm_sblk, PINGPONG_0, 0, DSPP_0), +}; + +static const struct dpu_dspp_cfg qcm2290_dspp[] = { + DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK, + &sm8150_dspp_sblk), +}; + +static const struct dpu_pingpong_cfg qcm2290_pp[] = { + PP_BLK("pingpong_0", PINGPONG_0, 0x70000, 0, sdm845_pp_sblk, + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12)), +}; + +static const struct dpu_intf_cfg qcm2290_intf[] = { + INTF_BLK("intf_0", INTF_0, 0x00000, 0x280, INTF_NONE, 0, 0, 0, 0, 0, 0), + INTF_BLK("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 26, 27), +}; + +static const struct dpu_perf_cfg qcm2290_perf_data = { + .max_bw_low = 2700000, + .max_bw_high = 2700000, + .min_core_ib = 1300000, + .min_llcc_ib = 0, + .min_dram_ib = 1600000, + .min_prefill_lines = 24, + .danger_lut_tbl = {0xff, 0x0, 0x0}, + .safe_lut_tbl = {0xfff0, 0x0, 0x0}, + .qos_lut_tbl = { + {.nentry = ARRAY_SIZE(qcm2290_qos_linear), + .entries = qcm2290_qos_linear + }, + }, + .cdp_cfg = { + {.rd_enable = 1, .wr_enable = 1}, + {.rd_enable = 1, .wr_enable = 0} + }, + .clk_inefficiency_factor = 105, + .bw_inefficiency_factor = 120, +}; + +const struct dpu_mdss_cfg dpu_qcm2290_cfg = { + .caps = &qcm2290_dpu_caps, + .ubwc = &qcm2290_ubwc_cfg, + .mdp_count = ARRAY_SIZE(qcm2290_mdp), + .mdp = qcm2290_mdp, + .ctl_count = ARRAY_SIZE(qcm2290_ctl), + .ctl = qcm2290_ctl, + .sspp_count = ARRAY_SIZE(qcm2290_sspp), + .sspp = qcm2290_sspp, + .mixer_count = ARRAY_SIZE(qcm2290_lm), + .mixer = qcm2290_lm, + .dspp_count = ARRAY_SIZE(qcm2290_dspp), + .dspp = qcm2290_dspp, + .pingpong_count = ARRAY_SIZE(qcm2290_pp), + .pingpong = qcm2290_pp, + .intf_count = ARRAY_SIZE(qcm2290_intf), + .intf = qcm2290_intf, + .vbif_count = ARRAY_SIZE(sdm845_vbif), + .vbif = sdm845_vbif, + .perf = &qcm2290_perf_data, + .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \ + BIT(MDP_SSPP_TOP0_INTR2) | \ + BIT(MDP_SSPP_TOP0_HIST_INTR) | \ + BIT(MDP_INTF1_INTR), +}; + +#endif diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h new file mode 100644 index 000000000000..4f6a965bcd90 --- /dev/null +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h @@ -0,0 +1,226 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved. + */ + +#ifndef _DPU_7_0_SM8350_H +#define _DPU_7_0_SM8350_H + +static const struct dpu_caps sm8350_dpu_caps = { + .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, + .max_mixer_blendstages = 0xb, + .qseed_type = DPU_SSPP_SCALER_QSEED4, + .has_src_split = true, + .has_dim_layer = true, + .has_idle_pc = true, + .has_3d_merge = true, + .max_linewidth = 4096, + .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, +}; + +static const struct dpu_ubwc_cfg sm8350_ubwc_cfg = { + .ubwc_version = DPU_HW_UBWC_VER_40, + .highest_bank_bit = 0x3, /* TODO: 2 for LP_DDR4 */ +}; + +static const struct dpu_mdp_cfg sm8350_mdp[] = { + { + .name = "top_0", .id = MDP_TOP, + .base = 0x0, .len = 0x494, + .features = 0, + .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, + .clk_ctrls[DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 }, + .clk_ctrls[DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 }, + .clk_ctrls[DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 }, + .clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 }, + .clk_ctrls[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 }, + .clk_ctrls[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 }, + .clk_ctrls[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 }, + .clk_ctrls[DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 }, + }, +}; + +/* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper ACTIVE_CTL support */ +static const struct dpu_ctl_cfg sm8350_ctl[] = { + { + .name = "ctl_0", .id = CTL_0, + .base = 0x15000, .len = 0x1e8, + .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK, + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), + }, + { + .name = "ctl_1", .id = CTL_1, + .base = 0x16000, .len = 0x1e8, + .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK, + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), + }, + { + .name = "ctl_2", .id = CTL_2, + .base = 0x17000, .len = 0x1e8, + .features = CTL_SC7280_MASK, + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), + }, + { + .name = "ctl_3", .id = CTL_3, + .base = 0x18000, .len = 0x1e8, + .features = CTL_SC7280_MASK, + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), + }, + { + .name = "ctl_4", .id = CTL_4, + .base = 0x19000, .len = 0x1e8, + .features = CTL_SC7280_MASK, + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), + }, + { + .name = "ctl_5", .id = CTL_5, + .base = 0x1a000, .len = 0x1e8, + .features = CTL_SC7280_MASK, + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23), + }, +}; + +static const struct dpu_sspp_cfg sm8350_sspp[] = { + SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_SC7180_MASK, + sm8250_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0), + SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, 0x1f8, VIG_SC7180_MASK, + sm8250_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1), + SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, 0x1f8, VIG_SC7180_MASK, + sm8250_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2), + SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, 0x1f8, VIG_SC7180_MASK, + sm8250_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3), + SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_SDM845_MASK, + sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0), + SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1f8, DMA_SDM845_MASK, + sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1), + SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1f8, DMA_CURSOR_SDM845_MASK, + sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2), + SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, 0x1f8, DMA_CURSOR_SDM845_MASK, + sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA3), +}; + +static const struct dpu_lm_cfg sm8350_lm[] = { + LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK, + &sdm845_lm_sblk, PINGPONG_0, LM_1, DSPP_0), + LM_BLK("lm_1", LM_1, 0x45000, MIXER_SDM845_MASK, + &sdm845_lm_sblk, PINGPONG_1, LM_0, DSPP_1), + LM_BLK("lm_2", LM_2, 0x46000, MIXER_SDM845_MASK, + &sdm845_lm_sblk, PINGPONG_2, LM_3, 0), + LM_BLK("lm_3", LM_3, 0x47000, MIXER_SDM845_MASK, + &sdm845_lm_sblk, PINGPONG_3, LM_2, 0), + LM_BLK("lm_4", LM_4, 0x48000, MIXER_SDM845_MASK, + &sdm845_lm_sblk, PINGPONG_4, LM_5, 0), + LM_BLK("lm_5", LM_5, 0x49000, MIXER_SDM845_MASK, + &sdm845_lm_sblk, PINGPONG_5, LM_4, 0), +}; + +static const struct dpu_dspp_cfg sm8350_dspp[] = { + DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK, + &sm8150_dspp_sblk), + DSPP_BLK("dspp_1", DSPP_1, 0x56000, DSPP_SC7180_MASK, + &sm8150_dspp_sblk), + DSPP_BLK("dspp_2", DSPP_2, 0x58000, DSPP_SC7180_MASK, + &sm8150_dspp_sblk), + DSPP_BLK("dspp_3", DSPP_3, 0x5a000, DSPP_SC7180_MASK, + &sm8150_dspp_sblk), +}; + +static const struct dpu_pingpong_cfg sm8350_pp[] = { + PP_BLK_DITHER("pingpong_0", PINGPONG_0, 0x69000, MERGE_3D_0, sc7280_pp_sblk, + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12)), + PP_BLK_DITHER("pingpong_1", PINGPONG_1, 0x6a000, MERGE_3D_0, sc7280_pp_sblk, + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13)), + PP_BLK_DITHER("pingpong_2", PINGPONG_2, 0x6b000, MERGE_3D_1, sc7280_pp_sblk, + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14)), + PP_BLK_DITHER("pingpong_3", PINGPONG_3, 0x6c000, MERGE_3D_1, sc7280_pp_sblk, + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15)), + PP_BLK_DITHER("pingpong_4", PINGPONG_4, 0x6d000, MERGE_3D_2, sc7280_pp_sblk, + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30), + -1), + PP_BLK_DITHER("pingpong_5", PINGPONG_5, 0x6e000, MERGE_3D_2, sc7280_pp_sblk, + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31), + -1), +}; + +static const struct dpu_merge_3d_cfg sm8350_merge_3d[] = { + MERGE_3D_BLK("merge_3d_0", MERGE_3D_0, 0x4e000), + MERGE_3D_BLK("merge_3d_1", MERGE_3D_1, 0x4f000), + MERGE_3D_BLK("merge_3d_2", MERGE_3D_2, 0x50000), +}; + +static const struct dpu_intf_cfg sm8350_intf[] = { + INTF_BLK("intf_0", INTF_0, 0x34000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 24, 25), + INTF_BLK("intf_1", INTF_1, 0x35000, 0x2c4, INTF_DSI, 0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 26, 27), + INTF_BLK("intf_2", INTF_2, 0x36000, 0x2c4, INTF_DSI, 1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 28, 29), + INTF_BLK("intf_3", INTF_3, 0x37000, 0x280, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 30, 31), +}; + +static const struct dpu_perf_cfg sm8350_perf_data = { + .max_bw_low = 11800000, + .max_bw_high = 15500000, + .min_core_ib = 2500000, + .min_llcc_ib = 0, + .min_dram_ib = 800000, + .min_prefill_lines = 40, + /* FIXME: lut tables */ + .danger_lut_tbl = {0x3ffff, 0x3ffff, 0x0}, + .safe_lut_tbl = {0xfe00, 0xfe00, 0xffff}, + .qos_lut_tbl = { + {.nentry = ARRAY_SIZE(sc7180_qos_linear), + .entries = sc7180_qos_linear + }, + {.nentry = ARRAY_SIZE(sc7180_qos_macrotile), + .entries = sc7180_qos_macrotile + }, + {.nentry = ARRAY_SIZE(sc7180_qos_nrt), + .entries = sc7180_qos_nrt + }, + /* TODO: macrotile-qseed is different from macrotile */ + }, + .cdp_cfg = { + {.rd_enable = 1, .wr_enable = 1}, + {.rd_enable = 1, .wr_enable = 0} + }, + .clk_inefficiency_factor = 105, + .bw_inefficiency_factor = 120, +}; + +const struct dpu_mdss_cfg dpu_sm8350_cfg = { + .caps = &sm8350_dpu_caps, + .ubwc = &sm8350_ubwc_cfg, + .mdp_count = ARRAY_SIZE(sm8350_mdp), + .mdp = sm8350_mdp, + .ctl_count = ARRAY_SIZE(sm8350_ctl), + .ctl = sm8350_ctl, + .sspp_count = ARRAY_SIZE(sm8350_sspp), + .sspp = sm8350_sspp, + .mixer_count = ARRAY_SIZE(sm8350_lm), + .mixer = sm8350_lm, + .dspp_count = ARRAY_SIZE(sm8350_dspp), + .dspp = sm8350_dspp, + .pingpong_count = ARRAY_SIZE(sm8350_pp), + .pingpong = sm8350_pp, + .merge_3d_count = ARRAY_SIZE(sm8350_merge_3d), + .merge_3d = sm8350_merge_3d, + .intf_count = ARRAY_SIZE(sm8350_intf), + .intf = sm8350_intf, + .vbif_count = ARRAY_SIZE(sdm845_vbif), + .vbif = sdm845_vbif, + .reg_dma_count = 1, + .dma_cfg = &sm8350_regdma, + .perf = &sm8350_perf_data, + .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \ + BIT(MDP_SSPP_TOP0_INTR2) | \ + BIT(MDP_SSPP_TOP0_HIST_INTR) | \ + BIT(MDP_INTF0_7xxx_INTR) | \ + BIT(MDP_INTF1_7xxx_INTR) | \ + BIT(MDP_INTF2_7xxx_INTR) | \ + BIT(MDP_INTF3_7xxx_INTR), +}; + +#endif diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h new file mode 100644 index 000000000000..6b2c7eae71d9 --- /dev/null +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h @@ -0,0 +1,158 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved. + */ + +#ifndef _DPU_7_2_SC7280_H +#define _DPU_7_2_SC7280_H + +static const struct dpu_caps sc7280_dpu_caps = { + .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, + .max_mixer_blendstages = 0x7, + .qseed_type = DPU_SSPP_SCALER_QSEED4, + .has_dim_layer = true, + .has_idle_pc = true, + .max_linewidth = 2400, + .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, +}; + +static const struct dpu_ubwc_cfg sc7280_ubwc_cfg = { + .ubwc_version = DPU_HW_UBWC_VER_30, + .highest_bank_bit = 0x1, + .ubwc_swizzle = 0x6, +}; + +static const struct dpu_mdp_cfg sc7280_mdp[] = { + { + .name = "top_0", .id = MDP_TOP, + .base = 0x0, .len = 0x2014, + .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, + .clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 }, + .clk_ctrls[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 }, + .clk_ctrls[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2c4, .bit_off = 8 }, + }, +}; + +static const struct dpu_ctl_cfg sc7280_ctl[] = { + { + .name = "ctl_0", .id = CTL_0, + .base = 0x15000, .len = 0x1e8, + .features = CTL_SC7280_MASK, + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), + }, + { + .name = "ctl_1", .id = CTL_1, + .base = 0x16000, .len = 0x1e8, + .features = CTL_SC7280_MASK, + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), + }, + { + .name = "ctl_2", .id = CTL_2, + .base = 0x17000, .len = 0x1e8, + .features = CTL_SC7280_MASK, + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), + }, + { + .name = "ctl_3", .id = CTL_3, + .base = 0x18000, .len = 0x1e8, + .features = CTL_SC7280_MASK, + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), + }, +}; + +static const struct dpu_sspp_cfg sc7280_sspp[] = { + SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_SC7280_MASK_SDMA, + sc7280_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0), + SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_SDM845_MASK_SDMA, + sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0), + SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1f8, DMA_CURSOR_SDM845_MASK_SDMA, + sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1), + SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1f8, DMA_CURSOR_SDM845_MASK_SDMA, + sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2), +}; + +static const struct dpu_lm_cfg sc7280_lm[] = { + LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK, + &sc7180_lm_sblk, PINGPONG_0, 0, DSPP_0), + LM_BLK("lm_2", LM_2, 0x46000, MIXER_SDM845_MASK, + &sc7180_lm_sblk, PINGPONG_2, LM_3, 0), + LM_BLK("lm_3", LM_3, 0x47000, MIXER_SDM845_MASK, + &sc7180_lm_sblk, PINGPONG_3, LM_2, 0), +}; + +static const struct dpu_dspp_cfg sc7280_dspp[] = { + DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK, + &sc7180_dspp_sblk), +}; + +static const struct dpu_pingpong_cfg sc7280_pp[] = { + PP_BLK_DITHER("pingpong_0", PINGPONG_0, 0x69000, 0, sc7280_pp_sblk, -1, -1), + PP_BLK_DITHER("pingpong_1", PINGPONG_1, 0x6a000, 0, sc7280_pp_sblk, -1, -1), + PP_BLK_DITHER("pingpong_2", PINGPONG_2, 0x6b000, 0, sc7280_pp_sblk, -1, -1), + PP_BLK_DITHER("pingpong_3", PINGPONG_3, 0x6c000, 0, sc7280_pp_sblk, -1, -1), +}; + +static const struct dpu_intf_cfg sc7280_intf[] = { + INTF_BLK("intf_0", INTF_0, 0x34000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 24, 25), + INTF_BLK("intf_1", INTF_1, 0x35000, 0x2c4, INTF_DSI, 0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 26, 27), + INTF_BLK("intf_5", INTF_5, 0x39000, 0x280, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 22, 23), +}; + +static const struct dpu_perf_cfg sc7280_perf_data = { + .max_bw_low = 4700000, + .max_bw_high = 8800000, + .min_core_ib = 2500000, + .min_llcc_ib = 0, + .min_dram_ib = 1600000, + .min_prefill_lines = 24, + .danger_lut_tbl = {0xffff, 0xffff, 0x0}, + .safe_lut_tbl = {0xff00, 0xff00, 0xffff}, + .qos_lut_tbl = { + {.nentry = ARRAY_SIZE(sc7180_qos_macrotile), + .entries = sc7180_qos_macrotile + }, + {.nentry = ARRAY_SIZE(sc7180_qos_macrotile), + .entries = sc7180_qos_macrotile + }, + {.nentry = ARRAY_SIZE(sc7180_qos_nrt), + .entries = sc7180_qos_nrt + }, + }, + .cdp_cfg = { + {.rd_enable = 1, .wr_enable = 1}, + {.rd_enable = 1, .wr_enable = 0} + }, + .clk_inefficiency_factor = 105, + .bw_inefficiency_factor = 120, +}; + +const struct dpu_mdss_cfg dpu_sc7280_cfg = { + .caps = &sc7280_dpu_caps, + .ubwc = &sc7280_ubwc_cfg, + .mdp_count = ARRAY_SIZE(sc7280_mdp), + .mdp = sc7280_mdp, + .ctl_count = ARRAY_SIZE(sc7280_ctl), + .ctl = sc7280_ctl, + .sspp_count = ARRAY_SIZE(sc7280_sspp), + .sspp = sc7280_sspp, + .dspp_count = ARRAY_SIZE(sc7280_dspp), + .dspp = sc7280_dspp, + .mixer_count = ARRAY_SIZE(sc7280_lm), + .mixer = sc7280_lm, + .pingpong_count = ARRAY_SIZE(sc7280_pp), + .pingpong = sc7280_pp, + .intf_count = ARRAY_SIZE(sc7280_intf), + .intf = sc7280_intf, + .vbif_count = ARRAY_SIZE(sdm845_vbif), + .vbif = sdm845_vbif, + .perf = &sc7280_perf_data, + .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \ + BIT(MDP_SSPP_TOP0_INTR2) | \ + BIT(MDP_SSPP_TOP0_HIST_INTR) | \ + BIT(MDP_INTF0_7xxx_INTR) | \ + BIT(MDP_INTF1_7xxx_INTR) | \ + BIT(MDP_INTF5_7xxx_INTR), +}; + +#endif diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h new file mode 100644 index 000000000000..706d0f13b598 --- /dev/null +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h @@ -0,0 +1,222 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved. + */ + +#ifndef _DPU_8_0_SC8280XP_H +#define _DPU_8_0_SC8280XP_H + +static const struct dpu_caps sc8280xp_dpu_caps = { + .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, + .max_mixer_blendstages = 11, + .qseed_type = DPU_SSPP_SCALER_QSEED4, + .has_src_split = true, + .has_dim_layer = true, + .has_idle_pc = true, + .has_3d_merge = true, + .max_linewidth = 5120, + .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, +}; + +static const struct dpu_ubwc_cfg sc8280xp_ubwc_cfg = { + .ubwc_version = DPU_HW_UBWC_VER_40, + .highest_bank_bit = 2, + .ubwc_swizzle = 6, +}; + +static const struct dpu_mdp_cfg sc8280xp_mdp[] = { + { + .name = "top_0", .id = MDP_TOP, + .base = 0x0, .len = 0x494, + .features = BIT(DPU_MDP_PERIPH_0_REMOVED), + .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, + .clk_ctrls[DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 }, + .clk_ctrls[DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 }, + .clk_ctrls[DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 }, + .clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 }, + .clk_ctrls[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 }, + .clk_ctrls[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 }, + .clk_ctrls[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 }, + .clk_ctrls[DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 }, + }, +}; + +static const struct dpu_ctl_cfg sc8280xp_ctl[] = { + { + .name = "ctl_0", .id = CTL_0, + .base = 0x15000, .len = 0x204, + .features = CTL_SC7280_MASK, + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), + }, + { + .name = "ctl_1", .id = CTL_1, + .base = 0x16000, .len = 0x204, + .features = CTL_SC7280_MASK, + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), + }, + { + .name = "ctl_2", .id = CTL_2, + .base = 0x17000, .len = 0x204, + .features = CTL_SC7280_MASK, + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), + }, + { + .name = "ctl_3", .id = CTL_3, + .base = 0x18000, .len = 0x204, + .features = CTL_SC7280_MASK, + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), + }, + { + .name = "ctl_4", .id = CTL_4, + .base = 0x19000, .len = 0x204, + .features = CTL_SC7280_MASK, + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), + }, + { + .name = "ctl_5", .id = CTL_5, + .base = 0x1a000, .len = 0x204, + .features = CTL_SC7280_MASK, + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23), + }, +}; + +static const struct dpu_sspp_cfg sc8280xp_sspp[] = { + SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x2ac, VIG_SC7180_MASK, + sm8250_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0), + SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, 0x2ac, VIG_SC7180_MASK, + sm8250_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1), + SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, 0x2ac, VIG_SC7180_MASK, + sm8250_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2), + SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, 0x2ac, VIG_SC7180_MASK, + sm8250_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3), + SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x2ac, DMA_SDM845_MASK, + sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0), + SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x2ac, DMA_SDM845_MASK, + sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1), + SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x2ac, DMA_CURSOR_SDM845_MASK, + sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2), + SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, 0x2ac, DMA_CURSOR_SDM845_MASK, + sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA3), +}; + +static const struct dpu_lm_cfg sc8280xp_lm[] = { + LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK, &sdm845_lm_sblk, PINGPONG_0, LM_1, DSPP_0), + LM_BLK("lm_1", LM_1, 0x45000, MIXER_SDM845_MASK, &sdm845_lm_sblk, PINGPONG_1, LM_0, DSPP_1), + LM_BLK("lm_2", LM_2, 0x46000, MIXER_SDM845_MASK, &sdm845_lm_sblk, PINGPONG_2, LM_3, DSPP_2), + LM_BLK("lm_3", LM_3, 0x47000, MIXER_SDM845_MASK, &sdm845_lm_sblk, PINGPONG_3, LM_2, DSPP_3), + LM_BLK("lm_4", LM_4, 0x48000, MIXER_SDM845_MASK, &sdm845_lm_sblk, PINGPONG_4, LM_5, 0), + LM_BLK("lm_5", LM_5, 0x49000, MIXER_SDM845_MASK, &sdm845_lm_sblk, PINGPONG_5, LM_4, 0), +}; + +static const struct dpu_dspp_cfg sc8280xp_dspp[] = { + DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK, + &sm8150_dspp_sblk), + DSPP_BLK("dspp_1", DSPP_1, 0x56000, DSPP_SC7180_MASK, + &sm8150_dspp_sblk), + DSPP_BLK("dspp_2", DSPP_2, 0x58000, DSPP_SC7180_MASK, + &sm8150_dspp_sblk), + DSPP_BLK("dspp_3", DSPP_3, 0x5a000, DSPP_SC7180_MASK, + &sm8150_dspp_sblk), +}; + +static const struct dpu_pingpong_cfg sc8280xp_pp[] = { + PP_BLK_DITHER("pingpong_0", PINGPONG_0, 0x69000, MERGE_3D_0, sc7280_pp_sblk, + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), -1), + PP_BLK_DITHER("pingpong_1", PINGPONG_1, 0x6a000, MERGE_3D_0, sc7280_pp_sblk, + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), -1), + PP_BLK_DITHER("pingpong_2", PINGPONG_2, 0x6b000, MERGE_3D_1, sc7280_pp_sblk, + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), -1), + PP_BLK_DITHER("pingpong_3", PINGPONG_3, 0x6c000, MERGE_3D_1, sc7280_pp_sblk, + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), -1), + PP_BLK_DITHER("pingpong_4", PINGPONG_4, 0x6d000, MERGE_3D_2, sc7280_pp_sblk, + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30), -1), + PP_BLK_DITHER("pingpong_5", PINGPONG_5, 0x6e000, MERGE_3D_2, sc7280_pp_sblk, + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31), -1), +}; + +static const struct dpu_merge_3d_cfg sc8280xp_merge_3d[] = { + MERGE_3D_BLK("merge_3d_0", MERGE_3D_0, 0x4e000), + MERGE_3D_BLK("merge_3d_1", MERGE_3D_1, 0x4f000), + MERGE_3D_BLK("merge_3d_2", MERGE_3D_2, 0x50000), +}; + +/* TODO: INTF 3, 8 and 7 are used for MST, marked as INTF_NONE for now */ +static const struct dpu_intf_cfg sc8280xp_intf[] = { + INTF_BLK("intf_0", INTF_0, 0x34000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 24, 25), + INTF_BLK("intf_1", INTF_1, 0x35000, 0x300, INTF_DSI, 0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 26, 27), + INTF_BLK("intf_2", INTF_2, 0x36000, 0x300, INTF_DSI, 1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 28, 29), + INTF_BLK("intf_3", INTF_3, 0x37000, 0x280, INTF_NONE, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 30, 31), + INTF_BLK("intf_4", INTF_4, 0x38000, 0x280, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 20, 21), + INTF_BLK("intf_5", INTF_5, 0x39000, 0x280, INTF_DP, MSM_DP_CONTROLLER_3, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 22, 23), + INTF_BLK("intf_6", INTF_6, 0x3a000, 0x280, INTF_DP, MSM_DP_CONTROLLER_2, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 16, 17), + INTF_BLK("intf_7", INTF_7, 0x3b000, 0x280, INTF_NONE, MSM_DP_CONTROLLER_2, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 18, 19), + INTF_BLK("intf_8", INTF_8, 0x3c000, 0x280, INTF_NONE, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 12, 13), +}; + +static const struct dpu_perf_cfg sc8280xp_perf_data = { + .max_bw_low = 13600000, + .max_bw_high = 18200000, + .min_core_ib = 2500000, + .min_llcc_ib = 0, + .min_dram_ib = 800000, + .danger_lut_tbl = {0xf, 0xffff, 0x0}, + .qos_lut_tbl = { + {.nentry = ARRAY_SIZE(sc8180x_qos_linear), + .entries = sc8180x_qos_linear + }, + {.nentry = ARRAY_SIZE(sc8180x_qos_macrotile), + .entries = sc8180x_qos_macrotile + }, + {.nentry = ARRAY_SIZE(sc7180_qos_nrt), + .entries = sc7180_qos_nrt + }, + /* TODO: macrotile-qseed is different from macrotile */ + }, + .cdp_cfg = { + {.rd_enable = 1, .wr_enable = 1}, + {.rd_enable = 1, .wr_enable = 0} + }, + .clk_inefficiency_factor = 105, + .bw_inefficiency_factor = 120, +}; + +const struct dpu_mdss_cfg dpu_sc8280xp_cfg = { + .caps = &sc8280xp_dpu_caps, + .ubwc = &sc8280xp_ubwc_cfg, + .mdp_count = ARRAY_SIZE(sc8280xp_mdp), + .mdp = sc8280xp_mdp, + .ctl_count = ARRAY_SIZE(sc8280xp_ctl), + .ctl = sc8280xp_ctl, + .sspp_count = ARRAY_SIZE(sc8280xp_sspp), + .sspp = sc8280xp_sspp, + .mixer_count = ARRAY_SIZE(sc8280xp_lm), + .mixer = sc8280xp_lm, + .dspp_count = ARRAY_SIZE(sc8280xp_dspp), + .dspp = sc8280xp_dspp, + .pingpong_count = ARRAY_SIZE(sc8280xp_pp), + .pingpong = sc8280xp_pp, + .merge_3d_count = ARRAY_SIZE(sc8280xp_merge_3d), + .merge_3d = sc8280xp_merge_3d, + .intf_count = ARRAY_SIZE(sc8280xp_intf), + .intf = sc8280xp_intf, + .vbif_count = ARRAY_SIZE(sdm845_vbif), + .vbif = sdm845_vbif, + .reg_dma_count = 1, + .dma_cfg = &sc8280xp_regdma, + .perf = &sc8280xp_perf_data, + .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \ + BIT(MDP_SSPP_TOP0_INTR2) | \ + BIT(MDP_SSPP_TOP0_HIST_INTR) | \ + BIT(MDP_INTF0_7xxx_INTR) | \ + BIT(MDP_INTF1_7xxx_INTR) | \ + BIT(MDP_INTF2_7xxx_INTR) | \ + BIT(MDP_INTF3_7xxx_INTR) | \ + BIT(MDP_INTF4_7xxx_INTR) | \ + BIT(MDP_INTF5_7xxx_INTR) | \ + BIT(MDP_INTF6_7xxx_INTR) | \ + BIT(MDP_INTF7_7xxx_INTR) | \ + BIT(MDP_INTF8_7xxx_INTR), +}; + +#endif diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h new file mode 100644 index 000000000000..4ecb3df5cbc0 --- /dev/null +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h @@ -0,0 +1,234 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved. + */ + +#ifndef _DPU_8_1_SM8450_H +#define _DPU_8_1_SM8450_H + +static const struct dpu_caps sm8450_dpu_caps = { + .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, + .max_mixer_blendstages = 0xb, + .qseed_type = DPU_SSPP_SCALER_QSEED4, + .has_src_split = true, + .has_dim_layer = true, + .has_idle_pc = true, + .has_3d_merge = true, + .max_linewidth = 5120, + .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, +}; + +static const struct dpu_ubwc_cfg sm8450_ubwc_cfg = { + .ubwc_version = DPU_HW_UBWC_VER_40, + .highest_bank_bit = 0x3, /* TODO: 2 for LP_DDR4 */ + .ubwc_swizzle = 0x6, +}; + +static const struct dpu_mdp_cfg sm8450_mdp[] = { + { + .name = "top_0", .id = MDP_TOP, + .base = 0x0, .len = 0x494, + .features = BIT(DPU_MDP_PERIPH_0_REMOVED), + .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, + .clk_ctrls[DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 }, + .clk_ctrls[DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 }, + .clk_ctrls[DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 }, + .clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 }, + .clk_ctrls[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 }, + .clk_ctrls[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 }, + .clk_ctrls[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 }, + .clk_ctrls[DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 }, + }, +}; + +/* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper ACTIVE_CTL support */ +static const struct dpu_ctl_cfg sm8450_ctl[] = { + { + .name = "ctl_0", .id = CTL_0, + .base = 0x15000, .len = 0x204, + .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY) | BIT(DPU_CTL_FETCH_ACTIVE), + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), + }, + { + .name = "ctl_1", .id = CTL_1, + .base = 0x16000, .len = 0x204, + .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK, + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), + }, + { + .name = "ctl_2", .id = CTL_2, + .base = 0x17000, .len = 0x204, + .features = CTL_SC7280_MASK, + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), + }, + { + .name = "ctl_3", .id = CTL_3, + .base = 0x18000, .len = 0x204, + .features = CTL_SC7280_MASK, + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), + }, + { + .name = "ctl_4", .id = CTL_4, + .base = 0x19000, .len = 0x204, + .features = CTL_SC7280_MASK, + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), + }, + { + .name = "ctl_5", .id = CTL_5, + .base = 0x1a000, .len = 0x204, + .features = CTL_SC7280_MASK, + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23), + }, +}; + +static const struct dpu_sspp_cfg sm8450_sspp[] = { + SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x32c, VIG_SC7180_MASK, + sm8250_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0), + SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, 0x32c, VIG_SC7180_MASK, + sm8250_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1), + SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, 0x32c, VIG_SC7180_MASK, + sm8250_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2), + SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, 0x32c, VIG_SC7180_MASK, + sm8250_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3), + SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x32c, DMA_SDM845_MASK, + sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0), + SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x32c, DMA_SDM845_MASK, + sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1), + SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x32c, DMA_CURSOR_SDM845_MASK, + sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2), + SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, 0x32c, DMA_CURSOR_SDM845_MASK, + sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA3), +}; + +static const struct dpu_lm_cfg sm8450_lm[] = { + LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK, + &sdm845_lm_sblk, PINGPONG_0, LM_1, DSPP_0), + LM_BLK("lm_1", LM_1, 0x45000, MIXER_SDM845_MASK, + &sdm845_lm_sblk, PINGPONG_1, LM_0, DSPP_1), + LM_BLK("lm_2", LM_2, 0x46000, MIXER_SDM845_MASK, + &sdm845_lm_sblk, PINGPONG_2, LM_3, 0), + LM_BLK("lm_3", LM_3, 0x47000, MIXER_SDM845_MASK, + &sdm845_lm_sblk, PINGPONG_3, LM_2, 0), + LM_BLK("lm_4", LM_4, 0x48000, MIXER_SDM845_MASK, + &sdm845_lm_sblk, PINGPONG_4, LM_5, 0), + LM_BLK("lm_5", LM_5, 0x49000, MIXER_SDM845_MASK, + &sdm845_lm_sblk, PINGPONG_5, LM_4, 0), +}; + +static const struct dpu_dspp_cfg sm8450_dspp[] = { + DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK, + &sm8150_dspp_sblk), + DSPP_BLK("dspp_1", DSPP_1, 0x56000, DSPP_SC7180_MASK, + &sm8150_dspp_sblk), + DSPP_BLK("dspp_2", DSPP_2, 0x58000, DSPP_SC7180_MASK, + &sm8150_dspp_sblk), + DSPP_BLK("dspp_3", DSPP_3, 0x5a000, DSPP_SC7180_MASK, + &sm8150_dspp_sblk), +}; +/* FIXME: interrupts */ +static const struct dpu_pingpong_cfg sm8450_pp[] = { + PP_BLK_DITHER("pingpong_0", PINGPONG_0, 0x69000, MERGE_3D_0, sc7280_pp_sblk, + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12)), + PP_BLK_DITHER("pingpong_1", PINGPONG_1, 0x6a000, MERGE_3D_0, sc7280_pp_sblk, + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13)), + PP_BLK_DITHER("pingpong_2", PINGPONG_2, 0x6b000, MERGE_3D_1, sc7280_pp_sblk, + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14)), + PP_BLK_DITHER("pingpong_3", PINGPONG_3, 0x6c000, MERGE_3D_1, sc7280_pp_sblk, + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15)), + PP_BLK_DITHER("pingpong_4", PINGPONG_4, 0x6d000, MERGE_3D_2, sc7280_pp_sblk, + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30), + -1), + PP_BLK_DITHER("pingpong_5", PINGPONG_5, 0x6e000, MERGE_3D_2, sc7280_pp_sblk, + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31), + -1), + PP_BLK_DITHER("pingpong_6", PINGPONG_6, 0x65800, MERGE_3D_3, sc7280_pp_sblk, + -1, + -1), + PP_BLK_DITHER("pingpong_7", PINGPONG_7, 0x65c00, MERGE_3D_3, sc7280_pp_sblk, + -1, + -1), +}; + +static const struct dpu_merge_3d_cfg sm8450_merge_3d[] = { + MERGE_3D_BLK("merge_3d_0", MERGE_3D_0, 0x4e000), + MERGE_3D_BLK("merge_3d_1", MERGE_3D_1, 0x4f000), + MERGE_3D_BLK("merge_3d_2", MERGE_3D_2, 0x50000), + MERGE_3D_BLK("merge_3d_3", MERGE_3D_3, 0x65f00), +}; + +static const struct dpu_intf_cfg sm8450_intf[] = { + INTF_BLK("intf_0", INTF_0, 0x34000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 24, 25), + INTF_BLK("intf_1", INTF_1, 0x35000, 0x300, INTF_DSI, 0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 26, 27), + INTF_BLK("intf_2", INTF_2, 0x36000, 0x300, INTF_DSI, 1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 28, 29), + INTF_BLK("intf_3", INTF_3, 0x37000, 0x280, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 30, 31), +}; + +static const struct dpu_perf_cfg sm8450_perf_data = { + .max_bw_low = 13600000, + .max_bw_high = 18200000, + .min_core_ib = 2500000, + .min_llcc_ib = 0, + .min_dram_ib = 800000, + .min_prefill_lines = 35, + /* FIXME: lut tables */ + .danger_lut_tbl = {0x3ffff, 0x3ffff, 0x0}, + .safe_lut_tbl = {0xfe00, 0xfe00, 0xffff}, + .qos_lut_tbl = { + {.nentry = ARRAY_SIZE(sc7180_qos_linear), + .entries = sc7180_qos_linear + }, + {.nentry = ARRAY_SIZE(sc7180_qos_macrotile), + .entries = sc7180_qos_macrotile + }, + {.nentry = ARRAY_SIZE(sc7180_qos_nrt), + .entries = sc7180_qos_nrt + }, + /* TODO: macrotile-qseed is different from macrotile */ + }, + .cdp_cfg = { + {.rd_enable = 1, .wr_enable = 1}, + {.rd_enable = 1, .wr_enable = 0} + }, + .clk_inefficiency_factor = 105, + .bw_inefficiency_factor = 120, +}; + +const struct dpu_mdss_cfg dpu_sm8450_cfg = { + .caps = &sm8450_dpu_caps, + .ubwc = &sm8450_ubwc_cfg, + .mdp_count = ARRAY_SIZE(sm8450_mdp), + .mdp = sm8450_mdp, + .ctl_count = ARRAY_SIZE(sm8450_ctl), + .ctl = sm8450_ctl, + .sspp_count = ARRAY_SIZE(sm8450_sspp), + .sspp = sm8450_sspp, + .mixer_count = ARRAY_SIZE(sm8450_lm), + .mixer = sm8450_lm, + .dspp_count = ARRAY_SIZE(sm8450_dspp), + .dspp = sm8450_dspp, + .pingpong_count = ARRAY_SIZE(sm8450_pp), + .pingpong = sm8450_pp, + .merge_3d_count = ARRAY_SIZE(sm8450_merge_3d), + .merge_3d = sm8450_merge_3d, + .intf_count = ARRAY_SIZE(sm8450_intf), + .intf = sm8450_intf, + .vbif_count = ARRAY_SIZE(sdm845_vbif), + .vbif = sdm845_vbif, + .reg_dma_count = 1, + .dma_cfg = &sm8450_regdma, + .perf = &sm8450_perf_data, + .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \ + BIT(MDP_SSPP_TOP0_INTR2) | \ + BIT(MDP_SSPP_TOP0_HIST_INTR) | \ + BIT(MDP_INTF0_7xxx_INTR) | \ + BIT(MDP_INTF1_7xxx_INTR) | \ + BIT(MDP_INTF2_7xxx_INTR) | \ + BIT(MDP_INTF3_7xxx_INTR), +}; + +#endif diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h new file mode 100644 index 000000000000..d0ab351b6a8b --- /dev/null +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h @@ -0,0 +1,239 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved. + */ + +#ifndef _DPU_9_0_SM8550_H +#define _DPU_9_0_SM8550_H + +static const struct dpu_caps sm8550_dpu_caps = { + .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, + .max_mixer_blendstages = 0xb, + .qseed_type = DPU_SSPP_SCALER_QSEED4, + .has_src_split = true, + .has_dim_layer = true, + .has_idle_pc = true, + .has_3d_merge = true, + .max_linewidth = 5120, + .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, +}; + +static const struct dpu_ubwc_cfg sm8550_ubwc_cfg = { + .ubwc_version = DPU_HW_UBWC_VER_40, + .highest_bank_bit = 0x3, /* TODO: 2 for LP_DDR4 */ +}; + +static const struct dpu_mdp_cfg sm8550_mdp[] = { + { + .name = "top_0", .id = MDP_TOP, + .base = 0, .len = 0x494, + .features = BIT(DPU_MDP_PERIPH_0_REMOVED), + .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x4330, .bit_off = 0 }, + .clk_ctrls[DPU_CLK_CTRL_VIG1] = { .reg_off = 0x6330, .bit_off = 0 }, + .clk_ctrls[DPU_CLK_CTRL_VIG2] = { .reg_off = 0x8330, .bit_off = 0 }, + .clk_ctrls[DPU_CLK_CTRL_VIG3] = { .reg_off = 0xa330, .bit_off = 0 }, + .clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x24330, .bit_off = 0 }, + .clk_ctrls[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x26330, .bit_off = 0 }, + .clk_ctrls[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x28330, .bit_off = 0 }, + .clk_ctrls[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2a330, .bit_off = 0 }, + .clk_ctrls[DPU_CLK_CTRL_DMA4] = { .reg_off = 0x2c330, .bit_off = 0 }, + .clk_ctrls[DPU_CLK_CTRL_DMA5] = { .reg_off = 0x2e330, .bit_off = 0 }, + .clk_ctrls[DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 }, + }, +}; + +/* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper ACTIVE_CTL support */ +static const struct dpu_ctl_cfg sm8550_ctl[] = { + { + .name = "ctl_0", .id = CTL_0, + .base = 0x15000, .len = 0x290, + .features = CTL_SM8550_MASK | BIT(DPU_CTL_SPLIT_DISPLAY), + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), + }, + { + .name = "ctl_1", .id = CTL_1, + .base = 0x16000, .len = 0x290, + .features = CTL_SM8550_MASK | BIT(DPU_CTL_SPLIT_DISPLAY), + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), + }, + { + .name = "ctl_2", .id = CTL_2, + .base = 0x17000, .len = 0x290, + .features = CTL_SM8550_MASK, + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), + }, + { + .name = "ctl_3", .id = CTL_3, + .base = 0x18000, .len = 0x290, + .features = CTL_SM8550_MASK, + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), + }, + { + .name = "ctl_4", .id = CTL_4, + .base = 0x19000, .len = 0x290, + .features = CTL_SM8550_MASK, + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), + }, + { + .name = "ctl_5", .id = CTL_5, + .base = 0x1a000, .len = 0x290, + .features = CTL_SM8550_MASK, + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23), + }, +}; + +static const struct dpu_sspp_cfg sm8550_sspp[] = { + SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x344, VIG_SC7180_MASK, + sm8550_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0), + SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, 0x344, VIG_SC7180_MASK, + sm8550_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1), + SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, 0x344, VIG_SC7180_MASK, + sm8550_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2), + SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, 0x344, VIG_SC7180_MASK, + sm8550_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3), + SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x344, DMA_SDM845_MASK, + sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0), + SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x344, DMA_SDM845_MASK, + sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1), + SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x344, DMA_SDM845_MASK, + sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2), + SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, 0x344, DMA_SDM845_MASK, + sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA3), + SSPP_BLK("sspp_12", SSPP_DMA4, 0x2c000, 0x344, DMA_CURSOR_SDM845_MASK, + sm8550_dma_sblk_4, 14, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA4), + SSPP_BLK("sspp_13", SSPP_DMA5, 0x2e000, 0x344, DMA_CURSOR_SDM845_MASK, + sm8550_dma_sblk_5, 15, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA5), +}; + +static const struct dpu_lm_cfg sm8550_lm[] = { + LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK, + &sdm845_lm_sblk, PINGPONG_0, LM_1, DSPP_0), + LM_BLK("lm_1", LM_1, 0x45000, MIXER_SDM845_MASK, + &sdm845_lm_sblk, PINGPONG_1, LM_0, DSPP_1), + LM_BLK("lm_2", LM_2, 0x46000, MIXER_SDM845_MASK, + &sdm845_lm_sblk, PINGPONG_2, LM_3, 0), + LM_BLK("lm_3", LM_3, 0x47000, MIXER_SDM845_MASK, + &sdm845_lm_sblk, PINGPONG_3, LM_2, 0), + LM_BLK("lm_4", LM_4, 0x48000, MIXER_SDM845_MASK, + &sdm845_lm_sblk, PINGPONG_4, LM_5, 0), + LM_BLK("lm_5", LM_5, 0x49000, MIXER_SDM845_MASK, + &sdm845_lm_sblk, PINGPONG_5, LM_4, 0), +}; + +static const struct dpu_dspp_cfg sm8550_dspp[] = { + DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK, + &sm8150_dspp_sblk), + DSPP_BLK("dspp_1", DSPP_1, 0x56000, DSPP_SC7180_MASK, + &sm8150_dspp_sblk), + DSPP_BLK("dspp_2", DSPP_2, 0x58000, DSPP_SC7180_MASK, + &sm8150_dspp_sblk), + DSPP_BLK("dspp_3", DSPP_3, 0x5a000, DSPP_SC7180_MASK, + &sm8150_dspp_sblk), +}; +static const struct dpu_pingpong_cfg sm8550_pp[] = { + PP_BLK_DITHER("pingpong_0", PINGPONG_0, 0x69000, MERGE_3D_0, sc7280_pp_sblk, + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), + -1), + PP_BLK_DITHER("pingpong_1", PINGPONG_1, 0x6a000, MERGE_3D_0, sc7280_pp_sblk, + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), + -1), + PP_BLK_DITHER("pingpong_2", PINGPONG_2, 0x6b000, MERGE_3D_1, sc7280_pp_sblk, + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), + -1), + PP_BLK_DITHER("pingpong_3", PINGPONG_3, 0x6c000, MERGE_3D_1, sc7280_pp_sblk, + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), + -1), + PP_BLK_DITHER("pingpong_4", PINGPONG_4, 0x6d000, MERGE_3D_2, sc7280_pp_sblk, + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30), + -1), + PP_BLK_DITHER("pingpong_5", PINGPONG_5, 0x6e000, MERGE_3D_2, sc7280_pp_sblk, + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31), + -1), + PP_BLK_DITHER("pingpong_6", PINGPONG_6, 0x66000, MERGE_3D_3, sc7280_pp_sblk, + -1, + -1), + PP_BLK_DITHER("pingpong_7", PINGPONG_7, 0x66400, MERGE_3D_3, sc7280_pp_sblk, + -1, + -1), +}; + +static const struct dpu_merge_3d_cfg sm8550_merge_3d[] = { + MERGE_3D_BLK("merge_3d_0", MERGE_3D_0, 0x4e000), + MERGE_3D_BLK("merge_3d_1", MERGE_3D_1, 0x4f000), + MERGE_3D_BLK("merge_3d_2", MERGE_3D_2, 0x50000), + MERGE_3D_BLK("merge_3d_3", MERGE_3D_3, 0x66700), +}; + +static const struct dpu_intf_cfg sm8550_intf[] = { + INTF_BLK("intf_0", INTF_0, 0x34000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 24, 25), + /* TODO TE sub-blocks for intf1 & intf2 */ + INTF_BLK("intf_1", INTF_1, 0x35000, 0x300, INTF_DSI, 0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 26, 27), + INTF_BLK("intf_2", INTF_2, 0x36000, 0x300, INTF_DSI, 1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 28, 29), + INTF_BLK("intf_3", INTF_3, 0x37000, 0x280, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 30, 31), +}; + +static const struct dpu_perf_cfg sm8550_perf_data = { + .max_bw_low = 13600000, + .max_bw_high = 18200000, + .min_core_ib = 2500000, + .min_llcc_ib = 0, + .min_dram_ib = 800000, + .min_prefill_lines = 35, + /* FIXME: lut tables */ + .danger_lut_tbl = {0x3ffff, 0x3ffff, 0x0}, + .safe_lut_tbl = {0xfe00, 0xfe00, 0xffff}, + .qos_lut_tbl = { + {.nentry = ARRAY_SIZE(sc7180_qos_linear), + .entries = sc7180_qos_linear + }, + {.nentry = ARRAY_SIZE(sc7180_qos_macrotile), + .entries = sc7180_qos_macrotile + }, + {.nentry = ARRAY_SIZE(sc7180_qos_nrt), + .entries = sc7180_qos_nrt + }, + /* TODO: macrotile-qseed is different from macrotile */ + }, + .cdp_cfg = { + {.rd_enable = 1, .wr_enable = 1}, + {.rd_enable = 1, .wr_enable = 0} + }, + .clk_inefficiency_factor = 105, + .bw_inefficiency_factor = 120, +}; + +const struct dpu_mdss_cfg dpu_sm8550_cfg = { + .caps = &sm8550_dpu_caps, + .ubwc = &sm8550_ubwc_cfg, + .mdp_count = ARRAY_SIZE(sm8550_mdp), + .mdp = sm8550_mdp, + .ctl_count = ARRAY_SIZE(sm8550_ctl), + .ctl = sm8550_ctl, + .sspp_count = ARRAY_SIZE(sm8550_sspp), + .sspp = sm8550_sspp, + .mixer_count = ARRAY_SIZE(sm8550_lm), + .mixer = sm8550_lm, + .dspp_count = ARRAY_SIZE(sm8550_dspp), + .dspp = sm8550_dspp, + .pingpong_count = ARRAY_SIZE(sm8550_pp), + .pingpong = sm8550_pp, + .merge_3d_count = ARRAY_SIZE(sm8550_merge_3d), + .merge_3d = sm8550_merge_3d, + .intf_count = ARRAY_SIZE(sm8550_intf), + .intf = sm8550_intf, + .vbif_count = ARRAY_SIZE(sdm845_vbif), + .vbif = sdm845_vbif, + .reg_dma_count = 1, + .dma_cfg = &sm8450_regdma, + .perf = &sm8550_perf_data, + .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \ + BIT(MDP_SSPP_TOP0_INTR2) | \ + BIT(MDP_SSPP_TOP0_HIST_INTR) | \ + BIT(MDP_INTF0_7xxx_INTR) | \ + BIT(MDP_INTF1_7xxx_INTR) | \ + BIT(MDP_INTF2_7xxx_INTR) | \ + BIT(MDP_INTF3_7xxx_INTR), +}; + +#endif diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c index f29a339a3705..cc66ddffe672 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c @@ -21,6 +21,7 @@ #include <drm/drm_probe_helper.h> #include <drm/drm_rect.h> #include <drm/drm_vblank.h> +#include <drm/drm_self_refresh_helper.h> #include "dpu_kms.h" #include "dpu_hw_lm.h" @@ -400,6 +401,47 @@ static void _dpu_crtc_program_lm_output_roi(struct drm_crtc *crtc) } } +static void _dpu_crtc_blend_setup_pipe(struct drm_crtc *crtc, + struct drm_plane *plane, + struct dpu_crtc_mixer *mixer, + u32 num_mixers, + enum dpu_stage stage, + struct dpu_format *format, + uint64_t modifier, + struct dpu_sw_pipe *pipe, + unsigned int stage_idx, + struct dpu_hw_stage_cfg *stage_cfg + ) +{ + uint32_t lm_idx; + enum dpu_sspp sspp_idx; + struct drm_plane_state *state; + + sspp_idx = pipe->sspp->idx; + + state = plane->state; + + trace_dpu_crtc_setup_mixer(DRMID(crtc), DRMID(plane), + state, to_dpu_plane_state(state), stage_idx, + format->base.pixel_format, + modifier); + + DRM_DEBUG_ATOMIC("crtc %d stage:%d - plane %d sspp %d fb %d multirect_idx %d\n", + crtc->base.id, + stage, + plane->base.id, + sspp_idx - SSPP_NONE, + state->fb ? state->fb->base.id : -1, + pipe->multirect_index); + + stage_cfg->stage[stage][stage_idx] = sspp_idx; + stage_cfg->multirect_index[stage][stage_idx] = pipe->multirect_index; + + /* blend config update */ + for (lm_idx = 0; lm_idx < num_mixers; lm_idx++) + mixer[lm_idx].lm_ctl->ops.update_pending_flush_sspp(mixer[lm_idx].lm_ctl, sspp_idx); +} + static void _dpu_crtc_blend_setup_mixer(struct drm_crtc *crtc, struct dpu_crtc *dpu_crtc, struct dpu_crtc_mixer *mixer, struct dpu_hw_stage_cfg *stage_cfg) @@ -412,15 +454,12 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc *crtc, struct dpu_format *format; struct dpu_hw_ctl *ctl = mixer->lm_ctl; - uint32_t stage_idx, lm_idx; - int zpos_cnt[DPU_STAGE_MAX + 1] = { 0 }; + uint32_t lm_idx; bool bg_alpha_enable = false; DECLARE_BITMAP(fetch_active, SSPP_MAX); memset(fetch_active, 0, sizeof(fetch_active)); drm_atomic_crtc_for_each_plane(plane, crtc) { - enum dpu_sspp sspp_idx; - state = plane->state; if (!state) continue; @@ -431,40 +470,30 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc *crtc, pstate = to_dpu_plane_state(state); fb = state->fb; - sspp_idx = dpu_plane_pipe(plane); - set_bit(sspp_idx, fetch_active); - - DRM_DEBUG_ATOMIC("crtc %d stage:%d - plane %d sspp %d fb %d\n", - crtc->base.id, - pstate->stage, - plane->base.id, - sspp_idx - SSPP_VIG0, - state->fb ? state->fb->base.id : -1); - format = to_dpu_format(msm_framebuffer_format(pstate->base.fb)); if (pstate->stage == DPU_STAGE_BASE && format->alpha_enable) bg_alpha_enable = true; - stage_idx = zpos_cnt[pstate->stage]++; - stage_cfg->stage[pstate->stage][stage_idx] = - sspp_idx; - stage_cfg->multirect_index[pstate->stage][stage_idx] = - pstate->multirect_index; - - trace_dpu_crtc_setup_mixer(DRMID(crtc), DRMID(plane), - state, pstate, stage_idx, - sspp_idx - SSPP_VIG0, - format->base.pixel_format, - fb ? fb->modifier : 0); + set_bit(pstate->pipe.sspp->idx, fetch_active); + _dpu_crtc_blend_setup_pipe(crtc, plane, + mixer, cstate->num_mixers, + pstate->stage, + format, fb ? fb->modifier : 0, + &pstate->pipe, 0, stage_cfg); + + if (pstate->r_pipe.sspp) { + set_bit(pstate->r_pipe.sspp->idx, fetch_active); + _dpu_crtc_blend_setup_pipe(crtc, plane, + mixer, cstate->num_mixers, + pstate->stage, + format, fb ? fb->modifier : 0, + &pstate->r_pipe, 1, stage_cfg); + } /* blend config update */ for (lm_idx = 0; lm_idx < cstate->num_mixers; lm_idx++) { - _dpu_crtc_setup_blend_cfg(mixer + lm_idx, - pstate, format); - - mixer[lm_idx].lm_ctl->ops.update_pending_flush_sspp(mixer[lm_idx].lm_ctl, - sspp_idx); + _dpu_crtc_setup_blend_cfg(mixer + lm_idx, pstate, format); if (bg_alpha_enable && !format->alpha_enable) mixer[lm_idx].mixer_op_mode = 0; @@ -767,7 +796,7 @@ static void _dpu_crtc_setup_cp_blocks(struct drm_crtc *crtc) /* stage config flush mask */ ctl->ops.update_pending_flush_dspp(ctl, - mixer[i].hw_dspp->idx); + mixer[i].hw_dspp->idx, DPU_DSPP_PCC); } } @@ -1021,6 +1050,18 @@ static void dpu_crtc_disable(struct drm_crtc *crtc, DRM_DEBUG_KMS("crtc%d\n", crtc->base.id); + /* If disable is triggered while in self refresh mode, + * reset the encoder software state so that in enable + * it won't trigger a warn while assigning crtc. + */ + if (old_crtc_state->self_refresh_active) { + drm_for_each_encoder_mask(encoder, crtc->dev, + old_crtc_state->encoder_mask) { + dpu_encoder_assign_crtc(encoder, NULL); + } + return; + } + /* Disable/save vblank irq handling */ drm_crtc_vblank_off(crtc); @@ -1032,7 +1073,14 @@ static void dpu_crtc_disable(struct drm_crtc *crtc, */ if (dpu_encoder_get_intf_mode(encoder) == INTF_MODE_VIDEO) release_bandwidth = true; - dpu_encoder_assign_crtc(encoder, NULL); + + /* + * If disable is triggered during psr active(e.g: screen dim in PSR), + * we will need encoder->crtc connection to process the device sleep & + * preserve it during psr sequence. + */ + if (!crtc->state->self_refresh_active) + dpu_encoder_assign_crtc(encoder, NULL); } /* wait for frame_event_done completion */ @@ -1080,6 +1128,9 @@ static void dpu_crtc_enable(struct drm_crtc *crtc, struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc); struct drm_encoder *encoder; bool request_bandwidth = false; + struct drm_crtc_state *old_crtc_state; + + old_crtc_state = drm_atomic_get_old_crtc_state(state, crtc); pm_runtime_get_sync(crtc->dev->dev); @@ -1102,25 +1153,23 @@ static void dpu_crtc_enable(struct drm_crtc *crtc, trace_dpu_crtc_enable(DRMID(crtc), true, dpu_crtc); dpu_crtc->enabled = true; - drm_for_each_encoder_mask(encoder, crtc->dev, crtc->state->encoder_mask) - dpu_encoder_assign_crtc(encoder, crtc); + if (!old_crtc_state->self_refresh_active) { + drm_for_each_encoder_mask(encoder, crtc->dev, crtc->state->encoder_mask) + dpu_encoder_assign_crtc(encoder, crtc); + } /* Enable/restore vblank irq handling */ drm_crtc_vblank_on(crtc); } -struct plane_state { - struct dpu_plane_state *dpu_pstate; - const struct drm_plane_state *drm_pstate; - int stage; - u32 pipe_id; -}; - static bool dpu_crtc_needs_dirtyfb(struct drm_crtc_state *cstate) { struct drm_crtc *crtc = cstate->crtc; struct drm_encoder *encoder; + if (cstate->self_refresh_active) + return true; + drm_for_each_encoder_mask (encoder, crtc->dev, cstate->encoder_mask) { if (dpu_encoder_get_intf_mode(encoder) == INTF_MODE_CMD) { return true; @@ -1137,151 +1186,46 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc, crtc); struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc); struct dpu_crtc_state *cstate = to_dpu_crtc_state(crtc_state); - struct plane_state *pstates; const struct drm_plane_state *pstate; struct drm_plane *plane; - struct drm_display_mode *mode; - int cnt = 0, rc = 0, mixer_width = 0, i, z_pos; + int rc = 0; - struct dpu_multirect_plane_states multirect_plane[DPU_STAGE_MAX * 2]; - int multirect_count = 0; - const struct drm_plane_state *pipe_staged[SSPP_MAX]; - int left_zpos_cnt = 0, right_zpos_cnt = 0; - struct drm_rect crtc_rect = { 0 }; bool needs_dirtyfb = dpu_crtc_needs_dirtyfb(crtc_state); - pstates = kzalloc(sizeof(*pstates) * DPU_STAGE_MAX * 4, GFP_KERNEL); - if (!pstates) - return -ENOMEM; - - if (!crtc_state->enable || !crtc_state->active) { + if (!crtc_state->enable || !drm_atomic_crtc_effectively_active(crtc_state)) { DRM_DEBUG_ATOMIC("crtc%d -> enable %d, active %d, skip atomic_check\n", crtc->base.id, crtc_state->enable, crtc_state->active); memset(&cstate->new_perf, 0, sizeof(cstate->new_perf)); - goto end; + return 0; } - mode = &crtc_state->adjusted_mode; DRM_DEBUG_ATOMIC("%s: check\n", dpu_crtc->name); /* force a full mode set if active state changed */ if (crtc_state->active_changed) crtc_state->mode_changed = true; - memset(pipe_staged, 0, sizeof(pipe_staged)); - - if (cstate->num_mixers) { - mixer_width = mode->hdisplay / cstate->num_mixers; - + if (cstate->num_mixers) _dpu_crtc_setup_lm_bounds(crtc, crtc_state); - } - - crtc_rect.x2 = mode->hdisplay; - crtc_rect.y2 = mode->vdisplay; - /* get plane state for all drm planes associated with crtc state */ + /* FIXME: move this to dpu_plane_atomic_check? */ drm_atomic_crtc_state_for_each_plane_state(plane, pstate, crtc_state) { struct dpu_plane_state *dpu_pstate = to_dpu_plane_state(pstate); - struct drm_rect dst, clip = crtc_rect; if (IS_ERR_OR_NULL(pstate)) { rc = PTR_ERR(pstate); DPU_ERROR("%s: failed to get plane%d state, %d\n", dpu_crtc->name, plane->base.id, rc); - goto end; + return rc; } - if (cnt >= DPU_STAGE_MAX * 4) - continue; if (!pstate->visible) continue; - pstates[cnt].dpu_pstate = dpu_pstate; - pstates[cnt].drm_pstate = pstate; - pstates[cnt].stage = pstate->normalized_zpos; - pstates[cnt].pipe_id = dpu_plane_pipe(plane); - dpu_pstate->needs_dirtyfb = needs_dirtyfb; - - if (pipe_staged[pstates[cnt].pipe_id]) { - multirect_plane[multirect_count].r0 = - pipe_staged[pstates[cnt].pipe_id]; - multirect_plane[multirect_count].r1 = pstate; - multirect_count++; - - pipe_staged[pstates[cnt].pipe_id] = NULL; - } else { - pipe_staged[pstates[cnt].pipe_id] = pstate; - } - - cnt++; - - dst = drm_plane_state_dest(pstate); - if (!drm_rect_intersect(&clip, &dst)) { - DPU_ERROR("invalid vertical/horizontal destination\n"); - DPU_ERROR("display: " DRM_RECT_FMT " plane: " - DRM_RECT_FMT "\n", DRM_RECT_ARG(&crtc_rect), - DRM_RECT_ARG(&dst)); - rc = -E2BIG; - goto end; - } - } - - for (i = 1; i < SSPP_MAX; i++) { - if (pipe_staged[i]) - dpu_plane_clear_multirect(pipe_staged[i]); - } - - z_pos = -1; - for (i = 0; i < cnt; i++) { - /* reset counts at every new blend stage */ - if (pstates[i].stage != z_pos) { - left_zpos_cnt = 0; - right_zpos_cnt = 0; - z_pos = pstates[i].stage; - } - - /* verify z_pos setting before using it */ - if (z_pos >= DPU_STAGE_MAX - DPU_STAGE_0) { - DPU_ERROR("> %d plane stages assigned\n", - DPU_STAGE_MAX - DPU_STAGE_0); - rc = -EINVAL; - goto end; - } else if (pstates[i].drm_pstate->crtc_x < mixer_width) { - if (left_zpos_cnt == 2) { - DPU_ERROR("> 2 planes @ stage %d on left\n", - z_pos); - rc = -EINVAL; - goto end; - } - left_zpos_cnt++; - - } else { - if (right_zpos_cnt == 2) { - DPU_ERROR("> 2 planes @ stage %d on right\n", - z_pos); - rc = -EINVAL; - goto end; - } - right_zpos_cnt++; - } - - pstates[i].dpu_pstate->stage = z_pos + DPU_STAGE_0; - DRM_DEBUG_ATOMIC("%s: zpos %d\n", dpu_crtc->name, z_pos); - } - - for (i = 0; i < multirect_count; i++) { - if (dpu_plane_validate_multirect_v2(&multirect_plane[i])) { - DPU_ERROR( - "multirect validation failed for planes (%d - %d)\n", - multirect_plane[i].r0->plane->base.id, - multirect_plane[i].r1->plane->base.id); - rc = -EINVAL; - goto end; - } } atomic_inc(&_dpu_crtc_get_kms(crtc)->bandwidth_ref); @@ -1290,74 +1234,10 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc, if (rc) { DPU_ERROR("crtc%d failed performance check %d\n", crtc->base.id, rc); - goto end; + return rc; } - /* validate source split: - * use pstates sorted by stage to check planes on same stage - * we assume that all pipes are in source split so its valid to compare - * without taking into account left/right mixer placement - */ - for (i = 1; i < cnt; i++) { - struct plane_state *prv_pstate, *cur_pstate; - struct drm_rect left_rect, right_rect; - int32_t left_pid, right_pid; - int32_t stage; - - prv_pstate = &pstates[i - 1]; - cur_pstate = &pstates[i]; - if (prv_pstate->stage != cur_pstate->stage) - continue; - - stage = cur_pstate->stage; - - left_pid = prv_pstate->dpu_pstate->base.plane->base.id; - left_rect = drm_plane_state_dest(prv_pstate->drm_pstate); - - right_pid = cur_pstate->dpu_pstate->base.plane->base.id; - right_rect = drm_plane_state_dest(cur_pstate->drm_pstate); - - if (right_rect.x1 < left_rect.x1) { - swap(left_pid, right_pid); - swap(left_rect, right_rect); - } - - /** - * - planes are enumerated in pipe-priority order such that - * planes with lower drm_id must be left-most in a shared - * blend-stage when using source split. - * - planes in source split must be contiguous in width - * - planes in source split must have same dest yoff and height - */ - if (right_pid < left_pid) { - DPU_ERROR( - "invalid src split cfg. priority mismatch. stage: %d left: %d right: %d\n", - stage, left_pid, right_pid); - rc = -EINVAL; - goto end; - } else if (right_rect.x1 != drm_rect_width(&left_rect)) { - DPU_ERROR("non-contiguous coordinates for src split. " - "stage: %d left: " DRM_RECT_FMT " right: " - DRM_RECT_FMT "\n", stage, - DRM_RECT_ARG(&left_rect), - DRM_RECT_ARG(&right_rect)); - rc = -EINVAL; - goto end; - } else if (left_rect.y1 != right_rect.y1 || - drm_rect_height(&left_rect) != drm_rect_height(&right_rect)) { - DPU_ERROR("source split at stage: %d. invalid " - "yoff/height: left: " DRM_RECT_FMT " right: " - DRM_RECT_FMT "\n", stage, - DRM_RECT_ARG(&left_rect), - DRM_RECT_ARG(&right_rect)); - rc = -EINVAL; - goto end; - } - } - -end: - kfree(pstates); - return rc; + return 0; } int dpu_crtc_vblank(struct drm_crtc *crtc, bool en) @@ -1474,8 +1354,16 @@ static int _dpu_debugfs_status_show(struct seq_file *s, void *data) seq_printf(s, "\tdst x:%4d dst_y:%4d dst_w:%4d dst_h:%4d\n", state->crtc_x, state->crtc_y, state->crtc_w, state->crtc_h); - seq_printf(s, "\tmultirect: mode: %d index: %d\n", - pstate->multirect_mode, pstate->multirect_index); + seq_printf(s, "\tsspp[0]:%s\n", + pstate->pipe.sspp->cap->name); + seq_printf(s, "\tmultirect[0]: mode: %d index: %d\n", + pstate->pipe.multirect_mode, pstate->pipe.multirect_index); + if (pstate->r_pipe.sspp) { + seq_printf(s, "\tsspp[1]:%s\n", + pstate->r_pipe.sspp->cap->name); + seq_printf(s, "\tmultirect[1]: mode: %d index: %d\n", + pstate->r_pipe.multirect_mode, pstate->r_pipe.multirect_index); + } seq_puts(s, "\n"); } @@ -1577,7 +1465,7 @@ struct drm_crtc *dpu_crtc_init(struct drm_device *dev, struct drm_plane *plane, { struct drm_crtc *crtc = NULL; struct dpu_crtc *dpu_crtc = NULL; - int i; + int i, ret; dpu_crtc = kzalloc(sizeof(*dpu_crtc), GFP_KERNEL); if (!dpu_crtc) @@ -1614,6 +1502,13 @@ struct drm_crtc *dpu_crtc_init(struct drm_device *dev, struct drm_plane *plane, /* initialize event handling */ spin_lock_init(&dpu_crtc->event_lock); + ret = drm_self_refresh_helper_init(crtc); + if (ret) { + DPU_ERROR("Failed to initialize %s with self-refresh helpers %d\n", + crtc->name, ret); + return ERR_PTR(ret); + } + DRM_DEBUG_KMS("%s: successfully initialized crtc\n", dpu_crtc->name); return crtc; } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c index 758261e8ac73..1dc5dbe58572 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -12,6 +12,7 @@ #include <linux/kthread.h> #include <linux/seq_file.h> +#include <drm/drm_atomic.h> #include <drm/drm_crtc.h> #include <drm/drm_file.h> #include <drm/drm_probe_helper.h> @@ -544,7 +545,8 @@ bool dpu_encoder_use_dsc_merge(struct drm_encoder *drm_enc) static struct msm_display_topology dpu_encoder_get_topology( struct dpu_encoder_virt *dpu_enc, struct dpu_kms *dpu_kms, - struct drm_display_mode *mode) + struct drm_display_mode *mode, + struct drm_crtc_state *crtc_state) { struct msm_display_topology topology = {0}; int i, intf_count = 0; @@ -562,8 +564,7 @@ static struct msm_display_topology dpu_encoder_get_topology( * 1 LM, 1 INTF * 2 LM, 1 INTF (stream merge to support high resolution interfaces) * - * Adding color blocks only to primary interface if available in - * sufficient number + * Add dspps to the reservation requirements if ctm is requested */ if (intf_count == 2) topology.num_lm = 2; @@ -572,11 +573,8 @@ static struct msm_display_topology dpu_encoder_get_topology( else topology.num_lm = (mode->hdisplay > MAX_HDISPLAY_SPLIT) ? 2 : 1; - if (dpu_enc->disp_info.intf_type == DRM_MODE_ENCODER_DSI) { - if (dpu_kms->catalog->dspp && - (dpu_kms->catalog->dspp_count >= topology.num_lm)) - topology.num_dspp = topology.num_lm; - } + if (crtc_state->ctm) + topology.num_dspp = topology.num_lm; topology.num_intf = intf_count; @@ -637,25 +635,22 @@ static int dpu_encoder_virt_atomic_check( if (ret) { DPU_ERROR_ENC(dpu_enc, "mode unsupported, phys idx %d\n", i); - break; + return ret; } } - topology = dpu_encoder_get_topology(dpu_enc, dpu_kms, adj_mode); + topology = dpu_encoder_get_topology(dpu_enc, dpu_kms, adj_mode, crtc_state); - /* Reserve dynamic resources now. */ - if (!ret) { - /* - * Release and Allocate resources on every modeset - * Dont allocate when active is false. - */ - if (drm_atomic_crtc_needs_modeset(crtc_state)) { - dpu_rm_release(global_state, drm_enc); + /* + * Release and Allocate resources on every modeset + * Dont allocate when active is false. + */ + if (drm_atomic_crtc_needs_modeset(crtc_state)) { + dpu_rm_release(global_state, drm_enc); - if (!crtc_state->active_changed || crtc_state->active) - ret = dpu_rm_reserve(&dpu_kms->rm, global_state, - drm_enc, crtc_state, topology); - } + if (!crtc_state->active_changed || crtc_state->enable) + ret = dpu_rm_reserve(&dpu_kms->rm, global_state, + drm_enc, crtc_state, topology); } trace_dpu_enc_atomic_check_flags(DRMID(drm_enc), adj_mode->flags); @@ -1171,7 +1166,8 @@ out: mutex_unlock(&dpu_enc->enc_lock); } -static void dpu_encoder_virt_enable(struct drm_encoder *drm_enc) +static void dpu_encoder_virt_atomic_enable(struct drm_encoder *drm_enc, + struct drm_atomic_state *state) { struct dpu_encoder_virt *dpu_enc = NULL; int ret = 0; @@ -1207,14 +1203,28 @@ out: mutex_unlock(&dpu_enc->enc_lock); } -static void dpu_encoder_virt_disable(struct drm_encoder *drm_enc) +static void dpu_encoder_virt_atomic_disable(struct drm_encoder *drm_enc, + struct drm_atomic_state *state) { struct dpu_encoder_virt *dpu_enc = NULL; + struct drm_crtc *crtc; + struct drm_crtc_state *old_state = NULL; int i = 0; dpu_enc = to_dpu_encoder_virt(drm_enc); DPU_DEBUG_ENC(dpu_enc, "\n"); + crtc = drm_atomic_get_old_crtc_for_encoder(state, drm_enc); + if (crtc) + old_state = drm_atomic_get_old_crtc_state(state, crtc); + + /* + * The encoder is already disabled if self refresh mode was set earlier, + * in the old_state for the corresponding crtc. + */ + if (old_state && old_state->self_refresh_active) + return; + mutex_lock(&dpu_enc->enc_lock); dpu_enc->enabled = false; @@ -2078,25 +2088,6 @@ void dpu_encoder_helper_phys_cleanup(struct dpu_encoder_phys *phys_enc) ctl->ops.clear_pending_flush(ctl); } -void dpu_encoder_prepare_commit(struct drm_encoder *drm_enc) -{ - struct dpu_encoder_virt *dpu_enc; - struct dpu_encoder_phys *phys; - int i; - - if (!drm_enc) { - DPU_ERROR("invalid encoder\n"); - return; - } - dpu_enc = to_dpu_encoder_virt(drm_enc); - - for (i = 0; i < dpu_enc->num_phys_encs; i++) { - phys = dpu_enc->phys_encs[i]; - if (phys->ops.prepare_commit) - phys->ops.prepare_commit(phys); - } -} - #ifdef CONFIG_DEBUG_FS static int _dpu_encoder_status_show(struct seq_file *s, void *data) { @@ -2388,8 +2379,8 @@ static void dpu_encoder_frame_done_timeout(struct timer_list *t) static const struct drm_encoder_helper_funcs dpu_encoder_helper_funcs = { .atomic_mode_set = dpu_encoder_virt_atomic_mode_set, - .disable = dpu_encoder_virt_disable, - .enable = dpu_encoder_virt_enable, + .atomic_disable = dpu_encoder_virt_atomic_disable, + .atomic_enable = dpu_encoder_virt_atomic_enable, .atomic_check = dpu_encoder_virt_atomic_check, }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h index 9e7236ef34e6..2c9ef8d1b877 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h @@ -147,13 +147,6 @@ int dpu_encoder_setup(struct drm_device *dev, struct drm_encoder *enc, struct msm_display_info *disp_info); /** - * dpu_encoder_prepare_commit - prepare encoder at the very beginning of an - * atomic commit, before any registers are written - * @drm_enc: Pointer to previously created drm encoder structure - */ -void dpu_encoder_prepare_commit(struct drm_encoder *drm_enc); - -/** * dpu_encoder_set_idle_timeout - set the idle timeout for video * and command mode encoders. * @drm_enc: Pointer to previously created drm encoder structure diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c index c8f4a62a9536..74470d068622 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c @@ -40,6 +40,8 @@ #define DPU_ENC_MAX_POLL_TIMEOUT_US 2000 +static void dpu_encoder_phys_cmd_enable_te(struct dpu_encoder_phys *phys_enc); + static bool dpu_encoder_phys_cmd_is_master(struct dpu_encoder_phys *phys_enc) { return (phys_enc->split_role != ENC_ROLE_SLAVE); @@ -565,6 +567,8 @@ static void dpu_encoder_phys_cmd_prepare_for_kickoff( phys_enc->hw_pp->idx - PINGPONG_0); } + dpu_encoder_phys_cmd_enable_te(phys_enc); + DPU_DEBUG_CMDENC(cmd_enc, "pp:%d pending_cnt %d\n", phys_enc->hw_pp->idx - PINGPONG_0, atomic_read(&phys_enc->pending_kickoff_cnt)); @@ -586,8 +590,7 @@ static bool dpu_encoder_phys_cmd_is_ongoing_pptx( return false; } -static void dpu_encoder_phys_cmd_prepare_commit( - struct dpu_encoder_phys *phys_enc) +static void dpu_encoder_phys_cmd_enable_te(struct dpu_encoder_phys *phys_enc) { struct dpu_encoder_phys_cmd *cmd_enc = to_dpu_encoder_phys_cmd(phys_enc); @@ -732,7 +735,6 @@ static void dpu_encoder_phys_cmd_trigger_start( static void dpu_encoder_phys_cmd_init_ops( struct dpu_encoder_phys_ops *ops) { - ops->prepare_commit = dpu_encoder_phys_cmd_prepare_commit; ops->is_master = dpu_encoder_phys_cmd_is_master; ops->atomic_mode_set = dpu_encoder_phys_cmd_atomic_mode_set; ops->enable = dpu_encoder_phys_cmd_enable; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c index 48c48106b16a..3a374292f311 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c @@ -523,6 +523,7 @@ static void dpu_encoder_phys_vid_disable(struct dpu_encoder_phys *phys_enc) { unsigned long lock_flags; int ret; + struct intf_status intf_status = {0}; if (!phys_enc->parent || !phys_enc->parent->dev) { DPU_ERROR("invalid encoder/device\n"); @@ -567,6 +568,27 @@ static void dpu_encoder_phys_vid_disable(struct dpu_encoder_phys *phys_enc) } } + if (phys_enc->hw_intf && phys_enc->hw_intf->ops.get_status) + phys_enc->hw_intf->ops.get_status(phys_enc->hw_intf, &intf_status); + + /* + * Wait for a vsync if timing en status is on after timing engine + * is disabled. + */ + if (intf_status.is_en && dpu_encoder_phys_vid_is_master(phys_enc)) { + spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags); + dpu_encoder_phys_inc_pending(phys_enc); + spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags); + ret = dpu_encoder_phys_vid_wait_for_vblank(phys_enc); + if (ret) { + atomic_set(&phys_enc->pending_kickoff_cnt, 0); + DRM_ERROR("wait disable failed: id:%u intf:%d ret:%d\n", + DRMID(phys_enc->parent), + phys_enc->hw_intf->idx - INTF_0, ret); + } + } + + dpu_encoder_helper_phys_cleanup(phys_enc); phys_enc->enable_state = DPU_ENC_DISABLED; } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c index d95540309d4d..e366ab134249 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c @@ -536,6 +536,16 @@ static const struct dpu_format dpu_format_map_ubwc[] = { true, 4, DPU_FORMAT_FLAG_DX | DPU_FORMAT_FLAG_COMPRESSED, DPU_FETCH_UBWC, 2, DPU_TILE_HEIGHT_UBWC), + /* XRGB2101010 and ARGB2101010 purposely have the same color + * ordering. The hardware only supports ARGB2101010 UBWC + * natively. + */ + INTERLEAVED_RGB_FMT_TILED(ARGB2101010, + COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, + C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4, + true, 4, DPU_FORMAT_FLAG_DX | DPU_FORMAT_FLAG_COMPRESSED, + DPU_FETCH_UBWC, 2, DPU_TILE_HEIGHT_UBWC), + PSEUDO_YUV_FMT_TILED(NV12, 0, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, C1_B_Cb, C2_R_Cr, @@ -591,6 +601,7 @@ static int _dpu_format_get_media_color_ubwc(const struct dpu_format *fmt) {DRM_FORMAT_XBGR8888, COLOR_FMT_RGBA8888_UBWC}, {DRM_FORMAT_XRGB8888, COLOR_FMT_RGBA8888_UBWC}, {DRM_FORMAT_ABGR2101010, COLOR_FMT_RGBA1010102_UBWC}, + {DRM_FORMAT_ARGB2101010, COLOR_FMT_RGBA1010102_UBWC}, {DRM_FORMAT_XRGB2101010, COLOR_FMT_RGBA1010102_UBWC}, {DRM_FORMAT_XBGR2101010, COLOR_FMT_RGBA1010102_UBWC}, {DRM_FORMAT_BGR565, COLOR_FMT_RGB565_UBWC}, @@ -918,8 +929,7 @@ int dpu_format_populate_layout( struct drm_framebuffer *fb, struct dpu_hw_fmt_layout *layout) { - uint32_t plane_addr[DPU_MAX_PLANES]; - int i, ret; + int ret; if (!fb || !layout) { DRM_ERROR("invalid arguments\n"); @@ -940,9 +950,6 @@ int dpu_format_populate_layout( if (ret) return ret; - for (i = 0; i < DPU_MAX_PLANES; ++i) - plane_addr[i] = layout->plane_addr[i]; - /* Populate the addresses given the fb */ if (DPU_FORMAT_IS_UBWC(layout->format) || DPU_FORMAT_IS_TILE(layout->format)) @@ -950,10 +957,6 @@ int dpu_format_populate_layout( else ret = _dpu_format_populate_addrs_linear(aspace, fb, layout); - /* check if anything changed */ - if (!ret && !memcmp(plane_addr, layout->plane_addr, sizeof(plane_addr))) - ret = -EAGAIN; - return ret; } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c index 497c9e1673ab..5d994bce696f 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -27,9 +27,15 @@ #define VIG_SDM845_MASK \ (VIG_MASK | BIT(DPU_SSPP_QOS_8LVL) | BIT(DPU_SSPP_SCALER_QSEED3)) +#define VIG_SDM845_MASK_SDMA \ + (VIG_SDM845_MASK | BIT(DPU_SSPP_SMART_DMA_V2)) + #define VIG_SC7180_MASK \ (VIG_MASK | BIT(DPU_SSPP_QOS_8LVL) | BIT(DPU_SSPP_SCALER_QSEED4)) +#define VIG_SC7180_MASK_SDMA \ + (VIG_SC7180_MASK | BIT(DPU_SSPP_SMART_DMA_V2)) + #define VIG_QCM2290_MASK (VIG_BASE_MASK | BIT(DPU_SSPP_QOS_8LVL)) #define DMA_MSM8998_MASK \ @@ -40,6 +46,9 @@ #define VIG_SC7280_MASK \ (VIG_SC7180_MASK | BIT(DPU_SSPP_INLINE_ROTATION)) +#define VIG_SC7280_MASK_SDMA \ + (VIG_SC7280_MASK | BIT(DPU_SSPP_SMART_DMA_V2)) + #define DMA_SDM845_MASK \ (BIT(DPU_SSPP_SRC) | BIT(DPU_SSPP_QOS) | BIT(DPU_SSPP_QOS_8LVL) |\ BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_TS_PREFILL_REC1) |\ @@ -48,6 +57,12 @@ #define DMA_CURSOR_SDM845_MASK \ (DMA_SDM845_MASK | BIT(DPU_SSPP_CURSOR)) +#define DMA_SDM845_MASK_SDMA \ + (DMA_SDM845_MASK | BIT(DPU_SSPP_SMART_DMA_V2)) + +#define DMA_CURSOR_SDM845_MASK_SDMA \ + (DMA_CURSOR_SDM845_MASK | BIT(DPU_SSPP_SMART_DMA_V2)) + #define DMA_CURSOR_MSM8998_MASK \ (DMA_MSM8998_MASK | BIT(DPU_SSPP_CURSOR)) @@ -66,7 +81,10 @@ (PINGPONG_SDM845_MASK | BIT(DPU_PINGPONG_TE2)) #define CTL_SC7280_MASK \ - (BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_FETCH_ACTIVE) | BIT(DPU_CTL_VM_CFG)) + (BIT(DPU_CTL_ACTIVE_CFG) | \ + BIT(DPU_CTL_FETCH_ACTIVE) | \ + BIT(DPU_CTL_VM_CFG) | \ + BIT(DPU_CTL_DSPP_SUB_BLOCK_FLUSH)) #define CTL_SM8550_MASK \ (CTL_SC7280_MASK | BIT(DPU_CTL_HAS_LAYER_EXT4)) @@ -79,83 +97,11 @@ #define INTF_SDM845_MASK (0) -#define INTF_SC7180_MASK BIT(DPU_INTF_INPUT_CTRL) | BIT(DPU_INTF_TE) +#define INTF_SC7180_MASK \ + (BIT(DPU_INTF_INPUT_CTRL) | BIT(DPU_INTF_TE) | BIT(DPU_INTF_STATUS_SUPPORTED)) #define INTF_SC7280_MASK INTF_SC7180_MASK | BIT(DPU_DATA_HCTL_EN) -#define IRQ_SDM845_MASK (BIT(MDP_SSPP_TOP0_INTR) | \ - BIT(MDP_SSPP_TOP0_INTR2) | \ - BIT(MDP_SSPP_TOP0_HIST_INTR) | \ - BIT(MDP_INTF0_INTR) | \ - BIT(MDP_INTF1_INTR) | \ - BIT(MDP_INTF2_INTR) | \ - BIT(MDP_INTF3_INTR) | \ - BIT(MDP_AD4_0_INTR) | \ - BIT(MDP_AD4_1_INTR)) - -#define IRQ_SC7180_MASK (BIT(MDP_SSPP_TOP0_INTR) | \ - BIT(MDP_SSPP_TOP0_INTR2) | \ - BIT(MDP_SSPP_TOP0_HIST_INTR) | \ - BIT(MDP_INTF0_INTR) | \ - BIT(MDP_INTF1_INTR)) - -#define IRQ_SC7280_MASK (BIT(MDP_SSPP_TOP0_INTR) | \ - BIT(MDP_SSPP_TOP0_INTR2) | \ - BIT(MDP_SSPP_TOP0_HIST_INTR) | \ - BIT(MDP_INTF0_7xxx_INTR) | \ - BIT(MDP_INTF1_7xxx_INTR) | \ - BIT(MDP_INTF5_7xxx_INTR)) - -#define IRQ_SM8250_MASK (BIT(MDP_SSPP_TOP0_INTR) | \ - BIT(MDP_SSPP_TOP0_INTR2) | \ - BIT(MDP_SSPP_TOP0_HIST_INTR) | \ - BIT(MDP_INTF0_INTR) | \ - BIT(MDP_INTF1_INTR) | \ - BIT(MDP_INTF2_INTR) | \ - BIT(MDP_INTF3_INTR) | \ - BIT(MDP_INTF4_INTR)) - -#define IRQ_SM8350_MASK (BIT(MDP_SSPP_TOP0_INTR) | \ - BIT(MDP_SSPP_TOP0_INTR2) | \ - BIT(MDP_SSPP_TOP0_HIST_INTR) | \ - BIT(MDP_INTF0_7xxx_INTR) | \ - BIT(MDP_INTF1_7xxx_INTR) | \ - BIT(MDP_INTF2_7xxx_INTR) | \ - BIT(MDP_INTF3_7xxx_INTR)) - -#define IRQ_SC8180X_MASK (BIT(MDP_SSPP_TOP0_INTR) | \ - BIT(MDP_SSPP_TOP0_INTR2) | \ - BIT(MDP_SSPP_TOP0_HIST_INTR) | \ - BIT(MDP_INTF0_INTR) | \ - BIT(MDP_INTF1_INTR) | \ - BIT(MDP_INTF2_INTR) | \ - BIT(MDP_INTF3_INTR) | \ - BIT(MDP_INTF4_INTR) | \ - BIT(MDP_INTF5_INTR) | \ - BIT(MDP_AD4_0_INTR) | \ - BIT(MDP_AD4_1_INTR)) - -#define IRQ_SC8280XP_MASK (BIT(MDP_SSPP_TOP0_INTR) | \ - BIT(MDP_SSPP_TOP0_INTR2) | \ - BIT(MDP_SSPP_TOP0_HIST_INTR) | \ - BIT(MDP_INTF0_7xxx_INTR) | \ - BIT(MDP_INTF1_7xxx_INTR) | \ - BIT(MDP_INTF2_7xxx_INTR) | \ - BIT(MDP_INTF3_7xxx_INTR) | \ - BIT(MDP_INTF4_7xxx_INTR) | \ - BIT(MDP_INTF5_7xxx_INTR) | \ - BIT(MDP_INTF6_7xxx_INTR) | \ - BIT(MDP_INTF7_7xxx_INTR) | \ - BIT(MDP_INTF8_7xxx_INTR)) - -#define IRQ_SM8450_MASK (BIT(MDP_SSPP_TOP0_INTR) | \ - BIT(MDP_SSPP_TOP0_INTR2) | \ - BIT(MDP_SSPP_TOP0_HIST_INTR) | \ - BIT(MDP_INTF0_7xxx_INTR) | \ - BIT(MDP_INTF1_7xxx_INTR) | \ - BIT(MDP_INTF2_7xxx_INTR) | \ - BIT(MDP_INTF3_7xxx_INTR)) - #define WB_SM8250_MASK (BIT(DPU_WB_LINE_MODE) | \ BIT(DPU_WB_UBWC) | \ BIT(DPU_WB_YUV_CONFIG) | \ @@ -188,6 +134,7 @@ static const uint32_t plane_formats[] = { DRM_FORMAT_RGBX8888, DRM_FORMAT_BGRX8888, DRM_FORMAT_XBGR8888, + DRM_FORMAT_ARGB2101010, DRM_FORMAT_XRGB2101010, DRM_FORMAT_RGB888, DRM_FORMAT_BGR888, @@ -217,6 +164,7 @@ static const uint32_t plane_formats_yuv[] = { DRM_FORMAT_RGBA8888, DRM_FORMAT_BGRX8888, DRM_FORMAT_BGRA8888, + DRM_FORMAT_ARGB2101010, DRM_FORMAT_XRGB2101010, DRM_FORMAT_XRGB8888, DRM_FORMAT_XBGR8888, @@ -295,789 +243,6 @@ static const uint32_t wb2_formats[] = { }; /************************************************************* - * DPU sub blocks config - *************************************************************/ -/* DPU top level caps */ -static const struct dpu_caps msm8998_dpu_caps = { - .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, - .max_mixer_blendstages = 0x7, - .qseed_type = DPU_SSPP_SCALER_QSEED3, - .smart_dma_rev = DPU_SSPP_SMART_DMA_V1, - .ubwc_version = DPU_HW_UBWC_VER_10, - .has_src_split = true, - .has_dim_layer = true, - .has_idle_pc = true, - .has_3d_merge = true, - .max_linewidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH, - .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, - .max_hdeci_exp = MAX_HORZ_DECIMATION, - .max_vdeci_exp = MAX_VERT_DECIMATION, -}; - -static const struct dpu_caps qcm2290_dpu_caps = { - .max_mixer_width = DEFAULT_DPU_LINE_WIDTH, - .max_mixer_blendstages = 0x4, - .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, - .has_dim_layer = true, - .has_idle_pc = true, - .max_linewidth = 2160, - .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, -}; - -static const struct dpu_caps sdm845_dpu_caps = { - .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, - .max_mixer_blendstages = 0xb, - .qseed_type = DPU_SSPP_SCALER_QSEED3, - .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, - .ubwc_version = DPU_HW_UBWC_VER_20, - .has_src_split = true, - .has_dim_layer = true, - .has_idle_pc = true, - .has_3d_merge = true, - .max_linewidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH, - .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, - .max_hdeci_exp = MAX_HORZ_DECIMATION, - .max_vdeci_exp = MAX_VERT_DECIMATION, -}; - -static const struct dpu_caps sc7180_dpu_caps = { - .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, - .max_mixer_blendstages = 0x9, - .qseed_type = DPU_SSPP_SCALER_QSEED4, - .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, - .ubwc_version = DPU_HW_UBWC_VER_20, - .has_dim_layer = true, - .has_idle_pc = true, - .max_linewidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH, - .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, -}; - -static const struct dpu_caps sm6115_dpu_caps = { - .max_mixer_width = DEFAULT_DPU_LINE_WIDTH, - .max_mixer_blendstages = 0x4, - .qseed_type = DPU_SSPP_SCALER_QSEED4, - .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, /* TODO: v2.5 */ - .ubwc_version = DPU_HW_UBWC_VER_10, - .has_dim_layer = true, - .has_idle_pc = true, - .max_linewidth = 2160, - .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, -}; - -static const struct dpu_caps sm8150_dpu_caps = { - .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, - .max_mixer_blendstages = 0xb, - .qseed_type = DPU_SSPP_SCALER_QSEED3, - .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, /* TODO: v2.5 */ - .ubwc_version = DPU_HW_UBWC_VER_30, - .has_src_split = true, - .has_dim_layer = true, - .has_idle_pc = true, - .has_3d_merge = true, - .max_linewidth = 4096, - .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, - .max_hdeci_exp = MAX_HORZ_DECIMATION, - .max_vdeci_exp = MAX_VERT_DECIMATION, -}; - -static const struct dpu_caps sc8180x_dpu_caps = { - .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, - .max_mixer_blendstages = 0xb, - .qseed_type = DPU_SSPP_SCALER_QSEED3, - .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, /* TODO: v2.5 */ - .ubwc_version = DPU_HW_UBWC_VER_30, - .has_src_split = true, - .has_dim_layer = true, - .has_idle_pc = true, - .has_3d_merge = true, - .max_linewidth = 4096, - .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, - .max_hdeci_exp = MAX_HORZ_DECIMATION, - .max_vdeci_exp = MAX_VERT_DECIMATION, -}; - -static const struct dpu_caps sc8280xp_dpu_caps = { - .max_mixer_width = 2560, - .max_mixer_blendstages = 11, - .qseed_type = DPU_SSPP_SCALER_QSEED4, - .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, /* TODO: v2.5 */ - .ubwc_version = DPU_HW_UBWC_VER_40, - .has_src_split = true, - .has_dim_layer = true, - .has_idle_pc = true, - .has_3d_merge = true, - .max_linewidth = 5120, - .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, -}; - -static const struct dpu_caps sm8250_dpu_caps = { - .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, - .max_mixer_blendstages = 0xb, - .qseed_type = DPU_SSPP_SCALER_QSEED4, - .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, /* TODO: v2.5 */ - .ubwc_version = DPU_HW_UBWC_VER_40, - .has_src_split = true, - .has_dim_layer = true, - .has_idle_pc = true, - .has_3d_merge = true, - .max_linewidth = 4096, - .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, -}; - -static const struct dpu_caps sm8350_dpu_caps = { - .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, - .max_mixer_blendstages = 0xb, - .qseed_type = DPU_SSPP_SCALER_QSEED4, - .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, /* TODO: v2.5 */ - .ubwc_version = DPU_HW_UBWC_VER_40, - .has_src_split = true, - .has_dim_layer = true, - .has_idle_pc = true, - .has_3d_merge = true, - .max_linewidth = 4096, - .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, -}; - -static const struct dpu_caps sm8450_dpu_caps = { - .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, - .max_mixer_blendstages = 0xb, - .qseed_type = DPU_SSPP_SCALER_QSEED4, - .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, /* TODO: v2.5 */ - .ubwc_version = DPU_HW_UBWC_VER_40, - .has_src_split = true, - .has_dim_layer = true, - .has_idle_pc = true, - .has_3d_merge = true, - .max_linewidth = 5120, - .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, -}; - -static const struct dpu_caps sm8550_dpu_caps = { - .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, - .max_mixer_blendstages = 0xb, - .qseed_type = DPU_SSPP_SCALER_QSEED4, - .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, /* TODO: v2.5 */ - .ubwc_version = DPU_HW_UBWC_VER_40, - .has_src_split = true, - .has_dim_layer = true, - .has_idle_pc = true, - .has_3d_merge = true, - .max_linewidth = 5120, - .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, -}; - -static const struct dpu_caps sc7280_dpu_caps = { - .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, - .max_mixer_blendstages = 0x7, - .qseed_type = DPU_SSPP_SCALER_QSEED4, - .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, - .ubwc_version = DPU_HW_UBWC_VER_30, - .has_dim_layer = true, - .has_idle_pc = true, - .max_linewidth = 2400, - .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, -}; - -static const struct dpu_mdp_cfg msm8998_mdp[] = { - { - .name = "top_0", .id = MDP_TOP, - .base = 0x0, .len = 0x458, - .features = 0, - .highest_bank_bit = 0x2, - .clk_ctrls[DPU_CLK_CTRL_VIG0] = { - .reg_off = 0x2AC, .bit_off = 0}, - .clk_ctrls[DPU_CLK_CTRL_VIG1] = { - .reg_off = 0x2B4, .bit_off = 0}, - .clk_ctrls[DPU_CLK_CTRL_VIG2] = { - .reg_off = 0x2BC, .bit_off = 0}, - .clk_ctrls[DPU_CLK_CTRL_VIG3] = { - .reg_off = 0x2C4, .bit_off = 0}, - .clk_ctrls[DPU_CLK_CTRL_DMA0] = { - .reg_off = 0x2AC, .bit_off = 8}, - .clk_ctrls[DPU_CLK_CTRL_DMA1] = { - .reg_off = 0x2B4, .bit_off = 8}, - .clk_ctrls[DPU_CLK_CTRL_DMA2] = { - .reg_off = 0x2C4, .bit_off = 8}, - .clk_ctrls[DPU_CLK_CTRL_DMA3] = { - .reg_off = 0x2C4, .bit_off = 12}, - .clk_ctrls[DPU_CLK_CTRL_CURSOR0] = { - .reg_off = 0x3A8, .bit_off = 15}, - .clk_ctrls[DPU_CLK_CTRL_CURSOR1] = { - .reg_off = 0x3B0, .bit_off = 15}, - }, -}; - -static const struct dpu_mdp_cfg sdm845_mdp[] = { - { - .name = "top_0", .id = MDP_TOP, - .base = 0x0, .len = 0x45C, - .features = BIT(DPU_MDP_AUDIO_SELECT), - .highest_bank_bit = 0x2, - .clk_ctrls[DPU_CLK_CTRL_VIG0] = { - .reg_off = 0x2AC, .bit_off = 0}, - .clk_ctrls[DPU_CLK_CTRL_VIG1] = { - .reg_off = 0x2B4, .bit_off = 0}, - .clk_ctrls[DPU_CLK_CTRL_VIG2] = { - .reg_off = 0x2BC, .bit_off = 0}, - .clk_ctrls[DPU_CLK_CTRL_VIG3] = { - .reg_off = 0x2C4, .bit_off = 0}, - .clk_ctrls[DPU_CLK_CTRL_DMA0] = { - .reg_off = 0x2AC, .bit_off = 8}, - .clk_ctrls[DPU_CLK_CTRL_DMA1] = { - .reg_off = 0x2B4, .bit_off = 8}, - .clk_ctrls[DPU_CLK_CTRL_DMA2] = { - .reg_off = 0x2BC, .bit_off = 8}, - .clk_ctrls[DPU_CLK_CTRL_DMA3] = { - .reg_off = 0x2C4, .bit_off = 8}, - }, -}; - -static const struct dpu_mdp_cfg sc7180_mdp[] = { - { - .name = "top_0", .id = MDP_TOP, - .base = 0x0, .len = 0x494, - .features = 0, - .highest_bank_bit = 0x3, - .clk_ctrls[DPU_CLK_CTRL_VIG0] = { - .reg_off = 0x2AC, .bit_off = 0}, - .clk_ctrls[DPU_CLK_CTRL_DMA0] = { - .reg_off = 0x2AC, .bit_off = 8}, - .clk_ctrls[DPU_CLK_CTRL_DMA1] = { - .reg_off = 0x2B4, .bit_off = 8}, - .clk_ctrls[DPU_CLK_CTRL_DMA2] = { - .reg_off = 0x2C4, .bit_off = 8}, - .clk_ctrls[DPU_CLK_CTRL_WB2] = { - .reg_off = 0x3B8, .bit_off = 24}, - }, -}; - -static const struct dpu_mdp_cfg sc8180x_mdp[] = { - { - .name = "top_0", .id = MDP_TOP, - .base = 0x0, .len = 0x45C, - .features = BIT(DPU_MDP_AUDIO_SELECT), - .highest_bank_bit = 0x3, - .clk_ctrls[DPU_CLK_CTRL_VIG0] = { - .reg_off = 0x2AC, .bit_off = 0}, - .clk_ctrls[DPU_CLK_CTRL_VIG1] = { - .reg_off = 0x2B4, .bit_off = 0}, - .clk_ctrls[DPU_CLK_CTRL_VIG2] = { - .reg_off = 0x2BC, .bit_off = 0}, - .clk_ctrls[DPU_CLK_CTRL_VIG3] = { - .reg_off = 0x2C4, .bit_off = 0}, - .clk_ctrls[DPU_CLK_CTRL_DMA0] = { - .reg_off = 0x2AC, .bit_off = 8}, - .clk_ctrls[DPU_CLK_CTRL_DMA1] = { - .reg_off = 0x2B4, .bit_off = 8}, - .clk_ctrls[DPU_CLK_CTRL_DMA2] = { - .reg_off = 0x2BC, .bit_off = 8}, - .clk_ctrls[DPU_CLK_CTRL_DMA3] = { - .reg_off = 0x2C4, .bit_off = 8}, - }, -}; - -static const struct dpu_mdp_cfg sm6115_mdp[] = { - { - .name = "top_0", .id = MDP_TOP, - .base = 0x0, .len = 0x494, - .features = 0, - .highest_bank_bit = 0x1, - .ubwc_swizzle = 0x7, - .clk_ctrls[DPU_CLK_CTRL_VIG0] = { - .reg_off = 0x2ac, .bit_off = 0}, - .clk_ctrls[DPU_CLK_CTRL_DMA0] = { - .reg_off = 0x2ac, .bit_off = 8}, - }, -}; - -static const struct dpu_mdp_cfg sm8250_mdp[] = { - { - .name = "top_0", .id = MDP_TOP, - .base = 0x0, .len = 0x494, - .features = 0, - .highest_bank_bit = 0x3, /* TODO: 2 for LP_DDR4 */ - .ubwc_swizzle = 0x6, - .clk_ctrls[DPU_CLK_CTRL_VIG0] = { - .reg_off = 0x2AC, .bit_off = 0}, - .clk_ctrls[DPU_CLK_CTRL_VIG1] = { - .reg_off = 0x2B4, .bit_off = 0}, - .clk_ctrls[DPU_CLK_CTRL_VIG2] = { - .reg_off = 0x2BC, .bit_off = 0}, - .clk_ctrls[DPU_CLK_CTRL_VIG3] = { - .reg_off = 0x2C4, .bit_off = 0}, - .clk_ctrls[DPU_CLK_CTRL_DMA0] = { - .reg_off = 0x2AC, .bit_off = 8}, - .clk_ctrls[DPU_CLK_CTRL_DMA1] = { - .reg_off = 0x2B4, .bit_off = 8}, - .clk_ctrls[DPU_CLK_CTRL_DMA2] = { - .reg_off = 0x2BC, .bit_off = 8}, - .clk_ctrls[DPU_CLK_CTRL_DMA3] = { - .reg_off = 0x2C4, .bit_off = 8}, - .clk_ctrls[DPU_CLK_CTRL_REG_DMA] = { - .reg_off = 0x2BC, .bit_off = 20}, - .clk_ctrls[DPU_CLK_CTRL_WB2] = { - .reg_off = 0x3B8, .bit_off = 24}, - }, -}; - -static const struct dpu_mdp_cfg sm8350_mdp[] = { - { - .name = "top_0", .id = MDP_TOP, - .base = 0x0, .len = 0x494, - .features = 0, - .highest_bank_bit = 0x3, /* TODO: 2 for LP_DDR4 */ - .clk_ctrls[DPU_CLK_CTRL_VIG0] = { - .reg_off = 0x2ac, .bit_off = 0}, - .clk_ctrls[DPU_CLK_CTRL_VIG1] = { - .reg_off = 0x2b4, .bit_off = 0}, - .clk_ctrls[DPU_CLK_CTRL_VIG2] = { - .reg_off = 0x2bc, .bit_off = 0}, - .clk_ctrls[DPU_CLK_CTRL_VIG3] = { - .reg_off = 0x2c4, .bit_off = 0}, - .clk_ctrls[DPU_CLK_CTRL_DMA0] = { - .reg_off = 0x2ac, .bit_off = 8}, - .clk_ctrls[DPU_CLK_CTRL_DMA1] = { - .reg_off = 0x2b4, .bit_off = 8}, - .clk_ctrls[DPU_CLK_CTRL_DMA2] = { - .reg_off = 0x2bc, .bit_off = 8}, - .clk_ctrls[DPU_CLK_CTRL_DMA3] = { - .reg_off = 0x2c4, .bit_off = 8}, - .clk_ctrls[DPU_CLK_CTRL_REG_DMA] = { - .reg_off = 0x2bc, .bit_off = 20}, - }, -}; - -static const struct dpu_mdp_cfg sm8450_mdp[] = { - { - .name = "top_0", .id = MDP_TOP, - .base = 0x0, .len = 0x494, - .features = BIT(DPU_MDP_PERIPH_0_REMOVED), - .highest_bank_bit = 0x3, /* TODO: 2 for LP_DDR4 */ - .ubwc_swizzle = 0x6, - .clk_ctrls[DPU_CLK_CTRL_VIG0] = { - .reg_off = 0x2AC, .bit_off = 0}, - .clk_ctrls[DPU_CLK_CTRL_VIG1] = { - .reg_off = 0x2B4, .bit_off = 0}, - .clk_ctrls[DPU_CLK_CTRL_VIG2] = { - .reg_off = 0x2BC, .bit_off = 0}, - .clk_ctrls[DPU_CLK_CTRL_VIG3] = { - .reg_off = 0x2C4, .bit_off = 0}, - .clk_ctrls[DPU_CLK_CTRL_DMA0] = { - .reg_off = 0x2AC, .bit_off = 8}, - .clk_ctrls[DPU_CLK_CTRL_DMA1] = { - .reg_off = 0x2B4, .bit_off = 8}, - .clk_ctrls[DPU_CLK_CTRL_DMA2] = { - .reg_off = 0x2BC, .bit_off = 8}, - .clk_ctrls[DPU_CLK_CTRL_DMA3] = { - .reg_off = 0x2C4, .bit_off = 8}, - .clk_ctrls[DPU_CLK_CTRL_REG_DMA] = { - .reg_off = 0x2BC, .bit_off = 20}, - }, -}; - -static const struct dpu_mdp_cfg sc7280_mdp[] = { - { - .name = "top_0", .id = MDP_TOP, - .base = 0x0, .len = 0x2014, - .highest_bank_bit = 0x1, - .ubwc_swizzle = 0x6, - .clk_ctrls[DPU_CLK_CTRL_VIG0] = { - .reg_off = 0x2AC, .bit_off = 0}, - .clk_ctrls[DPU_CLK_CTRL_DMA0] = { - .reg_off = 0x2AC, .bit_off = 8}, - .clk_ctrls[DPU_CLK_CTRL_DMA1] = { - .reg_off = 0x2B4, .bit_off = 8}, - .clk_ctrls[DPU_CLK_CTRL_DMA2] = { - .reg_off = 0x2C4, .bit_off = 8}, - }, -}; - -static const struct dpu_mdp_cfg sc8280xp_mdp[] = { - { - .name = "top_0", .id = MDP_TOP, - .base = 0x0, .len = 0x494, - .features = BIT(DPU_MDP_PERIPH_0_REMOVED), - .highest_bank_bit = 2, - .ubwc_swizzle = 6, - .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0}, - .clk_ctrls[DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0}, - .clk_ctrls[DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0}, - .clk_ctrls[DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0}, - .clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8}, - .clk_ctrls[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8}, - .clk_ctrls[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8}, - .clk_ctrls[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8}, - .clk_ctrls[DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20}, - }, -}; - -static const struct dpu_mdp_cfg sm8550_mdp[] = { - { - .name = "top_0", .id = MDP_TOP, - .base = 0, .len = 0x494, - .features = BIT(DPU_MDP_PERIPH_0_REMOVED), - .highest_bank_bit = 0x3, /* TODO: 2 for LP_DDR4 */ - .ubwc_swizzle = 0x6, - .clk_ctrls[DPU_CLK_CTRL_VIG0] = { - .reg_off = 0x4330, .bit_off = 0}, - .clk_ctrls[DPU_CLK_CTRL_VIG1] = { - .reg_off = 0x6330, .bit_off = 0}, - .clk_ctrls[DPU_CLK_CTRL_VIG2] = { - .reg_off = 0x8330, .bit_off = 0}, - .clk_ctrls[DPU_CLK_CTRL_VIG3] = { - .reg_off = 0xa330, .bit_off = 0}, - .clk_ctrls[DPU_CLK_CTRL_DMA0] = { - .reg_off = 0x24330, .bit_off = 0}, - .clk_ctrls[DPU_CLK_CTRL_DMA1] = { - .reg_off = 0x26330, .bit_off = 0}, - .clk_ctrls[DPU_CLK_CTRL_DMA2] = { - .reg_off = 0x28330, .bit_off = 0}, - .clk_ctrls[DPU_CLK_CTRL_DMA3] = { - .reg_off = 0x2a330, .bit_off = 0}, - .clk_ctrls[DPU_CLK_CTRL_DMA4] = { - .reg_off = 0x2c330, .bit_off = 0}, - .clk_ctrls[DPU_CLK_CTRL_DMA5] = { - .reg_off = 0x2e330, .bit_off = 0}, - .clk_ctrls[DPU_CLK_CTRL_REG_DMA] = { - .reg_off = 0x2bc, .bit_off = 20}, - }, -}; - -static const struct dpu_mdp_cfg qcm2290_mdp[] = { - { - .name = "top_0", .id = MDP_TOP, - .base = 0x0, .len = 0x494, - .features = 0, - .highest_bank_bit = 0x2, - .clk_ctrls[DPU_CLK_CTRL_VIG0] = { - .reg_off = 0x2AC, .bit_off = 0}, - .clk_ctrls[DPU_CLK_CTRL_DMA0] = { - .reg_off = 0x2AC, .bit_off = 8}, - }, -}; - -/************************************************************* - * CTL sub blocks config - *************************************************************/ -static const struct dpu_ctl_cfg msm8998_ctl[] = { - { - .name = "ctl_0", .id = CTL_0, - .base = 0x1000, .len = 0x94, - .features = BIT(DPU_CTL_SPLIT_DISPLAY), - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), - }, - { - .name = "ctl_1", .id = CTL_1, - .base = 0x1200, .len = 0x94, - .features = 0, - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), - }, - { - .name = "ctl_2", .id = CTL_2, - .base = 0x1400, .len = 0x94, - .features = BIT(DPU_CTL_SPLIT_DISPLAY), - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), - }, - { - .name = "ctl_3", .id = CTL_3, - .base = 0x1600, .len = 0x94, - .features = 0, - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), - }, - { - .name = "ctl_4", .id = CTL_4, - .base = 0x1800, .len = 0x94, - .features = 0, - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), - }, -}; - -static const struct dpu_ctl_cfg sdm845_ctl[] = { - { - .name = "ctl_0", .id = CTL_0, - .base = 0x1000, .len = 0xE4, - .features = BIT(DPU_CTL_SPLIT_DISPLAY), - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), - }, - { - .name = "ctl_1", .id = CTL_1, - .base = 0x1200, .len = 0xE4, - .features = BIT(DPU_CTL_SPLIT_DISPLAY), - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), - }, - { - .name = "ctl_2", .id = CTL_2, - .base = 0x1400, .len = 0xE4, - .features = 0, - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), - }, - { - .name = "ctl_3", .id = CTL_3, - .base = 0x1600, .len = 0xE4, - .features = 0, - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), - }, - { - .name = "ctl_4", .id = CTL_4, - .base = 0x1800, .len = 0xE4, - .features = 0, - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), - }, -}; - -static const struct dpu_ctl_cfg sc7180_ctl[] = { - { - .name = "ctl_0", .id = CTL_0, - .base = 0x1000, .len = 0x1dc, - .features = BIT(DPU_CTL_ACTIVE_CFG), - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), - }, - { - .name = "ctl_1", .id = CTL_1, - .base = 0x1200, .len = 0x1dc, - .features = BIT(DPU_CTL_ACTIVE_CFG), - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), - }, - { - .name = "ctl_2", .id = CTL_2, - .base = 0x1400, .len = 0x1dc, - .features = BIT(DPU_CTL_ACTIVE_CFG), - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), - }, -}; - -static const struct dpu_ctl_cfg sc8280xp_ctl[] = { - { - .name = "ctl_0", .id = CTL_0, - .base = 0x15000, .len = 0x204, - .features = CTL_SC7280_MASK, - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), - }, - { - .name = "ctl_1", .id = CTL_1, - .base = 0x16000, .len = 0x204, - .features = CTL_SC7280_MASK, - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), - }, - { - .name = "ctl_2", .id = CTL_2, - .base = 0x17000, .len = 0x204, - .features = CTL_SC7280_MASK, - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), - }, - { - .name = "ctl_3", .id = CTL_3, - .base = 0x18000, .len = 0x204, - .features = CTL_SC7280_MASK, - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), - }, - { - .name = "ctl_4", .id = CTL_4, - .base = 0x19000, .len = 0x204, - .features = CTL_SC7280_MASK, - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), - }, - { - .name = "ctl_5", .id = CTL_5, - .base = 0x1a000, .len = 0x204, - .features = CTL_SC7280_MASK, - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23), - }, -}; - -static const struct dpu_ctl_cfg sm8150_ctl[] = { - { - .name = "ctl_0", .id = CTL_0, - .base = 0x1000, .len = 0x1e0, - .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY), - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), - }, - { - .name = "ctl_1", .id = CTL_1, - .base = 0x1200, .len = 0x1e0, - .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY), - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), - }, - { - .name = "ctl_2", .id = CTL_2, - .base = 0x1400, .len = 0x1e0, - .features = BIT(DPU_CTL_ACTIVE_CFG), - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), - }, - { - .name = "ctl_3", .id = CTL_3, - .base = 0x1600, .len = 0x1e0, - .features = BIT(DPU_CTL_ACTIVE_CFG), - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), - }, - { - .name = "ctl_4", .id = CTL_4, - .base = 0x1800, .len = 0x1e0, - .features = BIT(DPU_CTL_ACTIVE_CFG), - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), - }, - { - .name = "ctl_5", .id = CTL_5, - .base = 0x1a00, .len = 0x1e0, - .features = BIT(DPU_CTL_ACTIVE_CFG), - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23), - }, -}; - -static const struct dpu_ctl_cfg sm8350_ctl[] = { - { - .name = "ctl_0", .id = CTL_0, - .base = 0x15000, .len = 0x1e8, - .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK, - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), - }, - { - .name = "ctl_1", .id = CTL_1, - .base = 0x16000, .len = 0x1e8, - .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK, - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), - }, - { - .name = "ctl_2", .id = CTL_2, - .base = 0x17000, .len = 0x1e8, - .features = CTL_SC7280_MASK, - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), - }, - { - .name = "ctl_3", .id = CTL_3, - .base = 0x18000, .len = 0x1e8, - .features = CTL_SC7280_MASK, - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), - }, - { - .name = "ctl_4", .id = CTL_4, - .base = 0x19000, .len = 0x1e8, - .features = CTL_SC7280_MASK, - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), - }, - { - .name = "ctl_5", .id = CTL_5, - .base = 0x1a000, .len = 0x1e8, - .features = CTL_SC7280_MASK, - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23), - }, -}; - -static const struct dpu_ctl_cfg sm8450_ctl[] = { - { - .name = "ctl_0", .id = CTL_0, - .base = 0x15000, .len = 0x204, - .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY) | BIT(DPU_CTL_FETCH_ACTIVE), - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), - }, - { - .name = "ctl_1", .id = CTL_1, - .base = 0x16000, .len = 0x204, - .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK, - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), - }, - { - .name = "ctl_2", .id = CTL_2, - .base = 0x17000, .len = 0x204, - .features = CTL_SC7280_MASK, - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), - }, - { - .name = "ctl_3", .id = CTL_3, - .base = 0x18000, .len = 0x204, - .features = CTL_SC7280_MASK, - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), - }, - { - .name = "ctl_4", .id = CTL_4, - .base = 0x19000, .len = 0x204, - .features = CTL_SC7280_MASK, - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), - }, - { - .name = "ctl_5", .id = CTL_5, - .base = 0x1a000, .len = 0x204, - .features = CTL_SC7280_MASK, - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23), - }, -}; - -static const struct dpu_ctl_cfg sm8550_ctl[] = { - { - .name = "ctl_0", .id = CTL_0, - .base = 0x15000, .len = 0x290, - .features = CTL_SM8550_MASK | BIT(DPU_CTL_SPLIT_DISPLAY), - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), - }, - { - .name = "ctl_1", .id = CTL_1, - .base = 0x16000, .len = 0x290, - .features = CTL_SM8550_MASK | BIT(DPU_CTL_SPLIT_DISPLAY), - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), - }, - { - .name = "ctl_2", .id = CTL_2, - .base = 0x17000, .len = 0x290, - .features = CTL_SM8550_MASK, - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), - }, - { - .name = "ctl_3", .id = CTL_3, - .base = 0x18000, .len = 0x290, - .features = CTL_SM8550_MASK, - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), - }, - { - .name = "ctl_4", .id = CTL_4, - .base = 0x19000, .len = 0x290, - .features = CTL_SM8550_MASK, - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), - }, - { - .name = "ctl_5", .id = CTL_5, - .base = 0x1a000, .len = 0x290, - .features = CTL_SM8550_MASK, - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23), - }, -}; - -static const struct dpu_ctl_cfg sc7280_ctl[] = { - { - .name = "ctl_0", .id = CTL_0, - .base = 0x15000, .len = 0x1E8, - .features = CTL_SC7280_MASK, - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), - }, - { - .name = "ctl_1", .id = CTL_1, - .base = 0x16000, .len = 0x1E8, - .features = CTL_SC7280_MASK, - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), - }, - { - .name = "ctl_2", .id = CTL_2, - .base = 0x17000, .len = 0x1E8, - .features = CTL_SC7280_MASK, - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), - }, - { - .name = "ctl_3", .id = CTL_3, - .base = 0x18000, .len = 0x1E8, - .features = CTL_SC7280_MASK, - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), - }, -}; - -static const struct dpu_ctl_cfg qcm2290_ctl[] = { - { - .name = "ctl_0", .id = CTL_0, - .base = 0x1000, .len = 0x1dc, - .features = BIT(DPU_CTL_ACTIVE_CFG), - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), - }, -}; - -/************************************************************* * SSPP sub blocks config *************************************************************/ @@ -1164,11 +329,11 @@ static const struct dpu_sspp_sub_blks sdm845_dma_sblk_1 = _DMA_SBLK("9", 2); static const struct dpu_sspp_sub_blks sdm845_dma_sblk_2 = _DMA_SBLK("10", 3); static const struct dpu_sspp_sub_blks sdm845_dma_sblk_3 = _DMA_SBLK("11", 4); -#define SSPP_BLK(_name, _id, _base, _features, \ +#define SSPP_BLK(_name, _id, _base, _len, _features, \ _sblk, _xinid, _type, _clkctrl) \ { \ .name = _name, .id = _id, \ - .base = _base, .len = 0x1c8, \ + .base = _base, .len = _len, \ .features = _features, \ .sblk = &_sblk, \ .xin_id = _xinid, \ @@ -1176,71 +341,15 @@ static const struct dpu_sspp_sub_blks sdm845_dma_sblk_3 = _DMA_SBLK("11", 4); .clk_ctrl = _clkctrl \ } -static const struct dpu_sspp_cfg msm8998_sspp[] = { - SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_MSM8998_MASK, - msm8998_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0), - SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, VIG_MSM8998_MASK, - msm8998_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1), - SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, VIG_MSM8998_MASK, - msm8998_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2), - SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, VIG_MSM8998_MASK, - msm8998_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3), - SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, DMA_MSM8998_MASK, - sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0), - SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, DMA_MSM8998_MASK, - sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1), - SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, DMA_CURSOR_MSM8998_MASK, - sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2), - SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, DMA_CURSOR_MSM8998_MASK, - sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA3), -}; - -static const struct dpu_sspp_cfg sdm845_sspp[] = { - SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_SDM845_MASK, - sdm845_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0), - SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, VIG_SDM845_MASK, - sdm845_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1), - SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, VIG_SDM845_MASK, - sdm845_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2), - SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, VIG_SDM845_MASK, - sdm845_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3), - SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, DMA_SDM845_MASK, - sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0), - SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, DMA_SDM845_MASK, - sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1), - SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, DMA_CURSOR_SDM845_MASK, - sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2), - SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, DMA_CURSOR_SDM845_MASK, - sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA3), -}; - static const struct dpu_sspp_sub_blks sc7180_vig_sblk_0 = _VIG_SBLK("0", 4, DPU_SSPP_SCALER_QSEED4); static const struct dpu_sspp_sub_blks sc7280_vig_sblk_0 = _VIG_SBLK_ROT("0", 4, DPU_SSPP_SCALER_QSEED4, &dpu_rot_sc7280_cfg_v2); -static const struct dpu_sspp_cfg sc7180_sspp[] = { - SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_SC7180_MASK, - sc7180_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0), - SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, DMA_SDM845_MASK, - sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0), - SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, DMA_CURSOR_SDM845_MASK, - sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1), - SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, DMA_CURSOR_SDM845_MASK, - sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2), -}; - static const struct dpu_sspp_sub_blks sm6115_vig_sblk_0 = _VIG_SBLK("0", 2, DPU_SSPP_SCALER_QSEED4); -static const struct dpu_sspp_cfg sm6115_sspp[] = { - SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_SC7180_MASK, - sm6115_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0), - SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, DMA_SDM845_MASK, - sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0), -}; - static const struct dpu_sspp_sub_blks sm8250_vig_sblk_0 = _VIG_SBLK("0", 5, DPU_SSPP_SCALER_QSEED4); static const struct dpu_sspp_sub_blks sm8250_vig_sblk_1 = @@ -1250,53 +359,6 @@ static const struct dpu_sspp_sub_blks sm8250_vig_sblk_2 = static const struct dpu_sspp_sub_blks sm8250_vig_sblk_3 = _VIG_SBLK("3", 8, DPU_SSPP_SCALER_QSEED4); -static const struct dpu_sspp_cfg sm8250_sspp[] = { - SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_SC7180_MASK, - sm8250_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0), - SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, VIG_SC7180_MASK, - sm8250_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1), - SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, VIG_SC7180_MASK, - sm8250_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2), - SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, VIG_SC7180_MASK, - sm8250_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3), - SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, DMA_SDM845_MASK, - sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0), - SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, DMA_SDM845_MASK, - sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1), - SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, DMA_CURSOR_SDM845_MASK, - sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2), - SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, DMA_CURSOR_SDM845_MASK, - sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA3), -}; - -static const struct dpu_sspp_sub_blks sm8450_vig_sblk_0 = - _VIG_SBLK("0", 5, DPU_SSPP_SCALER_QSEED4); -static const struct dpu_sspp_sub_blks sm8450_vig_sblk_1 = - _VIG_SBLK("1", 6, DPU_SSPP_SCALER_QSEED4); -static const struct dpu_sspp_sub_blks sm8450_vig_sblk_2 = - _VIG_SBLK("2", 7, DPU_SSPP_SCALER_QSEED4); -static const struct dpu_sspp_sub_blks sm8450_vig_sblk_3 = - _VIG_SBLK("3", 8, DPU_SSPP_SCALER_QSEED4); - -static const struct dpu_sspp_cfg sm8450_sspp[] = { - SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_SC7180_MASK, - sm8450_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0), - SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, VIG_SC7180_MASK, - sm8450_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1), - SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, VIG_SC7180_MASK, - sm8450_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2), - SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, VIG_SC7180_MASK, - sm8450_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3), - SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, DMA_SDM845_MASK, - sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0), - SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, DMA_SDM845_MASK, - sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1), - SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, DMA_CURSOR_SDM845_MASK, - sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2), - SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, DMA_CURSOR_SDM845_MASK, - sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA3), -}; - static const struct dpu_sspp_sub_blks sm8550_vig_sblk_0 = _VIG_SBLK("0", 7, DPU_SSPP_SCALER_QSEED4); static const struct dpu_sspp_sub_blks sm8550_vig_sblk_1 = @@ -1308,68 +370,6 @@ static const struct dpu_sspp_sub_blks sm8550_vig_sblk_3 = static const struct dpu_sspp_sub_blks sm8550_dma_sblk_4 = _DMA_SBLK("12", 5); static const struct dpu_sspp_sub_blks sm8550_dma_sblk_5 = _DMA_SBLK("13", 6); -static const struct dpu_sspp_cfg sm8550_sspp[] = { - SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_SC7180_MASK, - sm8550_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0), - SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, VIG_SC7180_MASK, - sm8550_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1), - SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, VIG_SC7180_MASK, - sm8550_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2), - SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, VIG_SC7180_MASK, - sm8550_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3), - SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, DMA_SDM845_MASK, - sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0), - SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, DMA_SDM845_MASK, - sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1), - SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, DMA_SDM845_MASK, - sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2), - SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, DMA_SDM845_MASK, - sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA3), - SSPP_BLK("sspp_12", SSPP_DMA4, 0x2c000, DMA_CURSOR_SDM845_MASK, - sm8550_dma_sblk_4, 14, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA4), - SSPP_BLK("sspp_13", SSPP_DMA5, 0x2e000, DMA_CURSOR_SDM845_MASK, - sm8550_dma_sblk_5, 15, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA5), -}; - -static const struct dpu_sspp_cfg sc7280_sspp[] = { - SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_SC7280_MASK, - sc7280_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0), - SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, DMA_SDM845_MASK, - sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0), - SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, DMA_CURSOR_SDM845_MASK, - sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1), - SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, DMA_CURSOR_SDM845_MASK, - sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2), -}; - -static const struct dpu_sspp_sub_blks sc8280xp_vig_sblk_0 = - _VIG_SBLK("0", 5, DPU_SSPP_SCALER_QSEED4); -static const struct dpu_sspp_sub_blks sc8280xp_vig_sblk_1 = - _VIG_SBLK("1", 6, DPU_SSPP_SCALER_QSEED4); -static const struct dpu_sspp_sub_blks sc8280xp_vig_sblk_2 = - _VIG_SBLK("2", 7, DPU_SSPP_SCALER_QSEED4); -static const struct dpu_sspp_sub_blks sc8280xp_vig_sblk_3 = - _VIG_SBLK("3", 8, DPU_SSPP_SCALER_QSEED4); - -static const struct dpu_sspp_cfg sc8280xp_sspp[] = { - SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_SC7180_MASK, - sc8280xp_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0), - SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, VIG_SC7180_MASK, - sc8280xp_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1), - SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, VIG_SC7180_MASK, - sc8280xp_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2), - SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, VIG_SC7180_MASK, - sc8280xp_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3), - SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, DMA_SDM845_MASK, - sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0), - SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, DMA_SDM845_MASK, - sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1), - SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, DMA_CURSOR_SDM845_MASK, - sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2), - SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, DMA_CURSOR_SDM845_MASK, - sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA3), -}; - #define _VIG_SBLK_NOSCALE(num, sdma_pri) \ { \ .maxdwnscale = SSPP_UNITY_SCALE, \ @@ -1386,13 +386,6 @@ static const struct dpu_sspp_cfg sc8280xp_sspp[] = { static const struct dpu_sspp_sub_blks qcm2290_vig_sblk_0 = _VIG_SBLK_NOSCALE("0", 2); static const struct dpu_sspp_sub_blks qcm2290_dma_sblk_0 = _DMA_SBLK("8", 1); -static const struct dpu_sspp_cfg qcm2290_sspp[] = { - SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_QCM2290_MASK, - qcm2290_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0), - SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, DMA_SDM845_MASK, - qcm2290_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0), -}; - /************************************************************* * MIXER sub blocks config *************************************************************/ @@ -1419,21 +412,6 @@ static const struct dpu_lm_sub_blks msm8998_lm_sblk = { }, }; -static const struct dpu_lm_cfg msm8998_lm[] = { - LM_BLK("lm_0", LM_0, 0x44000, MIXER_MSM8998_MASK, - &msm8998_lm_sblk, PINGPONG_0, LM_2, DSPP_0), - LM_BLK("lm_1", LM_1, 0x45000, MIXER_MSM8998_MASK, - &msm8998_lm_sblk, PINGPONG_1, LM_5, DSPP_1), - LM_BLK("lm_2", LM_2, 0x46000, MIXER_MSM8998_MASK, - &msm8998_lm_sblk, PINGPONG_2, LM_0, 0), - LM_BLK("lm_3", LM_3, 0x47000, MIXER_MSM8998_MASK, - &msm8998_lm_sblk, PINGPONG_MAX, 0, 0), - LM_BLK("lm_4", LM_4, 0x48000, MIXER_MSM8998_MASK, - &msm8998_lm_sblk, PINGPONG_MAX, 0, 0), - LM_BLK("lm_5", LM_5, 0x49000, MIXER_MSM8998_MASK, - &msm8998_lm_sblk, PINGPONG_3, LM_1, 0), -}; - /* SDM845 */ static const struct dpu_lm_sub_blks sdm845_lm_sblk = { @@ -1445,21 +423,6 @@ static const struct dpu_lm_sub_blks sdm845_lm_sblk = { }, }; -static const struct dpu_lm_cfg sdm845_lm[] = { - LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK, - &sdm845_lm_sblk, PINGPONG_0, LM_1, 0), - LM_BLK("lm_1", LM_1, 0x45000, MIXER_SDM845_MASK, - &sdm845_lm_sblk, PINGPONG_1, LM_0, 0), - LM_BLK("lm_2", LM_2, 0x46000, MIXER_SDM845_MASK, - &sdm845_lm_sblk, PINGPONG_2, LM_5, 0), - LM_BLK("lm_3", LM_3, 0x0, MIXER_SDM845_MASK, - &sdm845_lm_sblk, PINGPONG_MAX, 0, 0), - LM_BLK("lm_4", LM_4, 0x0, MIXER_SDM845_MASK, - &sdm845_lm_sblk, PINGPONG_MAX, 0, 0), - LM_BLK("lm_5", LM_5, 0x49000, MIXER_SDM845_MASK, - &sdm845_lm_sblk, PINGPONG_3, LM_2, 0), -}; - /* SC7180 */ static const struct dpu_lm_sub_blks sc7180_lm_sblk = { @@ -1470,50 +433,6 @@ static const struct dpu_lm_sub_blks sc7180_lm_sblk = { }, }; -static const struct dpu_lm_cfg sc7180_lm[] = { - LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK, - &sc7180_lm_sblk, PINGPONG_0, LM_1, DSPP_0), - LM_BLK("lm_1", LM_1, 0x45000, MIXER_SDM845_MASK, - &sc7180_lm_sblk, PINGPONG_1, LM_0, 0), -}; - -/* SC8280XP */ - -static const struct dpu_lm_cfg sc8280xp_lm[] = { - LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK, &sdm845_lm_sblk, PINGPONG_0, LM_1, DSPP_0), - LM_BLK("lm_1", LM_1, 0x45000, MIXER_SDM845_MASK, &sdm845_lm_sblk, PINGPONG_1, LM_0, DSPP_1), - LM_BLK("lm_2", LM_2, 0x46000, MIXER_SDM845_MASK, &sdm845_lm_sblk, PINGPONG_2, LM_3, DSPP_2), - LM_BLK("lm_3", LM_3, 0x47000, MIXER_SDM845_MASK, &sdm845_lm_sblk, PINGPONG_3, LM_2, DSPP_3), - LM_BLK("lm_4", LM_4, 0x48000, MIXER_SDM845_MASK, &sdm845_lm_sblk, PINGPONG_4, LM_5, 0), - LM_BLK("lm_5", LM_5, 0x49000, MIXER_SDM845_MASK, &sdm845_lm_sblk, PINGPONG_5, LM_4, 0), -}; - -/* SM8150 */ - -static const struct dpu_lm_cfg sm8150_lm[] = { - LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK, - &sdm845_lm_sblk, PINGPONG_0, LM_1, DSPP_0), - LM_BLK("lm_1", LM_1, 0x45000, MIXER_SDM845_MASK, - &sdm845_lm_sblk, PINGPONG_1, LM_0, DSPP_1), - LM_BLK("lm_2", LM_2, 0x46000, MIXER_SDM845_MASK, - &sdm845_lm_sblk, PINGPONG_2, LM_3, 0), - LM_BLK("lm_3", LM_3, 0x47000, MIXER_SDM845_MASK, - &sdm845_lm_sblk, PINGPONG_3, LM_2, 0), - LM_BLK("lm_4", LM_4, 0x48000, MIXER_SDM845_MASK, - &sdm845_lm_sblk, PINGPONG_4, LM_5, 0), - LM_BLK("lm_5", LM_5, 0x49000, MIXER_SDM845_MASK, - &sdm845_lm_sblk, PINGPONG_5, LM_4, 0), -}; - -static const struct dpu_lm_cfg sc7280_lm[] = { - LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK, - &sc7180_lm_sblk, PINGPONG_0, 0, DSPP_0), - LM_BLK("lm_2", LM_2, 0x46000, MIXER_SDM845_MASK, - &sc7180_lm_sblk, PINGPONG_2, LM_3, 0), - LM_BLK("lm_3", LM_3, 0x47000, MIXER_SDM845_MASK, - &sc7180_lm_sblk, PINGPONG_3, LM_2, 0), -}; - /* QCM2290 */ static const struct dpu_lm_sub_blks qcm2290_lm_sblk = { @@ -1524,11 +443,6 @@ static const struct dpu_lm_sub_blks qcm2290_lm_sblk = { }, }; -static const struct dpu_lm_cfg qcm2290_lm[] = { - LM_BLK("lm_0", LM_0, 0x44000, MIXER_QCM2290_MASK, - &qcm2290_lm_sblk, PINGPONG_0, 0, DSPP_0), -}; - /************************************************************* * DSPP sub blocks config *************************************************************/ @@ -1557,34 +471,6 @@ static const struct dpu_dspp_sub_blks sm8150_dspp_sblk = { .sblk = _sblk \ } -static const struct dpu_dspp_cfg msm8998_dspp[] = { - DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_MSM8998_MASK, - &msm8998_dspp_sblk), - DSPP_BLK("dspp_1", DSPP_1, 0x56000, DSPP_MSM8998_MASK, - &msm8998_dspp_sblk), -}; - -static const struct dpu_dspp_cfg sc7180_dspp[] = { - DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK, - &sc7180_dspp_sblk), -}; - -static const struct dpu_dspp_cfg sm8150_dspp[] = { - DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK, - &sm8150_dspp_sblk), - DSPP_BLK("dspp_1", DSPP_1, 0x56000, DSPP_SC7180_MASK, - &sm8150_dspp_sblk), - DSPP_BLK("dspp_2", DSPP_2, 0x58000, DSPP_SC7180_MASK, - &sm8150_dspp_sblk), - DSPP_BLK("dspp_3", DSPP_3, 0x5a000, DSPP_SC7180_MASK, - &sm8150_dspp_sblk), -}; - -static const struct dpu_dspp_cfg qcm2290_dspp[] = { - DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK, - &sm8150_dspp_sblk), -}; - /************************************************************* * PINGPONG sub blocks config *************************************************************/ @@ -1605,7 +491,7 @@ static const struct dpu_pingpong_sub_blks sc7280_pp_sblk = { .len = 0x20, .version = 0x20000}, }; -#define PP_BLK_DIPHER(_name, _id, _base, _merge_3d, _sblk, _done, _rdptr) \ +#define PP_BLK_DITHER(_name, _id, _base, _merge_3d, _sblk, _done, _rdptr) \ {\ .name = _name, .id = _id, \ .base = _base, .len = 0, \ @@ -1636,151 +522,6 @@ static const struct dpu_pingpong_sub_blks sc7280_pp_sblk = { .intr_rdptr = _rdptr, \ } -static const struct dpu_pingpong_cfg sdm845_pp[] = { - PP_BLK_TE("pingpong_0", PINGPONG_0, 0x70000, 0, sdm845_pp_sblk_te, - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12)), - PP_BLK_TE("pingpong_1", PINGPONG_1, 0x70800, 0, sdm845_pp_sblk_te, - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13)), - PP_BLK("pingpong_2", PINGPONG_2, 0x71000, 0, sdm845_pp_sblk, - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14)), - PP_BLK("pingpong_3", PINGPONG_3, 0x71800, 0, sdm845_pp_sblk, - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15)), -}; - -static struct dpu_pingpong_cfg sc7180_pp[] = { - PP_BLK_TE("pingpong_0", PINGPONG_0, 0x70000, 0, sdm845_pp_sblk_te, -1, -1), - PP_BLK_TE("pingpong_1", PINGPONG_1, 0x70800, 0, sdm845_pp_sblk_te, -1, -1), -}; - -static struct dpu_pingpong_cfg sc8280xp_pp[] = { - PP_BLK_TE("pingpong_0", PINGPONG_0, 0x69000, MERGE_3D_0, sdm845_pp_sblk_te, - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), -1), - PP_BLK_TE("pingpong_1", PINGPONG_1, 0x6a000, MERGE_3D_0, sdm845_pp_sblk_te, - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), -1), - PP_BLK_TE("pingpong_2", PINGPONG_2, 0x6b000, MERGE_3D_1, sdm845_pp_sblk_te, - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), -1), - PP_BLK_TE("pingpong_3", PINGPONG_3, 0x6c000, MERGE_3D_1, sdm845_pp_sblk_te, - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), -1), - PP_BLK_TE("pingpong_4", PINGPONG_4, 0x6d000, MERGE_3D_2, sdm845_pp_sblk_te, - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30), -1), - PP_BLK_TE("pingpong_5", PINGPONG_5, 0x6e000, MERGE_3D_2, sdm845_pp_sblk_te, - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31), -1), -}; - -static const struct dpu_pingpong_cfg sm8150_pp[] = { - PP_BLK_TE("pingpong_0", PINGPONG_0, 0x70000, MERGE_3D_0, sdm845_pp_sblk_te, - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12)), - PP_BLK_TE("pingpong_1", PINGPONG_1, 0x70800, MERGE_3D_0, sdm845_pp_sblk_te, - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13)), - PP_BLK("pingpong_2", PINGPONG_2, 0x71000, MERGE_3D_1, sdm845_pp_sblk, - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14)), - PP_BLK("pingpong_3", PINGPONG_3, 0x71800, MERGE_3D_1, sdm845_pp_sblk, - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15)), - PP_BLK("pingpong_4", PINGPONG_4, 0x72000, MERGE_3D_2, sdm845_pp_sblk, - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30), - -1), - PP_BLK("pingpong_5", PINGPONG_5, 0x72800, MERGE_3D_2, sdm845_pp_sblk, - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31), - -1), -}; - -static const struct dpu_pingpong_cfg sm8350_pp[] = { - PP_BLK_TE("pingpong_0", PINGPONG_0, 0x69000, MERGE_3D_0, sdm845_pp_sblk_te, - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12)), - PP_BLK_TE("pingpong_1", PINGPONG_1, 0x6a000, MERGE_3D_0, sdm845_pp_sblk_te, - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13)), - PP_BLK("pingpong_2", PINGPONG_2, 0x6b000, MERGE_3D_1, sdm845_pp_sblk, - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14)), - PP_BLK("pingpong_3", PINGPONG_3, 0x6c000, MERGE_3D_1, sdm845_pp_sblk, - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15)), - PP_BLK("pingpong_4", PINGPONG_4, 0x6d000, MERGE_3D_2, sdm845_pp_sblk, - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30), - -1), - PP_BLK("pingpong_5", PINGPONG_5, 0x6e000, MERGE_3D_2, sdm845_pp_sblk, - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31), - -1), -}; - -static const struct dpu_pingpong_cfg sc7280_pp[] = { - PP_BLK("pingpong_0", PINGPONG_0, 0x69000, 0, sc7280_pp_sblk, -1, -1), - PP_BLK("pingpong_1", PINGPONG_1, 0x6a000, 0, sc7280_pp_sblk, -1, -1), - PP_BLK("pingpong_2", PINGPONG_2, 0x6b000, 0, sc7280_pp_sblk, -1, -1), - PP_BLK("pingpong_3", PINGPONG_3, 0x6c000, 0, sc7280_pp_sblk, -1, -1), -}; - -static struct dpu_pingpong_cfg qcm2290_pp[] = { - PP_BLK("pingpong_0", PINGPONG_0, 0x70000, 0, sdm845_pp_sblk, - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12)), -}; - -/* FIXME: interrupts */ -static const struct dpu_pingpong_cfg sm8450_pp[] = { - PP_BLK_TE("pingpong_0", PINGPONG_0, 0x69000, MERGE_3D_0, sdm845_pp_sblk_te, - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12)), - PP_BLK_TE("pingpong_1", PINGPONG_1, 0x6a000, MERGE_3D_0, sdm845_pp_sblk_te, - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13)), - PP_BLK("pingpong_2", PINGPONG_2, 0x6b000, MERGE_3D_1, sdm845_pp_sblk, - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14)), - PP_BLK("pingpong_3", PINGPONG_3, 0x6c000, MERGE_3D_1, sdm845_pp_sblk, - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15)), - PP_BLK("pingpong_4", PINGPONG_4, 0x6d000, MERGE_3D_2, sdm845_pp_sblk, - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30), - -1), - PP_BLK("pingpong_5", PINGPONG_5, 0x6e000, MERGE_3D_2, sdm845_pp_sblk, - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31), - -1), - PP_BLK("pingpong_6", PINGPONG_6, 0x65800, MERGE_3D_3, sdm845_pp_sblk, - -1, - -1), - PP_BLK("pingpong_7", PINGPONG_7, 0x65c00, MERGE_3D_3, sdm845_pp_sblk, - -1, - -1), -}; - -static const struct dpu_pingpong_cfg sm8550_pp[] = { - PP_BLK_DIPHER("pingpong_0", PINGPONG_0, 0x69000, MERGE_3D_0, sc7280_pp_sblk, - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), - -1), - PP_BLK_DIPHER("pingpong_1", PINGPONG_1, 0x6a000, MERGE_3D_0, sc7280_pp_sblk, - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), - -1), - PP_BLK_DIPHER("pingpong_2", PINGPONG_2, 0x6b000, MERGE_3D_1, sc7280_pp_sblk, - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), - -1), - PP_BLK_DIPHER("pingpong_3", PINGPONG_3, 0x6c000, MERGE_3D_1, sc7280_pp_sblk, - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), - -1), - PP_BLK_DIPHER("pingpong_4", PINGPONG_4, 0x6d000, MERGE_3D_2, sc7280_pp_sblk, - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30), - -1), - PP_BLK_DIPHER("pingpong_5", PINGPONG_5, 0x6e000, MERGE_3D_2, sc7280_pp_sblk, - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31), - -1), - PP_BLK_DIPHER("pingpong_6", PINGPONG_6, 0x66000, MERGE_3D_3, sc7280_pp_sblk, - -1, - -1), - PP_BLK_DIPHER("pingpong_7", PINGPONG_7, 0x66400, MERGE_3D_3, sc7280_pp_sblk, - -1, - -1), -}; - /************************************************************* * MERGE_3D sub blocks config *************************************************************/ @@ -1792,32 +533,6 @@ static const struct dpu_pingpong_cfg sm8550_pp[] = { .sblk = NULL \ } -static const struct dpu_merge_3d_cfg sm8150_merge_3d[] = { - MERGE_3D_BLK("merge_3d_0", MERGE_3D_0, 0x83000), - MERGE_3D_BLK("merge_3d_1", MERGE_3D_1, 0x83100), - MERGE_3D_BLK("merge_3d_2", MERGE_3D_2, 0x83200), -}; - -static const struct dpu_merge_3d_cfg sm8350_merge_3d[] = { - MERGE_3D_BLK("merge_3d_0", MERGE_3D_0, 0x4e000), - MERGE_3D_BLK("merge_3d_1", MERGE_3D_1, 0x4f000), - MERGE_3D_BLK("merge_3d_2", MERGE_3D_2, 0x50000), -}; - -static const struct dpu_merge_3d_cfg sm8450_merge_3d[] = { - MERGE_3D_BLK("merge_3d_0", MERGE_3D_0, 0x4e000), - MERGE_3D_BLK("merge_3d_1", MERGE_3D_1, 0x4f000), - MERGE_3D_BLK("merge_3d_2", MERGE_3D_2, 0x50000), - MERGE_3D_BLK("merge_3d_3", MERGE_3D_3, 0x65f00), -}; - -static const struct dpu_merge_3d_cfg sm8550_merge_3d[] = { - MERGE_3D_BLK("merge_3d_0", MERGE_3D_0, 0x4e000), - MERGE_3D_BLK("merge_3d_1", MERGE_3D_1, 0x4f000), - MERGE_3D_BLK("merge_3d_2", MERGE_3D_2, 0x50000), - MERGE_3D_BLK("merge_3d_3", MERGE_3D_3, 0x66700), -}; - /************************************************************* * DSC sub blocks config *************************************************************/ @@ -1828,27 +543,13 @@ static const struct dpu_merge_3d_cfg sm8550_merge_3d[] = { .features = _features, \ } -static struct dpu_dsc_cfg sdm845_dsc[] = { - DSC_BLK("dsc_0", DSC_0, 0x80000, 0), - DSC_BLK("dsc_1", DSC_1, 0x80400, 0), - DSC_BLK("dsc_2", DSC_2, 0x80800, 0), - DSC_BLK("dsc_3", DSC_3, 0x80c00, 0), -}; - -static struct dpu_dsc_cfg sm8150_dsc[] = { - DSC_BLK("dsc_0", DSC_0, 0x80000, BIT(DPU_DSC_OUTPUT_CTRL)), - DSC_BLK("dsc_1", DSC_1, 0x80400, BIT(DPU_DSC_OUTPUT_CTRL)), - DSC_BLK("dsc_2", DSC_2, 0x80800, BIT(DPU_DSC_OUTPUT_CTRL)), - DSC_BLK("dsc_3", DSC_3, 0x80c00, BIT(DPU_DSC_OUTPUT_CTRL)), -}; - /************************************************************* * INTF sub blocks config *************************************************************/ -#define INTF_BLK(_name, _id, _base, _type, _ctrl_id, _progfetch, _features, _reg, _underrun_bit, _vsync_bit) \ +#define INTF_BLK(_name, _id, _base, _len, _type, _ctrl_id, _progfetch, _features, _reg, _underrun_bit, _vsync_bit) \ {\ .name = _name, .id = _id, \ - .base = _base, .len = 0x280, \ + .base = _base, .len = _len, \ .features = _features, \ .type = _type, \ .controller_id = _ctrl_id, \ @@ -1857,88 +558,6 @@ static struct dpu_dsc_cfg sm8150_dsc[] = { .intr_vsync = DPU_IRQ_IDX(_reg, _vsync_bit), \ } -static const struct dpu_intf_cfg msm8998_intf[] = { - INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, 0, 25, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 24, 25), - INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, 25, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 26, 27), - INTF_BLK("intf_2", INTF_2, 0x6B000, INTF_DSI, 1, 25, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 28, 29), - INTF_BLK("intf_3", INTF_3, 0x6B800, INTF_HDMI, 0, 25, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 30, 31), -}; - -static const struct dpu_intf_cfg sdm845_intf[] = { - INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, 0, 24, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 24, 25), - INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, 24, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 26, 27), - INTF_BLK("intf_2", INTF_2, 0x6B000, INTF_DSI, 1, 24, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 28, 29), - INTF_BLK("intf_3", INTF_3, 0x6B800, INTF_DP, 1, 24, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 30, 31), -}; - -static const struct dpu_intf_cfg sc7180_intf[] = { - INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 24, 25), - INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 26, 27), -}; - -static const struct dpu_intf_cfg sm8150_intf[] = { - INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 24, 25), - INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 26, 27), - INTF_BLK("intf_2", INTF_2, 0x6B000, INTF_DSI, 1, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 28, 29), - INTF_BLK("intf_3", INTF_3, 0x6B800, INTF_DP, 1, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 30, 31), -}; - -static const struct dpu_intf_cfg sc7280_intf[] = { - INTF_BLK("intf_0", INTF_0, 0x34000, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 24, 25), - INTF_BLK("intf_1", INTF_1, 0x35000, INTF_DSI, 0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 26, 27), - INTF_BLK("intf_5", INTF_5, 0x39000, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 22, 23), -}; - -static const struct dpu_intf_cfg sm8350_intf[] = { - INTF_BLK("intf_0", INTF_0, 0x34000, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 24, 25), - INTF_BLK("intf_1", INTF_1, 0x35000, INTF_DSI, 0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 26, 27), - INTF_BLK("intf_2", INTF_2, 0x36000, INTF_DSI, 1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 28, 29), - INTF_BLK("intf_3", INTF_3, 0x37000, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 30, 31), -}; - -static const struct dpu_intf_cfg sc8180x_intf[] = { - INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 24, 25), - INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 26, 27), - INTF_BLK("intf_2", INTF_2, 0x6B000, INTF_DSI, 1, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 28, 29), - /* INTF_3 is for MST, wired to INTF_DP 0 and 1, use dummy index until this is supported */ - INTF_BLK("intf_3", INTF_3, 0x6B800, INTF_DP, 999, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 30, 31), - INTF_BLK("intf_4", INTF_4, 0x6C000, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 20, 21), - INTF_BLK("intf_5", INTF_5, 0x6C800, INTF_DP, MSM_DP_CONTROLLER_2, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 22, 23), -}; - -/* TODO: INTF 3, 8 and 7 are used for MST, marked as INTF_NONE for now */ -static const struct dpu_intf_cfg sc8280xp_intf[] = { - INTF_BLK("intf_0", INTF_0, 0x34000, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 24, 25), - INTF_BLK("intf_1", INTF_1, 0x35000, INTF_DSI, 0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 26, 27), - INTF_BLK("intf_2", INTF_2, 0x36000, INTF_DSI, 1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 28, 29), - INTF_BLK("intf_3", INTF_3, 0x37000, INTF_NONE, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 30, 31), - INTF_BLK("intf_4", INTF_4, 0x38000, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 20, 21), - INTF_BLK("intf_5", INTF_5, 0x39000, INTF_DP, MSM_DP_CONTROLLER_3, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 22, 23), - INTF_BLK("intf_6", INTF_6, 0x3a000, INTF_DP, MSM_DP_CONTROLLER_2, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 16, 17), - INTF_BLK("intf_7", INTF_7, 0x3b000, INTF_NONE, MSM_DP_CONTROLLER_2, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 18, 19), - INTF_BLK("intf_8", INTF_8, 0x3c000, INTF_NONE, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 12, 13), -}; - -static const struct dpu_intf_cfg qcm2290_intf[] = { - INTF_BLK("intf_0", INTF_0, 0x00000, INTF_NONE, 0, 0, 0, 0, 0, 0), - INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 26, 27), -}; - -static const struct dpu_intf_cfg sm8450_intf[] = { - INTF_BLK("intf_0", INTF_0, 0x34000, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 24, 25), - INTF_BLK("intf_1", INTF_1, 0x35000, INTF_DSI, 0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 26, 27), - INTF_BLK("intf_2", INTF_2, 0x36000, INTF_DSI, 1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 28, 29), - INTF_BLK("intf_3", INTF_3, 0x37000, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 30, 31), -}; - -static const struct dpu_intf_cfg sm8550_intf[] = { - INTF_BLK("intf_0", INTF_0, 0x34000, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 24, 25), - /* TODO TE sub-blocks for intf1 & intf2 */ - INTF_BLK("intf_1", INTF_1, 0x35000, INTF_DSI, 0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 26, 27), - INTF_BLK("intf_2", INTF_2, 0x36000, INTF_DSI, 1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 28, 29), - INTF_BLK("intf_3", INTF_3, 0x37000, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 30, 31), -}; - /************************************************************* * Writeback blocks config *************************************************************/ @@ -1957,11 +576,6 @@ static const struct dpu_intf_cfg sm8550_intf[] = { .intr_wb_done = DPU_IRQ_IDX(_reg, _wb_done_bit) \ } -static const struct dpu_wb_cfg sm8250_wb[] = { - WB_BLK("wb_2", WB_2, 0x65000, WB_SM8250_MASK, DPU_CLK_CTRL_WB2, 6, - VBIF_RT, MDP_SSPP_TOP0_INTR, 4096, 4), -}; - /************************************************************* * VBIF sub blocks config *************************************************************/ @@ -1973,12 +587,12 @@ static const u32 sdm845_nrt_pri_lvl[] = {3, 3, 3, 3, 3, 3, 3, 3}; static const struct dpu_vbif_dynamic_ot_cfg msm8998_ot_rdwr_cfg[] = { { - .pps = 1088 * 1920 * 30, + .pps = 1920 * 1080 * 30, .ot_limit = 2, }, { - .pps = 1088 * 1920 * 60, - .ot_limit = 6, + .pps = 1920 * 1080 * 60, + .ot_limit = 4, }, { .pps = 3840 * 2160 * 30, @@ -2091,10 +705,7 @@ static const struct dpu_qos_lut_entry msm8998_qos_linear[] = { {.fl = 10, .lut = 0x1555b}, {.fl = 11, .lut = 0x5555b}, {.fl = 12, .lut = 0x15555b}, - {.fl = 13, .lut = 0x55555b}, - {.fl = 14, .lut = 0}, - {.fl = 1, .lut = 0x1b}, - {.fl = 0, .lut = 0} + {.fl = 0, .lut = 0x55555b} }; static const struct dpu_qos_lut_entry sdm845_qos_linear[] = { @@ -2116,9 +727,7 @@ static const struct dpu_qos_lut_entry msm8998_qos_macrotile[] = { {.fl = 10, .lut = 0x1aaff}, {.fl = 11, .lut = 0x5aaff}, {.fl = 12, .lut = 0x15aaff}, - {.fl = 13, .lut = 0x55aaff}, - {.fl = 1, .lut = 0x1aaff}, - {.fl = 0, .lut = 0}, + {.fl = 0, .lut = 0x55aaff}, }; static const struct dpu_qos_lut_entry sc7180_qos_linear[] = { @@ -2166,715 +775,26 @@ static const struct dpu_qos_lut_entry sc7180_qos_nrt[] = { {.fl = 0, .lut = 0x0}, }; -static const struct dpu_perf_cfg msm8998_perf_data = { - .max_bw_low = 6700000, - .max_bw_high = 6700000, - .min_core_ib = 2400000, - .min_llcc_ib = 800000, - .min_dram_ib = 800000, - .undersized_prefill_lines = 2, - .xtra_prefill_lines = 2, - .dest_scale_prefill_lines = 3, - .macrotile_prefill_lines = 4, - .yuv_nv12_prefill_lines = 8, - .linear_prefill_lines = 1, - .downscaling_prefill_lines = 1, - .amortizable_threshold = 25, - .min_prefill_lines = 25, - .danger_lut_tbl = {0xf, 0xffff, 0x0}, - .safe_lut_tbl = {0xfffc, 0xff00, 0xffff}, - .qos_lut_tbl = { - {.nentry = ARRAY_SIZE(msm8998_qos_linear), - .entries = msm8998_qos_linear - }, - {.nentry = ARRAY_SIZE(msm8998_qos_macrotile), - .entries = msm8998_qos_macrotile - }, - {.nentry = ARRAY_SIZE(msm8998_qos_nrt), - .entries = msm8998_qos_nrt - }, - }, - .cdp_cfg = { - {.rd_enable = 1, .wr_enable = 1}, - {.rd_enable = 1, .wr_enable = 0} - }, - .clk_inefficiency_factor = 200, - .bw_inefficiency_factor = 120, -}; - -static const struct dpu_perf_cfg sdm845_perf_data = { - .max_bw_low = 6800000, - .max_bw_high = 6800000, - .min_core_ib = 2400000, - .min_llcc_ib = 800000, - .min_dram_ib = 800000, - .undersized_prefill_lines = 2, - .xtra_prefill_lines = 2, - .dest_scale_prefill_lines = 3, - .macrotile_prefill_lines = 4, - .yuv_nv12_prefill_lines = 8, - .linear_prefill_lines = 1, - .downscaling_prefill_lines = 1, - .amortizable_threshold = 25, - .min_prefill_lines = 24, - .danger_lut_tbl = {0xf, 0xffff, 0x0}, - .safe_lut_tbl = {0xfff0, 0xf000, 0xffff}, - .qos_lut_tbl = { - {.nentry = ARRAY_SIZE(sdm845_qos_linear), - .entries = sdm845_qos_linear - }, - {.nentry = ARRAY_SIZE(sdm845_qos_macrotile), - .entries = sdm845_qos_macrotile - }, - {.nentry = ARRAY_SIZE(sdm845_qos_nrt), - .entries = sdm845_qos_nrt - }, - }, - .cdp_cfg = { - {.rd_enable = 1, .wr_enable = 1}, - {.rd_enable = 1, .wr_enable = 0} - }, - .clk_inefficiency_factor = 105, - .bw_inefficiency_factor = 120, -}; - -static const struct dpu_perf_cfg sc7180_perf_data = { - .max_bw_low = 6800000, - .max_bw_high = 6800000, - .min_core_ib = 2400000, - .min_llcc_ib = 800000, - .min_dram_ib = 1600000, - .min_prefill_lines = 24, - .danger_lut_tbl = {0xff, 0xffff, 0x0}, - .safe_lut_tbl = {0xfff0, 0xff00, 0xffff}, - .qos_lut_tbl = { - {.nentry = ARRAY_SIZE(sc7180_qos_linear), - .entries = sc7180_qos_linear - }, - {.nentry = ARRAY_SIZE(sc7180_qos_macrotile), - .entries = sc7180_qos_macrotile - }, - {.nentry = ARRAY_SIZE(sc7180_qos_nrt), - .entries = sc7180_qos_nrt - }, - }, - .cdp_cfg = { - {.rd_enable = 1, .wr_enable = 1}, - {.rd_enable = 1, .wr_enable = 0} - }, - .clk_inefficiency_factor = 105, - .bw_inefficiency_factor = 120, -}; - -static const struct dpu_perf_cfg sm6115_perf_data = { - .max_bw_low = 3100000, - .max_bw_high = 4000000, - .min_core_ib = 2400000, - .min_llcc_ib = 800000, - .min_dram_ib = 800000, - .min_prefill_lines = 24, - .danger_lut_tbl = {0xff, 0xffff, 0x0}, - .safe_lut_tbl = {0xfff0, 0xff00, 0xffff}, - .qos_lut_tbl = { - {.nentry = ARRAY_SIZE(sc7180_qos_linear), - .entries = sc7180_qos_linear - }, - {.nentry = ARRAY_SIZE(sc7180_qos_macrotile), - .entries = sc7180_qos_macrotile - }, - {.nentry = ARRAY_SIZE(sc7180_qos_nrt), - .entries = sc7180_qos_nrt - }, - /* TODO: macrotile-qseed is different from macrotile */ - }, - .cdp_cfg = { - {.rd_enable = 1, .wr_enable = 1}, - {.rd_enable = 1, .wr_enable = 0} - }, - .clk_inefficiency_factor = 105, - .bw_inefficiency_factor = 120, -}; - -static const struct dpu_perf_cfg sm8150_perf_data = { - .max_bw_low = 12800000, - .max_bw_high = 12800000, - .min_core_ib = 2400000, - .min_llcc_ib = 800000, - .min_dram_ib = 800000, - .min_prefill_lines = 24, - .danger_lut_tbl = {0xf, 0xffff, 0x0}, - .safe_lut_tbl = {0xfff8, 0xf000, 0xffff}, - .qos_lut_tbl = { - {.nentry = ARRAY_SIZE(sm8150_qos_linear), - .entries = sm8150_qos_linear - }, - {.nentry = ARRAY_SIZE(sc7180_qos_macrotile), - .entries = sc7180_qos_macrotile - }, - {.nentry = ARRAY_SIZE(sc7180_qos_nrt), - .entries = sc7180_qos_nrt - }, - /* TODO: macrotile-qseed is different from macrotile */ - }, - .cdp_cfg = { - {.rd_enable = 1, .wr_enable = 1}, - {.rd_enable = 1, .wr_enable = 0} - }, - .clk_inefficiency_factor = 105, - .bw_inefficiency_factor = 120, -}; - -static const struct dpu_perf_cfg sc8180x_perf_data = { - .max_bw_low = 9600000, - .max_bw_high = 9600000, - .min_core_ib = 2400000, - .min_llcc_ib = 800000, - .min_dram_ib = 800000, - .danger_lut_tbl = {0xf, 0xffff, 0x0}, - .qos_lut_tbl = { - {.nentry = ARRAY_SIZE(sc7180_qos_linear), - .entries = sc7180_qos_linear - }, - {.nentry = ARRAY_SIZE(sc7180_qos_macrotile), - .entries = sc7180_qos_macrotile - }, - {.nentry = ARRAY_SIZE(sc7180_qos_nrt), - .entries = sc7180_qos_nrt - }, - /* TODO: macrotile-qseed is different from macrotile */ - }, - .cdp_cfg = { - {.rd_enable = 1, .wr_enable = 1}, - {.rd_enable = 1, .wr_enable = 0} - }, - .clk_inefficiency_factor = 105, - .bw_inefficiency_factor = 120, -}; - -static const struct dpu_perf_cfg sc8280xp_perf_data = { - .max_bw_low = 13600000, - .max_bw_high = 18200000, - .min_core_ib = 2500000, - .min_llcc_ib = 0, - .min_dram_ib = 800000, - .danger_lut_tbl = {0xf, 0xffff, 0x0}, - .qos_lut_tbl = { - {.nentry = ARRAY_SIZE(sc8180x_qos_linear), - .entries = sc8180x_qos_linear - }, - {.nentry = ARRAY_SIZE(sc8180x_qos_macrotile), - .entries = sc8180x_qos_macrotile - }, - {.nentry = ARRAY_SIZE(sc7180_qos_nrt), - .entries = sc7180_qos_nrt - }, - /* TODO: macrotile-qseed is different from macrotile */ - }, - .cdp_cfg = { - {.rd_enable = 1, .wr_enable = 1}, - {.rd_enable = 1, .wr_enable = 0} - }, - .clk_inefficiency_factor = 105, - .bw_inefficiency_factor = 120, -}; - -static const struct dpu_perf_cfg sm8250_perf_data = { - .max_bw_low = 13700000, - .max_bw_high = 16600000, - .min_core_ib = 4800000, - .min_llcc_ib = 0, - .min_dram_ib = 800000, - .min_prefill_lines = 35, - .danger_lut_tbl = {0xf, 0xffff, 0x0}, - .safe_lut_tbl = {0xfff0, 0xff00, 0xffff}, - .qos_lut_tbl = { - {.nentry = ARRAY_SIZE(sc7180_qos_linear), - .entries = sc7180_qos_linear - }, - {.nentry = ARRAY_SIZE(sc7180_qos_macrotile), - .entries = sc7180_qos_macrotile - }, - {.nentry = ARRAY_SIZE(sc7180_qos_nrt), - .entries = sc7180_qos_nrt - }, - /* TODO: macrotile-qseed is different from macrotile */ - }, - .cdp_cfg = { - {.rd_enable = 1, .wr_enable = 1}, - {.rd_enable = 1, .wr_enable = 0} - }, - .clk_inefficiency_factor = 105, - .bw_inefficiency_factor = 120, -}; - -static const struct dpu_perf_cfg sm8450_perf_data = { - .max_bw_low = 13600000, - .max_bw_high = 18200000, - .min_core_ib = 2500000, - .min_llcc_ib = 0, - .min_dram_ib = 800000, - .min_prefill_lines = 35, - /* FIXME: lut tables */ - .danger_lut_tbl = {0x3ffff, 0x3ffff, 0x0}, - .safe_lut_tbl = {0xfe00, 0xfe00, 0xffff}, - .qos_lut_tbl = { - {.nentry = ARRAY_SIZE(sc7180_qos_linear), - .entries = sc7180_qos_linear - }, - {.nentry = ARRAY_SIZE(sc7180_qos_macrotile), - .entries = sc7180_qos_macrotile - }, - {.nentry = ARRAY_SIZE(sc7180_qos_nrt), - .entries = sc7180_qos_nrt - }, - /* TODO: macrotile-qseed is different from macrotile */ - }, - .cdp_cfg = { - {.rd_enable = 1, .wr_enable = 1}, - {.rd_enable = 1, .wr_enable = 0} - }, - .clk_inefficiency_factor = 105, - .bw_inefficiency_factor = 120, -}; - -static const struct dpu_perf_cfg sc7280_perf_data = { - .max_bw_low = 4700000, - .max_bw_high = 8800000, - .min_core_ib = 2500000, - .min_llcc_ib = 0, - .min_dram_ib = 1600000, - .min_prefill_lines = 24, - .danger_lut_tbl = {0xffff, 0xffff, 0x0}, - .safe_lut_tbl = {0xff00, 0xff00, 0xffff}, - .qos_lut_tbl = { - {.nentry = ARRAY_SIZE(sc7180_qos_macrotile), - .entries = sc7180_qos_macrotile - }, - {.nentry = ARRAY_SIZE(sc7180_qos_macrotile), - .entries = sc7180_qos_macrotile - }, - {.nentry = ARRAY_SIZE(sc7180_qos_nrt), - .entries = sc7180_qos_nrt - }, - }, - .cdp_cfg = { - {.rd_enable = 1, .wr_enable = 1}, - {.rd_enable = 1, .wr_enable = 0} - }, - .clk_inefficiency_factor = 105, - .bw_inefficiency_factor = 120, -}; - -static const struct dpu_perf_cfg sm8350_perf_data = { - .max_bw_low = 11800000, - .max_bw_high = 15500000, - .min_core_ib = 2500000, - .min_llcc_ib = 0, - .min_dram_ib = 800000, - .min_prefill_lines = 40, - /* FIXME: lut tables */ - .danger_lut_tbl = {0x3ffff, 0x3ffff, 0x0}, - .safe_lut_tbl = {0xfe00, 0xfe00, 0xffff}, - .qos_lut_tbl = { - {.nentry = ARRAY_SIZE(sc7180_qos_linear), - .entries = sc7180_qos_linear - }, - {.nentry = ARRAY_SIZE(sc7180_qos_macrotile), - .entries = sc7180_qos_macrotile - }, - {.nentry = ARRAY_SIZE(sc7180_qos_nrt), - .entries = sc7180_qos_nrt - }, - /* TODO: macrotile-qseed is different from macrotile */ - }, - .cdp_cfg = { - {.rd_enable = 1, .wr_enable = 1}, - {.rd_enable = 1, .wr_enable = 0} - }, - .clk_inefficiency_factor = 105, - .bw_inefficiency_factor = 120, -}; - -static const struct dpu_perf_cfg qcm2290_perf_data = { - .max_bw_low = 2700000, - .max_bw_high = 2700000, - .min_core_ib = 1300000, - .min_llcc_ib = 0, - .min_dram_ib = 1600000, - .min_prefill_lines = 24, - .danger_lut_tbl = {0xff, 0x0, 0x0}, - .safe_lut_tbl = {0xfff0, 0x0, 0x0}, - .qos_lut_tbl = { - {.nentry = ARRAY_SIZE(qcm2290_qos_linear), - .entries = qcm2290_qos_linear - }, - }, - .cdp_cfg = { - {.rd_enable = 1, .wr_enable = 1}, - {.rd_enable = 1, .wr_enable = 0} - }, - .clk_inefficiency_factor = 105, - .bw_inefficiency_factor = 120, -}; /************************************************************* * Hardware catalog *************************************************************/ -static const struct dpu_mdss_cfg msm8998_dpu_cfg = { - .caps = &msm8998_dpu_caps, - .mdp_count = ARRAY_SIZE(msm8998_mdp), - .mdp = msm8998_mdp, - .ctl_count = ARRAY_SIZE(msm8998_ctl), - .ctl = msm8998_ctl, - .sspp_count = ARRAY_SIZE(msm8998_sspp), - .sspp = msm8998_sspp, - .mixer_count = ARRAY_SIZE(msm8998_lm), - .mixer = msm8998_lm, - .dspp_count = ARRAY_SIZE(msm8998_dspp), - .dspp = msm8998_dspp, - .pingpong_count = ARRAY_SIZE(sdm845_pp), - .pingpong = sdm845_pp, - .intf_count = ARRAY_SIZE(msm8998_intf), - .intf = msm8998_intf, - .vbif_count = ARRAY_SIZE(msm8998_vbif), - .vbif = msm8998_vbif, - .reg_dma_count = 0, - .perf = &msm8998_perf_data, - .mdss_irqs = IRQ_SM8250_MASK, -}; +#include "catalog/dpu_3_0_msm8998.h" -static const struct dpu_mdss_cfg sdm845_dpu_cfg = { - .caps = &sdm845_dpu_caps, - .mdp_count = ARRAY_SIZE(sdm845_mdp), - .mdp = sdm845_mdp, - .ctl_count = ARRAY_SIZE(sdm845_ctl), - .ctl = sdm845_ctl, - .sspp_count = ARRAY_SIZE(sdm845_sspp), - .sspp = sdm845_sspp, - .mixer_count = ARRAY_SIZE(sdm845_lm), - .mixer = sdm845_lm, - .pingpong_count = ARRAY_SIZE(sdm845_pp), - .pingpong = sdm845_pp, - .dsc_count = ARRAY_SIZE(sdm845_dsc), - .dsc = sdm845_dsc, - .intf_count = ARRAY_SIZE(sdm845_intf), - .intf = sdm845_intf, - .vbif_count = ARRAY_SIZE(sdm845_vbif), - .vbif = sdm845_vbif, - .reg_dma_count = 1, - .dma_cfg = &sdm845_regdma, - .perf = &sdm845_perf_data, - .mdss_irqs = IRQ_SDM845_MASK, -}; +#include "catalog/dpu_4_0_sdm845.h" -static const struct dpu_mdss_cfg sc7180_dpu_cfg = { - .caps = &sc7180_dpu_caps, - .mdp_count = ARRAY_SIZE(sc7180_mdp), - .mdp = sc7180_mdp, - .ctl_count = ARRAY_SIZE(sc7180_ctl), - .ctl = sc7180_ctl, - .sspp_count = ARRAY_SIZE(sc7180_sspp), - .sspp = sc7180_sspp, - .mixer_count = ARRAY_SIZE(sc7180_lm), - .mixer = sc7180_lm, - .dspp_count = ARRAY_SIZE(sc7180_dspp), - .dspp = sc7180_dspp, - .pingpong_count = ARRAY_SIZE(sc7180_pp), - .pingpong = sc7180_pp, - .intf_count = ARRAY_SIZE(sc7180_intf), - .intf = sc7180_intf, - .wb_count = ARRAY_SIZE(sm8250_wb), - .wb = sm8250_wb, - .vbif_count = ARRAY_SIZE(sdm845_vbif), - .vbif = sdm845_vbif, - .reg_dma_count = 1, - .dma_cfg = &sdm845_regdma, - .perf = &sc7180_perf_data, - .mdss_irqs = IRQ_SC7180_MASK, -}; - -static const struct dpu_mdss_cfg sm6115_dpu_cfg = { - .caps = &sm6115_dpu_caps, - .mdp_count = ARRAY_SIZE(sm6115_mdp), - .mdp = sm6115_mdp, - .ctl_count = ARRAY_SIZE(qcm2290_ctl), - .ctl = qcm2290_ctl, - .sspp_count = ARRAY_SIZE(sm6115_sspp), - .sspp = sm6115_sspp, - .mixer_count = ARRAY_SIZE(qcm2290_lm), - .mixer = qcm2290_lm, - .dspp_count = ARRAY_SIZE(qcm2290_dspp), - .dspp = qcm2290_dspp, - .pingpong_count = ARRAY_SIZE(qcm2290_pp), - .pingpong = qcm2290_pp, - .intf_count = ARRAY_SIZE(qcm2290_intf), - .intf = qcm2290_intf, - .vbif_count = ARRAY_SIZE(sdm845_vbif), - .vbif = sdm845_vbif, - .perf = &sm6115_perf_data, - .mdss_irqs = IRQ_SC7180_MASK, -}; - -static const struct dpu_mdss_cfg sm8150_dpu_cfg = { - .caps = &sm8150_dpu_caps, - .mdp_count = ARRAY_SIZE(sdm845_mdp), - .mdp = sdm845_mdp, - .ctl_count = ARRAY_SIZE(sm8150_ctl), - .ctl = sm8150_ctl, - .sspp_count = ARRAY_SIZE(sdm845_sspp), - .sspp = sdm845_sspp, - .mixer_count = ARRAY_SIZE(sm8150_lm), - .mixer = sm8150_lm, - .dspp_count = ARRAY_SIZE(sm8150_dspp), - .dspp = sm8150_dspp, - .dsc_count = ARRAY_SIZE(sm8150_dsc), - .dsc = sm8150_dsc, - .pingpong_count = ARRAY_SIZE(sm8150_pp), - .pingpong = sm8150_pp, - .merge_3d_count = ARRAY_SIZE(sm8150_merge_3d), - .merge_3d = sm8150_merge_3d, - .intf_count = ARRAY_SIZE(sm8150_intf), - .intf = sm8150_intf, - .vbif_count = ARRAY_SIZE(sdm845_vbif), - .vbif = sdm845_vbif, - .reg_dma_count = 1, - .dma_cfg = &sm8150_regdma, - .perf = &sm8150_perf_data, - .mdss_irqs = IRQ_SDM845_MASK, -}; - -static const struct dpu_mdss_cfg sc8180x_dpu_cfg = { - .caps = &sc8180x_dpu_caps, - .mdp_count = ARRAY_SIZE(sc8180x_mdp), - .mdp = sc8180x_mdp, - .ctl_count = ARRAY_SIZE(sm8150_ctl), - .ctl = sm8150_ctl, - .sspp_count = ARRAY_SIZE(sdm845_sspp), - .sspp = sdm845_sspp, - .mixer_count = ARRAY_SIZE(sm8150_lm), - .mixer = sm8150_lm, - .pingpong_count = ARRAY_SIZE(sm8150_pp), - .pingpong = sm8150_pp, - .merge_3d_count = ARRAY_SIZE(sm8150_merge_3d), - .merge_3d = sm8150_merge_3d, - .intf_count = ARRAY_SIZE(sc8180x_intf), - .intf = sc8180x_intf, - .vbif_count = ARRAY_SIZE(sdm845_vbif), - .vbif = sdm845_vbif, - .reg_dma_count = 1, - .dma_cfg = &sm8150_regdma, - .perf = &sc8180x_perf_data, - .mdss_irqs = IRQ_SC8180X_MASK, -}; - -static const struct dpu_mdss_cfg sc8280xp_dpu_cfg = { - .caps = &sc8280xp_dpu_caps, - .mdp_count = ARRAY_SIZE(sc8280xp_mdp), - .mdp = sc8280xp_mdp, - .ctl_count = ARRAY_SIZE(sc8280xp_ctl), - .ctl = sc8280xp_ctl, - .sspp_count = ARRAY_SIZE(sc8280xp_sspp), - .sspp = sc8280xp_sspp, - .mixer_count = ARRAY_SIZE(sc8280xp_lm), - .mixer = sc8280xp_lm, - .dspp_count = ARRAY_SIZE(sm8150_dspp), - .dspp = sm8150_dspp, - .pingpong_count = ARRAY_SIZE(sc8280xp_pp), - .pingpong = sc8280xp_pp, - .merge_3d_count = ARRAY_SIZE(sm8350_merge_3d), - .merge_3d = sm8350_merge_3d, - .intf_count = ARRAY_SIZE(sc8280xp_intf), - .intf = sc8280xp_intf, - .vbif_count = ARRAY_SIZE(sdm845_vbif), - .vbif = sdm845_vbif, - .reg_dma_count = 1, - .dma_cfg = &sc8280xp_regdma, - .perf = &sc8280xp_perf_data, - .mdss_irqs = IRQ_SC8280XP_MASK, -}; - -static const struct dpu_mdss_cfg sm8250_dpu_cfg = { - .caps = &sm8250_dpu_caps, - .mdp_count = ARRAY_SIZE(sm8250_mdp), - .mdp = sm8250_mdp, - .ctl_count = ARRAY_SIZE(sm8150_ctl), - .ctl = sm8150_ctl, - .sspp_count = ARRAY_SIZE(sm8250_sspp), - .sspp = sm8250_sspp, - .mixer_count = ARRAY_SIZE(sm8150_lm), - .mixer = sm8150_lm, - .dspp_count = ARRAY_SIZE(sm8150_dspp), - .dspp = sm8150_dspp, - .dsc_count = ARRAY_SIZE(sm8150_dsc), - .dsc = sm8150_dsc, - .pingpong_count = ARRAY_SIZE(sm8150_pp), - .pingpong = sm8150_pp, - .merge_3d_count = ARRAY_SIZE(sm8150_merge_3d), - .merge_3d = sm8150_merge_3d, - .intf_count = ARRAY_SIZE(sm8150_intf), - .intf = sm8150_intf, - .vbif_count = ARRAY_SIZE(sdm845_vbif), - .vbif = sdm845_vbif, - .wb_count = ARRAY_SIZE(sm8250_wb), - .wb = sm8250_wb, - .reg_dma_count = 1, - .dma_cfg = &sm8250_regdma, - .perf = &sm8250_perf_data, - .mdss_irqs = IRQ_SM8250_MASK, -}; - -static const struct dpu_mdss_cfg sm8350_dpu_cfg = { - .caps = &sm8350_dpu_caps, - .mdp_count = ARRAY_SIZE(sm8350_mdp), - .mdp = sm8350_mdp, - .ctl_count = ARRAY_SIZE(sm8350_ctl), - .ctl = sm8350_ctl, - .sspp_count = ARRAY_SIZE(sm8250_sspp), - .sspp = sm8250_sspp, - .mixer_count = ARRAY_SIZE(sm8150_lm), - .mixer = sm8150_lm, - .dspp_count = ARRAY_SIZE(sm8150_dspp), - .dspp = sm8150_dspp, - .pingpong_count = ARRAY_SIZE(sm8350_pp), - .pingpong = sm8350_pp, - .merge_3d_count = ARRAY_SIZE(sm8350_merge_3d), - .merge_3d = sm8350_merge_3d, - .intf_count = ARRAY_SIZE(sm8350_intf), - .intf = sm8350_intf, - .vbif_count = ARRAY_SIZE(sdm845_vbif), - .vbif = sdm845_vbif, - .reg_dma_count = 1, - .dma_cfg = &sm8350_regdma, - .perf = &sm8350_perf_data, - .mdss_irqs = IRQ_SM8350_MASK, -}; +#include "catalog/dpu_5_0_sm8150.h" +#include "catalog/dpu_5_1_sc8180x.h" -static const struct dpu_mdss_cfg sm8450_dpu_cfg = { - .caps = &sm8450_dpu_caps, - .mdp_count = ARRAY_SIZE(sm8450_mdp), - .mdp = sm8450_mdp, - .ctl_count = ARRAY_SIZE(sm8450_ctl), - .ctl = sm8450_ctl, - .sspp_count = ARRAY_SIZE(sm8450_sspp), - .sspp = sm8450_sspp, - .mixer_count = ARRAY_SIZE(sm8150_lm), - .mixer = sm8150_lm, - .dspp_count = ARRAY_SIZE(sm8150_dspp), - .dspp = sm8150_dspp, - .pingpong_count = ARRAY_SIZE(sm8450_pp), - .pingpong = sm8450_pp, - .merge_3d_count = ARRAY_SIZE(sm8450_merge_3d), - .merge_3d = sm8450_merge_3d, - .intf_count = ARRAY_SIZE(sm8450_intf), - .intf = sm8450_intf, - .vbif_count = ARRAY_SIZE(sdm845_vbif), - .vbif = sdm845_vbif, - .reg_dma_count = 1, - .dma_cfg = &sm8450_regdma, - .perf = &sm8450_perf_data, - .mdss_irqs = IRQ_SM8450_MASK, -}; - -static const struct dpu_mdss_cfg sm8550_dpu_cfg = { - .caps = &sm8550_dpu_caps, - .mdp_count = ARRAY_SIZE(sm8550_mdp), - .mdp = sm8550_mdp, - .ctl_count = ARRAY_SIZE(sm8550_ctl), - .ctl = sm8550_ctl, - .sspp_count = ARRAY_SIZE(sm8550_sspp), - .sspp = sm8550_sspp, - .mixer_count = ARRAY_SIZE(sm8150_lm), - .mixer = sm8150_lm, - .dspp_count = ARRAY_SIZE(sm8150_dspp), - .dspp = sm8150_dspp, - .pingpong_count = ARRAY_SIZE(sm8550_pp), - .pingpong = sm8550_pp, - .merge_3d_count = ARRAY_SIZE(sm8550_merge_3d), - .merge_3d = sm8550_merge_3d, - .intf_count = ARRAY_SIZE(sm8550_intf), - .intf = sm8550_intf, - .vbif_count = ARRAY_SIZE(sdm845_vbif), - .vbif = sdm845_vbif, - .reg_dma_count = 1, - .dma_cfg = &sm8450_regdma, - .perf = &sm8450_perf_data, - .mdss_irqs = IRQ_SM8450_MASK, -}; - -static const struct dpu_mdss_cfg sc7280_dpu_cfg = { - .caps = &sc7280_dpu_caps, - .mdp_count = ARRAY_SIZE(sc7280_mdp), - .mdp = sc7280_mdp, - .ctl_count = ARRAY_SIZE(sc7280_ctl), - .ctl = sc7280_ctl, - .sspp_count = ARRAY_SIZE(sc7280_sspp), - .sspp = sc7280_sspp, - .dspp_count = ARRAY_SIZE(sc7180_dspp), - .dspp = sc7180_dspp, - .mixer_count = ARRAY_SIZE(sc7280_lm), - .mixer = sc7280_lm, - .pingpong_count = ARRAY_SIZE(sc7280_pp), - .pingpong = sc7280_pp, - .intf_count = ARRAY_SIZE(sc7280_intf), - .intf = sc7280_intf, - .vbif_count = ARRAY_SIZE(sdm845_vbif), - .vbif = sdm845_vbif, - .perf = &sc7280_perf_data, - .mdss_irqs = IRQ_SC7280_MASK, -}; - -static const struct dpu_mdss_cfg qcm2290_dpu_cfg = { - .caps = &qcm2290_dpu_caps, - .mdp_count = ARRAY_SIZE(qcm2290_mdp), - .mdp = qcm2290_mdp, - .ctl_count = ARRAY_SIZE(qcm2290_ctl), - .ctl = qcm2290_ctl, - .sspp_count = ARRAY_SIZE(qcm2290_sspp), - .sspp = qcm2290_sspp, - .mixer_count = ARRAY_SIZE(qcm2290_lm), - .mixer = qcm2290_lm, - .dspp_count = ARRAY_SIZE(qcm2290_dspp), - .dspp = qcm2290_dspp, - .pingpong_count = ARRAY_SIZE(qcm2290_pp), - .pingpong = qcm2290_pp, - .intf_count = ARRAY_SIZE(qcm2290_intf), - .intf = qcm2290_intf, - .vbif_count = ARRAY_SIZE(sdm845_vbif), - .vbif = sdm845_vbif, - .perf = &qcm2290_perf_data, - .mdss_irqs = IRQ_SC7180_MASK, -}; - -static const struct dpu_mdss_hw_cfg_handler cfg_handler[] = { - { .hw_rev = DPU_HW_VER_300, .dpu_cfg = &msm8998_dpu_cfg}, - { .hw_rev = DPU_HW_VER_301, .dpu_cfg = &msm8998_dpu_cfg}, - { .hw_rev = DPU_HW_VER_400, .dpu_cfg = &sdm845_dpu_cfg}, - { .hw_rev = DPU_HW_VER_401, .dpu_cfg = &sdm845_dpu_cfg}, - { .hw_rev = DPU_HW_VER_500, .dpu_cfg = &sm8150_dpu_cfg}, - { .hw_rev = DPU_HW_VER_501, .dpu_cfg = &sm8150_dpu_cfg}, - { .hw_rev = DPU_HW_VER_510, .dpu_cfg = &sc8180x_dpu_cfg}, - { .hw_rev = DPU_HW_VER_600, .dpu_cfg = &sm8250_dpu_cfg}, - { .hw_rev = DPU_HW_VER_620, .dpu_cfg = &sc7180_dpu_cfg}, - { .hw_rev = DPU_HW_VER_630, .dpu_cfg = &sm6115_dpu_cfg}, - { .hw_rev = DPU_HW_VER_650, .dpu_cfg = &qcm2290_dpu_cfg}, - { .hw_rev = DPU_HW_VER_700, .dpu_cfg = &sm8350_dpu_cfg}, - { .hw_rev = DPU_HW_VER_720, .dpu_cfg = &sc7280_dpu_cfg}, - { .hw_rev = DPU_HW_VER_800, .dpu_cfg = &sc8280xp_dpu_cfg}, - { .hw_rev = DPU_HW_VER_810, .dpu_cfg = &sm8450_dpu_cfg}, - { .hw_rev = DPU_HW_VER_900, .dpu_cfg = &sm8550_dpu_cfg}, -}; - -const struct dpu_mdss_cfg *dpu_hw_catalog_init(u32 hw_rev) -{ - int i; - - for (i = 0; i < ARRAY_SIZE(cfg_handler); i++) { - if (cfg_handler[i].hw_rev == hw_rev) - return cfg_handler[i].dpu_cfg; - } +#include "catalog/dpu_6_0_sm8250.h" +#include "catalog/dpu_6_2_sc7180.h" +#include "catalog/dpu_6_3_sm6115.h" +#include "catalog/dpu_6_5_qcm2290.h" - DPU_ERROR("unsupported chipset id:%X\n", hw_rev); +#include "catalog/dpu_7_0_sm8350.h" +#include "catalog/dpu_7_2_sc7280.h" - return ERR_PTR(-ENODEV); -} +#include "catalog/dpu_8_0_sc8280xp.h" +#include "catalog/dpu_8_1_sm8450.h" +#include "catalog/dpu_9_0_sm8550.h" diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h index e6590302b3bf..71584cd56fd7 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -19,47 +19,6 @@ */ #define MAX_BLOCKS 12 -#define DPU_HW_VER(MAJOR, MINOR, STEP) (((MAJOR & 0xF) << 28) |\ - ((MINOR & 0xFFF) << 16) |\ - (STEP & 0xFFFF)) - -#define DPU_HW_MAJOR(rev) ((rev) >> 28) -#define DPU_HW_MINOR(rev) (((rev) >> 16) & 0xFFF) -#define DPU_HW_STEP(rev) ((rev) & 0xFFFF) -#define DPU_HW_MAJOR_MINOR(rev) ((rev) >> 16) - -#define IS_DPU_MAJOR_MINOR_SAME(rev1, rev2) \ - (DPU_HW_MAJOR_MINOR((rev1)) == DPU_HW_MAJOR_MINOR((rev2))) - -#define DPU_HW_VER_170 DPU_HW_VER(1, 7, 0) /* 8996 v1.0 */ -#define DPU_HW_VER_171 DPU_HW_VER(1, 7, 1) /* 8996 v2.0 */ -#define DPU_HW_VER_172 DPU_HW_VER(1, 7, 2) /* 8996 v3.0 */ -#define DPU_HW_VER_300 DPU_HW_VER(3, 0, 0) /* 8998 v1.0 */ -#define DPU_HW_VER_301 DPU_HW_VER(3, 0, 1) /* 8998 v1.1 */ -#define DPU_HW_VER_400 DPU_HW_VER(4, 0, 0) /* sdm845 v1.0 */ -#define DPU_HW_VER_401 DPU_HW_VER(4, 0, 1) /* sdm845 v2.0 */ -#define DPU_HW_VER_410 DPU_HW_VER(4, 1, 0) /* sdm670 v1.0 */ -#define DPU_HW_VER_500 DPU_HW_VER(5, 0, 0) /* sm8150 v1.0 */ -#define DPU_HW_VER_501 DPU_HW_VER(5, 0, 1) /* sm8150 v2.0 */ -#define DPU_HW_VER_510 DPU_HW_VER(5, 1, 1) /* sc8180 */ -#define DPU_HW_VER_600 DPU_HW_VER(6, 0, 0) /* sm8250 */ -#define DPU_HW_VER_620 DPU_HW_VER(6, 2, 0) /* sc7180 v1.0 */ -#define DPU_HW_VER_630 DPU_HW_VER(6, 3, 0) /* sm6115|sm4250 */ -#define DPU_HW_VER_650 DPU_HW_VER(6, 5, 0) /* qcm2290|sm4125 */ -#define DPU_HW_VER_700 DPU_HW_VER(7, 0, 0) /* sm8350 */ -#define DPU_HW_VER_720 DPU_HW_VER(7, 2, 0) /* sc7280 */ -#define DPU_HW_VER_800 DPU_HW_VER(8, 0, 0) /* sc8280xp */ -#define DPU_HW_VER_810 DPU_HW_VER(8, 1, 0) /* sm8450 */ -#define DPU_HW_VER_900 DPU_HW_VER(9, 0, 0) /* sm8550 */ - -#define IS_MSM8996_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_170) -#define IS_MSM8998_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_300) -#define IS_SDM845_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_400) -#define IS_SDM670_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_410) -#define IS_SDM855_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_500) -#define IS_SC7180_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_620) -#define IS_SC7280_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_720) - #define DPU_HW_BLK_NAME_LEN 16 #define MAX_IMG_WIDTH 0x3fff @@ -169,10 +128,12 @@ enum { * DSPP sub-blocks * @DPU_DSPP_PCC Panel color correction block * @DPU_DSPP_GC Gamma correction block + * @DPU_DSPP_IGC Inverse gamma correction block */ enum { DPU_DSPP_PCC = 0x1, DPU_DSPP_GC, + DPU_DSPP_IGC, DPU_DSPP_MAX }; @@ -200,6 +161,7 @@ enum { * @DPU_CTL_FETCH_ACTIVE: Active CTL for fetch HW (SSPPs) * @DPU_CTL_VM_CFG: CTL config to support multiple VMs * @DPU_CTL_HAS_LAYER_EXT4: CTL has the CTL_LAYER_EXT4 register + * @DPU_CTL_DSPP_BLOCK_FLUSH: CTL config to support dspp sub-block flush * @DPU_CTL_MAX */ enum { @@ -208,22 +170,25 @@ enum { DPU_CTL_FETCH_ACTIVE, DPU_CTL_VM_CFG, DPU_CTL_HAS_LAYER_EXT4, + DPU_CTL_DSPP_SUB_BLOCK_FLUSH, DPU_CTL_MAX }; /** * INTF sub-blocks - * @DPU_INTF_INPUT_CTRL Supports the setting of pp block from which - * pixel data arrives to this INTF - * @DPU_INTF_TE INTF block has TE configuration support - * @DPU_DATA_HCTL_EN Allows data to be transferred at different rate - than video timing + * @DPU_INTF_INPUT_CTRL Supports the setting of pp block from which + * pixel data arrives to this INTF + * @DPU_INTF_TE INTF block has TE configuration support + * @DPU_DATA_HCTL_EN Allows data to be transferred at different rate + * than video timing + * @DPU_INTF_STATUS_SUPPORTED INTF block has INTF_STATUS register * @DPU_INTF_MAX */ enum { DPU_INTF_INPUT_CTRL = 0x1, DPU_INTF_TE, DPU_DATA_HCTL_EN, + DPU_INTF_STATUS_SUPPORTED, DPU_INTF_MAX }; @@ -393,8 +358,6 @@ struct dpu_rotation_cfg { * @max_mixer_blendstages max layer mixer blend stages or * supported z order * @qseed_type qseed2 or qseed3 support. - * @smart_dma_rev Supported version of SmartDMA feature. - * @ubwc_version UBWC feature version (0x0 for not supported) * @has_src_split source split feature status * @has_dim_layer dim layer feature status * @has_idle_pc indicate if idle power collapse feature is supported @@ -408,8 +371,6 @@ struct dpu_caps { u32 max_mixer_width; u32 max_mixer_blendstages; u32 qseed_type; - u32 smart_dma_rev; - u32 ubwc_version; bool has_src_split; bool has_dim_layer; bool has_idle_pc; @@ -538,15 +499,24 @@ struct dpu_clk_ctrl_reg { * @id: index identifying this block * @base: register base offset to mdss * @features bit mask identifying sub-blocks/features - * @highest_bank_bit: UBWC parameter - * @ubwc_swizzle: ubwc default swizzle setting * @clk_ctrls clock control register definition */ struct dpu_mdp_cfg { DPU_HW_BLK_INFO; + struct dpu_clk_ctrl_reg clk_ctrls[DPU_CLK_CTRL_MAX]; +}; + +/** + * struct dpu_ubwc_cfg - UBWC and memory configuration + * + * @ubwc_version UBWC feature version (0x0 for not supported) + * @highest_bank_bit: UBWC parameter + * @ubwc_swizzle: ubwc default swizzle setting + */ +struct dpu_ubwc_cfg { + u32 ubwc_version; u32 highest_bank_bit; u32 ubwc_swizzle; - struct dpu_clk_ctrl_reg clk_ctrls[DPU_CLK_CTRL_MAX]; }; /* struct dpu_ctl_cfg : MDP CTL instance info @@ -848,6 +818,8 @@ struct dpu_perf_cfg { struct dpu_mdss_cfg { const struct dpu_caps *caps; + const struct dpu_ubwc_cfg *ubwc; + u32 mdp_count; const struct dpu_mdp_cfg *mdp; @@ -867,7 +839,7 @@ struct dpu_mdss_cfg { const struct dpu_merge_3d_cfg *merge_3d; u32 dsc_count; - struct dpu_dsc_cfg *dsc; + const struct dpu_dsc_cfg *dsc; u32 intf_count; const struct dpu_intf_cfg *intf; @@ -896,18 +868,18 @@ struct dpu_mdss_cfg { unsigned long mdss_irqs; }; -struct dpu_mdss_hw_cfg_handler { - u32 hw_rev; - const struct dpu_mdss_cfg *dpu_cfg; -}; - -/** - * dpu_hw_catalog_init - dpu hardware catalog init API retrieves - * hardcoded target specific catalog information in config structure - * @hw_rev: caller needs provide the hardware revision. - * - * Return: dpu config structure - */ -const struct dpu_mdss_cfg *dpu_hw_catalog_init(u32 hw_rev); +extern const struct dpu_mdss_cfg dpu_msm8998_cfg; +extern const struct dpu_mdss_cfg dpu_sdm845_cfg; +extern const struct dpu_mdss_cfg dpu_sm8150_cfg; +extern const struct dpu_mdss_cfg dpu_sc8180x_cfg; +extern const struct dpu_mdss_cfg dpu_sm8250_cfg; +extern const struct dpu_mdss_cfg dpu_sc7180_cfg; +extern const struct dpu_mdss_cfg dpu_sm6115_cfg; +extern const struct dpu_mdss_cfg dpu_qcm2290_cfg; +extern const struct dpu_mdss_cfg dpu_sm8350_cfg; +extern const struct dpu_mdss_cfg dpu_sc7280_cfg; +extern const struct dpu_mdss_cfg dpu_sc8280xp_cfg; +extern const struct dpu_mdss_cfg dpu_sm8450_cfg; +extern const struct dpu_mdss_cfg dpu_sm8550_cfg; #endif /* _DPU_HW_CATALOG_H */ diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c index 6c53ea560ffa..bbdc95ce374a 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c @@ -26,15 +26,16 @@ #define CTL_SW_RESET 0x030 #define CTL_LAYER_EXTN_OFFSET 0x40 #define CTL_MERGE_3D_ACTIVE 0x0E4 +#define CTL_DSC_ACTIVE 0x0E8 #define CTL_WB_ACTIVE 0x0EC #define CTL_INTF_ACTIVE 0x0F4 +#define CTL_FETCH_PIPE_ACTIVE 0x0FC #define CTL_MERGE_3D_FLUSH 0x100 -#define CTL_DSC_ACTIVE 0x0E8 #define CTL_DSC_FLUSH 0x104 #define CTL_WB_FLUSH 0x108 #define CTL_INTF_FLUSH 0x110 #define CTL_INTF_MASTER 0x134 -#define CTL_FETCH_PIPE_ACTIVE 0x0FC +#define CTL_DSPP_n_FLUSH(n) ((0x13C) + ((n) * 4)) #define CTL_MIXER_BORDER_OUT BIT(24) #define CTL_FLUSH_MASK_CTL BIT(17) @@ -44,6 +45,7 @@ #define DSC_IDX 22 #define INTF_IDX 31 #define WB_IDX 16 +#define DSPP_IDX 29 /* From DPU hw rev 7.x.x */ #define CTL_INVALID_BIT 0xffff #define CTL_DEFAULT_GROUP_ID 0xf @@ -115,6 +117,9 @@ static inline void dpu_hw_ctl_clear_pending_flush(struct dpu_hw_ctl *ctx) trace_dpu_hw_ctl_clear_pending_flush(ctx->pending_flush_mask, dpu_hw_ctl_get_flush_register(ctx)); ctx->pending_flush_mask = 0x0; + + memset(ctx->pending_dspp_flush_mask, 0, + sizeof(ctx->pending_dspp_flush_mask)); } static inline void dpu_hw_ctl_update_pending_flush(struct dpu_hw_ctl *ctx, @@ -132,6 +137,8 @@ static u32 dpu_hw_ctl_get_pending_flush(struct dpu_hw_ctl *ctx) static inline void dpu_hw_ctl_trigger_flush_v1(struct dpu_hw_ctl *ctx) { + int dspp; + if (ctx->pending_flush_mask & BIT(MERGE_3D_IDX)) DPU_REG_WRITE(&ctx->hw, CTL_MERGE_3D_FLUSH, ctx->pending_merge_3d_flush_mask); @@ -142,6 +149,13 @@ static inline void dpu_hw_ctl_trigger_flush_v1(struct dpu_hw_ctl *ctx) DPU_REG_WRITE(&ctx->hw, CTL_WB_FLUSH, ctx->pending_wb_flush_mask); + if (ctx->pending_flush_mask & BIT(DSPP_IDX)) + for (dspp = DSPP_0; dspp < DSPP_MAX; dspp++) { + if (ctx->pending_dspp_flush_mask[dspp - DSPP_0]) + DPU_REG_WRITE(&ctx->hw, + CTL_DSPP_n_FLUSH(dspp - DSPP_0), + ctx->pending_dspp_flush_mask[dspp - DSPP_0]); + } DPU_REG_WRITE(&ctx->hw, CTL_FLUSH, ctx->pending_flush_mask); } @@ -289,7 +303,7 @@ static void dpu_hw_ctl_update_pending_flush_merge_3d_v1(struct dpu_hw_ctl *ctx, } static void dpu_hw_ctl_update_pending_flush_dspp(struct dpu_hw_ctl *ctx, - enum dpu_dspp dspp) + enum dpu_dspp dspp, u32 dspp_sub_blk) { switch (dspp) { case DSPP_0: @@ -309,6 +323,29 @@ static void dpu_hw_ctl_update_pending_flush_dspp(struct dpu_hw_ctl *ctx, } } +static void dpu_hw_ctl_update_pending_flush_dspp_sub_blocks( + struct dpu_hw_ctl *ctx, enum dpu_dspp dspp, u32 dspp_sub_blk) +{ + if (dspp >= DSPP_MAX) + return; + + switch (dspp_sub_blk) { + case DPU_DSPP_IGC: + ctx->pending_dspp_flush_mask[dspp - DSPP_0] |= BIT(2); + break; + case DPU_DSPP_PCC: + ctx->pending_dspp_flush_mask[dspp - DSPP_0] |= BIT(4); + break; + case DPU_DSPP_GC: + ctx->pending_dspp_flush_mask[dspp - DSPP_0] |= BIT(5); + break; + default: + return; + } + + ctx->pending_flush_mask |= BIT(DSPP_IDX); +} + static u32 dpu_hw_ctl_poll_reset_status(struct dpu_hw_ctl *ctx, u32 timeout_us) { struct dpu_hw_blk_reg_map *c = &ctx->hw; @@ -630,7 +667,11 @@ static void _setup_ctl_ops(struct dpu_hw_ctl_ops *ops, ops->setup_blendstage = dpu_hw_ctl_setup_blendstage; ops->update_pending_flush_sspp = dpu_hw_ctl_update_pending_flush_sspp; ops->update_pending_flush_mixer = dpu_hw_ctl_update_pending_flush_mixer; - ops->update_pending_flush_dspp = dpu_hw_ctl_update_pending_flush_dspp; + if (cap & BIT(DPU_CTL_DSPP_SUB_BLOCK_FLUSH)) + ops->update_pending_flush_dspp = dpu_hw_ctl_update_pending_flush_dspp_sub_blocks; + else + ops->update_pending_flush_dspp = dpu_hw_ctl_update_pending_flush_dspp; + if (cap & BIT(DPU_CTL_FETCH_ACTIVE)) ops->set_active_pipes = dpu_hw_ctl_set_fetch_pipe_active; }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h index 96c012ec8467..78611a831697 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h @@ -152,9 +152,11 @@ struct dpu_hw_ctl_ops { * No effect on hardware * @ctx : ctl path ctx pointer * @blk : DSPP block index + * @dspp_sub_blk : DSPP sub-block index */ void (*update_pending_flush_dspp)(struct dpu_hw_ctl *ctx, - enum dpu_dspp blk); + enum dpu_dspp blk, u32 dspp_sub_blk); + /** * Write the value of the pending_flush_mask to hardware * @ctx : ctl path ctx pointer @@ -242,6 +244,7 @@ struct dpu_hw_ctl { u32 pending_intf_flush_mask; u32 pending_wb_flush_mask; u32 pending_merge_3d_flush_mask; + u32 pending_dspp_flush_mask[DSPP_MAX - DSPP_0]; /* ops */ struct dpu_hw_ctl_ops ops; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c index 619926da1441..4e1396575e6a 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c @@ -175,7 +175,7 @@ static void dpu_hw_dsc_bind_pingpong_blk( DPU_REG_WRITE(c, dsc_ctl_offset, mux_cfg); } -static struct dpu_dsc_cfg *_dsc_offset(enum dpu_dsc dsc, +static const struct dpu_dsc_cfg *_dsc_offset(enum dpu_dsc dsc, const struct dpu_mdss_cfg *m, void __iomem *addr, struct dpu_hw_blk_reg_map *b) @@ -207,7 +207,7 @@ struct dpu_hw_dsc *dpu_hw_dsc_init(enum dpu_dsc idx, void __iomem *addr, const struct dpu_mdss_cfg *m) { struct dpu_hw_dsc *c; - struct dpu_dsc_cfg *cfg; + const struct dpu_dsc_cfg *cfg; c = kzalloc(sizeof(*c), GFP_KERNEL); if (!c) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c index 53326f25e40e..17f3e7e4f194 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c @@ -15,7 +15,7 @@ /* * Register offsets in MDSS register file for the interrupt registers - * w.r.t. to the MDP base + * w.r.t. the MDP base */ #define MDP_SSPP_TOP0_OFF 0x0 #define MDP_INTF_0_OFF 0x6A000 @@ -24,20 +24,23 @@ #define MDP_INTF_3_OFF 0x6B800 #define MDP_INTF_4_OFF 0x6C000 #define MDP_INTF_5_OFF 0x6C800 +#define INTF_INTR_EN 0x1c0 +#define INTF_INTR_STATUS 0x1c4 +#define INTF_INTR_CLEAR 0x1c8 #define MDP_AD4_0_OFF 0x7C000 #define MDP_AD4_1_OFF 0x7D000 #define MDP_AD4_INTR_EN_OFF 0x41c #define MDP_AD4_INTR_CLEAR_OFF 0x424 #define MDP_AD4_INTR_STATUS_OFF 0x420 -#define MDP_INTF_0_OFF_REV_7xxx 0x34000 -#define MDP_INTF_1_OFF_REV_7xxx 0x35000 -#define MDP_INTF_2_OFF_REV_7xxx 0x36000 -#define MDP_INTF_3_OFF_REV_7xxx 0x37000 -#define MDP_INTF_4_OFF_REV_7xxx 0x38000 -#define MDP_INTF_5_OFF_REV_7xxx 0x39000 -#define MDP_INTF_6_OFF_REV_7xxx 0x3a000 -#define MDP_INTF_7_OFF_REV_7xxx 0x3b000 -#define MDP_INTF_8_OFF_REV_7xxx 0x3c000 +#define MDP_INTF_0_OFF_REV_7xxx 0x34000 +#define MDP_INTF_1_OFF_REV_7xxx 0x35000 +#define MDP_INTF_2_OFF_REV_7xxx 0x36000 +#define MDP_INTF_3_OFF_REV_7xxx 0x37000 +#define MDP_INTF_4_OFF_REV_7xxx 0x38000 +#define MDP_INTF_5_OFF_REV_7xxx 0x39000 +#define MDP_INTF_6_OFF_REV_7xxx 0x3a000 +#define MDP_INTF_7_OFF_REV_7xxx 0x3b000 +#define MDP_INTF_8_OFF_REV_7xxx 0x3c000 /** * struct dpu_intr_reg - array of DPU register sets diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c index 7ce66bf3f4c8..b9dddf576c02 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c @@ -56,12 +56,8 @@ #define INTF_TPG_RGB_MAPPING 0x11C #define INTF_PROG_FETCH_START 0x170 #define INTF_PROG_ROT_START 0x174 - -#define INTF_FRAME_LINE_COUNT_EN 0x0A8 -#define INTF_FRAME_COUNT 0x0AC -#define INTF_LINE_COUNT 0x0B0 - #define INTF_MUX 0x25C +#define INTF_STATUS 0x26C #define INTF_CFG_ACTIVE_H_EN BIT(29) #define INTF_CFG_ACTIVE_V_EN BIT(30) @@ -297,8 +293,13 @@ static void dpu_hw_intf_get_status( struct intf_status *s) { struct dpu_hw_blk_reg_map *c = &intf->hw; + unsigned long cap = intf->cap->features; + + if (cap & BIT(DPU_INTF_STATUS_SUPPORTED)) + s->is_en = DPU_REG_READ(c, INTF_STATUS) & BIT(0); + else + s->is_en = DPU_REG_READ(c, INTF_TIMING_ENGINE_EN); - s->is_en = DPU_REG_READ(c, INTF_TIMING_ENGINE_EN); s->is_prog_fetch_en = !!(DPU_REG_READ(c, INTF_CONFIG) & BIT(31)); if (s->is_en) { s->frame_count = DPU_REG_READ(c, INTF_FRAME_COUNT); diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c index 4246ab0b3bee..cf70a9bd1034 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c @@ -136,7 +136,7 @@ #define TS_CLK 19200000 -static int _sspp_subblk_offset(struct dpu_hw_pipe *ctx, +static int _sspp_subblk_offset(struct dpu_hw_sspp *ctx, int s_id, u32 *idx) { @@ -168,17 +168,16 @@ static int _sspp_subblk_offset(struct dpu_hw_pipe *ctx, return rc; } -static void dpu_hw_sspp_setup_multirect(struct dpu_hw_pipe *ctx, - enum dpu_sspp_multirect_index index, - enum dpu_sspp_multirect_mode mode) +static void dpu_hw_sspp_setup_multirect(struct dpu_sw_pipe *pipe) { + struct dpu_hw_sspp *ctx = pipe->sspp; u32 mode_mask; u32 idx; if (_sspp_subblk_offset(ctx, DPU_SSPP_SRC, &idx)) return; - if (index == DPU_SSPP_RECT_SOLO) { + if (pipe->multirect_index == DPU_SSPP_RECT_SOLO) { /** * if rect index is RECT_SOLO, we cannot expect a * virtual plane sharing the same SSPP id. So we go @@ -187,8 +186,8 @@ static void dpu_hw_sspp_setup_multirect(struct dpu_hw_pipe *ctx, mode_mask = 0; } else { mode_mask = DPU_REG_READ(&ctx->hw, SSPP_MULTIRECT_OPMODE + idx); - mode_mask |= index; - if (mode == DPU_SSPP_MULTIRECT_TIME_MX) + mode_mask |= pipe->multirect_index; + if (pipe->multirect_mode == DPU_SSPP_MULTIRECT_TIME_MX) mode_mask |= BIT(2); else mode_mask &= ~BIT(2); @@ -197,7 +196,7 @@ static void dpu_hw_sspp_setup_multirect(struct dpu_hw_pipe *ctx, DPU_REG_WRITE(&ctx->hw, SSPP_MULTIRECT_OPMODE + idx, mode_mask); } -static void _sspp_setup_opmode(struct dpu_hw_pipe *ctx, +static void _sspp_setup_opmode(struct dpu_hw_sspp *ctx, u32 mask, u8 en) { u32 idx; @@ -218,7 +217,7 @@ static void _sspp_setup_opmode(struct dpu_hw_pipe *ctx, DPU_REG_WRITE(&ctx->hw, SSPP_VIG_OP_MODE + idx, opmode); } -static void _sspp_setup_csc10_opmode(struct dpu_hw_pipe *ctx, +static void _sspp_setup_csc10_opmode(struct dpu_hw_sspp *ctx, u32 mask, u8 en) { u32 idx; @@ -239,10 +238,10 @@ static void _sspp_setup_csc10_opmode(struct dpu_hw_pipe *ctx, /* * Setup source pixel format, flip, */ -static void dpu_hw_sspp_setup_format(struct dpu_hw_pipe *ctx, - const struct dpu_format *fmt, u32 flags, - enum dpu_sspp_multirect_index rect_mode) +static void dpu_hw_sspp_setup_format(struct dpu_sw_pipe *pipe, + const struct dpu_format *fmt, u32 flags) { + struct dpu_hw_sspp *ctx = pipe->sspp; struct dpu_hw_blk_reg_map *c; u32 chroma_samp, unpack, src_format; u32 opmode = 0; @@ -253,7 +252,8 @@ static void dpu_hw_sspp_setup_format(struct dpu_hw_pipe *ctx, if (_sspp_subblk_offset(ctx, DPU_SSPP_SRC, &idx) || !fmt) return; - if (rect_mode == DPU_SSPP_RECT_SOLO || rect_mode == DPU_SSPP_RECT_0) { + if (pipe->multirect_index == DPU_SSPP_RECT_SOLO || + pipe->multirect_index == DPU_SSPP_RECT_0) { op_mode_off = SSPP_SRC_OP_MODE; unpack_pat_off = SSPP_SRC_UNPACK_PATTERN; format_off = SSPP_SRC_FORMAT; @@ -307,25 +307,25 @@ static void dpu_hw_sspp_setup_format(struct dpu_hw_pipe *ctx, src_format |= (fmt->fetch_mode & 3) << 30; /*FRAME_FORMAT */ DPU_REG_WRITE(c, SSPP_FETCH_CONFIG, DPU_FETCH_CONFIG_RESET_VALUE | - ctx->mdp->highest_bank_bit << 18); - switch (ctx->catalog->caps->ubwc_version) { + ctx->ubwc->highest_bank_bit << 18); + switch (ctx->ubwc->ubwc_version) { case DPU_HW_UBWC_VER_10: fast_clear = fmt->alpha_enable ? BIT(31) : 0; DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL, - fast_clear | (ctx->mdp->ubwc_swizzle & 0x1) | + fast_clear | (ctx->ubwc->ubwc_swizzle & 0x1) | BIT(8) | - (ctx->mdp->highest_bank_bit << 4)); + (ctx->ubwc->highest_bank_bit << 4)); break; case DPU_HW_UBWC_VER_20: fast_clear = fmt->alpha_enable ? BIT(31) : 0; DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL, - fast_clear | (ctx->mdp->ubwc_swizzle) | - (ctx->mdp->highest_bank_bit << 4)); + fast_clear | (ctx->ubwc->ubwc_swizzle) | + (ctx->ubwc->highest_bank_bit << 4)); break; case DPU_HW_UBWC_VER_30: DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL, - BIT(30) | (ctx->mdp->ubwc_swizzle) | - (ctx->mdp->highest_bank_bit << 4)); + BIT(30) | (ctx->ubwc->ubwc_swizzle) | + (ctx->ubwc->highest_bank_bit << 4)); break; case DPU_HW_UBWC_VER_40: DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL, @@ -360,7 +360,7 @@ static void dpu_hw_sspp_setup_format(struct dpu_hw_pipe *ctx, DPU_REG_WRITE(c, SSPP_UBWC_ERROR_STATUS + idx, BIT(31)); } -static void dpu_hw_sspp_setup_pe_config(struct dpu_hw_pipe *ctx, +static void dpu_hw_sspp_setup_pe_config(struct dpu_hw_sspp *ctx, struct dpu_hw_pixel_ext *pe_ext) { struct dpu_hw_blk_reg_map *c; @@ -418,23 +418,22 @@ static void dpu_hw_sspp_setup_pe_config(struct dpu_hw_pipe *ctx, tot_req_pixels[3]); } -static void _dpu_hw_sspp_setup_scaler3(struct dpu_hw_pipe *ctx, - struct dpu_hw_pipe_cfg *sspp, - void *scaler_cfg) +static void _dpu_hw_sspp_setup_scaler3(struct dpu_hw_sspp *ctx, + struct dpu_hw_scaler3_cfg *scaler3_cfg, + const struct dpu_format *format) { u32 idx; - struct dpu_hw_scaler3_cfg *scaler3_cfg = scaler_cfg; - if (_sspp_subblk_offset(ctx, DPU_SSPP_SCALER_QSEED3, &idx) || !sspp + if (_sspp_subblk_offset(ctx, DPU_SSPP_SCALER_QSEED3, &idx) || !scaler3_cfg) return; dpu_hw_setup_scaler3(&ctx->hw, scaler3_cfg, idx, ctx->cap->sblk->scaler_blk.version, - sspp->layout.format); + format); } -static u32 _dpu_hw_sspp_get_scaler3_ver(struct dpu_hw_pipe *ctx) +static u32 _dpu_hw_sspp_get_scaler3_ver(struct dpu_hw_sspp *ctx) { u32 idx; @@ -447,12 +446,12 @@ static u32 _dpu_hw_sspp_get_scaler3_ver(struct dpu_hw_pipe *ctx) /* * dpu_hw_sspp_setup_rects() */ -static void dpu_hw_sspp_setup_rects(struct dpu_hw_pipe *ctx, - struct dpu_hw_pipe_cfg *cfg, - enum dpu_sspp_multirect_index rect_index) +static void dpu_hw_sspp_setup_rects(struct dpu_sw_pipe *pipe, + struct dpu_sw_pipe_cfg *cfg) { + struct dpu_hw_sspp *ctx = pipe->sspp; struct dpu_hw_blk_reg_map *c; - u32 src_size, src_xy, dst_size, dst_xy, ystride0, ystride1; + u32 src_size, src_xy, dst_size, dst_xy; u32 src_size_off, src_xy_off, out_size_off, out_xy_off; u32 idx; @@ -461,7 +460,8 @@ static void dpu_hw_sspp_setup_rects(struct dpu_hw_pipe *ctx, c = &ctx->hw; - if (rect_index == DPU_SSPP_RECT_SOLO || rect_index == DPU_SSPP_RECT_0) { + if (pipe->multirect_index == DPU_SSPP_RECT_SOLO || + pipe->multirect_index == DPU_SSPP_RECT_0) { src_size_off = SSPP_SRC_SIZE; src_xy_off = SSPP_SRC_XY; out_size_off = SSPP_OUT_SIZE; @@ -482,68 +482,69 @@ static void dpu_hw_sspp_setup_rects(struct dpu_hw_pipe *ctx, dst_size = (drm_rect_height(&cfg->dst_rect) << 16) | drm_rect_width(&cfg->dst_rect); - if (rect_index == DPU_SSPP_RECT_SOLO) { - ystride0 = (cfg->layout.plane_pitch[0]) | - (cfg->layout.plane_pitch[1] << 16); - ystride1 = (cfg->layout.plane_pitch[2]) | - (cfg->layout.plane_pitch[3] << 16); - } else { - ystride0 = DPU_REG_READ(c, SSPP_SRC_YSTRIDE0 + idx); - ystride1 = DPU_REG_READ(c, SSPP_SRC_YSTRIDE1 + idx); - - if (rect_index == DPU_SSPP_RECT_0) { - ystride0 = (ystride0 & 0xFFFF0000) | - (cfg->layout.plane_pitch[0] & 0x0000FFFF); - ystride1 = (ystride1 & 0xFFFF0000)| - (cfg->layout.plane_pitch[2] & 0x0000FFFF); - } else { - ystride0 = (ystride0 & 0x0000FFFF) | - ((cfg->layout.plane_pitch[0] << 16) & - 0xFFFF0000); - ystride1 = (ystride1 & 0x0000FFFF) | - ((cfg->layout.plane_pitch[2] << 16) & - 0xFFFF0000); - } - } - /* rectangle register programming */ DPU_REG_WRITE(c, src_size_off + idx, src_size); DPU_REG_WRITE(c, src_xy_off + idx, src_xy); DPU_REG_WRITE(c, out_size_off + idx, dst_size); DPU_REG_WRITE(c, out_xy_off + idx, dst_xy); - - DPU_REG_WRITE(c, SSPP_SRC_YSTRIDE0 + idx, ystride0); - DPU_REG_WRITE(c, SSPP_SRC_YSTRIDE1 + idx, ystride1); } -static void dpu_hw_sspp_setup_sourceaddress(struct dpu_hw_pipe *ctx, - struct dpu_hw_pipe_cfg *cfg, - enum dpu_sspp_multirect_index rect_mode) +static void dpu_hw_sspp_setup_sourceaddress(struct dpu_sw_pipe *pipe, + struct dpu_hw_fmt_layout *layout) { + struct dpu_hw_sspp *ctx = pipe->sspp; + u32 ystride0, ystride1; int i; u32 idx; if (_sspp_subblk_offset(ctx, DPU_SSPP_SRC, &idx)) return; - if (rect_mode == DPU_SSPP_RECT_SOLO) { - for (i = 0; i < ARRAY_SIZE(cfg->layout.plane_addr); i++) + if (pipe->multirect_index == DPU_SSPP_RECT_SOLO) { + for (i = 0; i < ARRAY_SIZE(layout->plane_addr); i++) DPU_REG_WRITE(&ctx->hw, SSPP_SRC0_ADDR + idx + i * 0x4, - cfg->layout.plane_addr[i]); - } else if (rect_mode == DPU_SSPP_RECT_0) { + layout->plane_addr[i]); + } else if (pipe->multirect_index == DPU_SSPP_RECT_0) { DPU_REG_WRITE(&ctx->hw, SSPP_SRC0_ADDR + idx, - cfg->layout.plane_addr[0]); + layout->plane_addr[0]); DPU_REG_WRITE(&ctx->hw, SSPP_SRC2_ADDR + idx, - cfg->layout.plane_addr[2]); + layout->plane_addr[2]); } else { DPU_REG_WRITE(&ctx->hw, SSPP_SRC1_ADDR + idx, - cfg->layout.plane_addr[0]); + layout->plane_addr[0]); DPU_REG_WRITE(&ctx->hw, SSPP_SRC3_ADDR + idx, - cfg->layout.plane_addr[2]); + layout->plane_addr[2]); } + + if (pipe->multirect_index == DPU_SSPP_RECT_SOLO) { + ystride0 = (layout->plane_pitch[0]) | + (layout->plane_pitch[1] << 16); + ystride1 = (layout->plane_pitch[2]) | + (layout->plane_pitch[3] << 16); + } else { + ystride0 = DPU_REG_READ(&ctx->hw, SSPP_SRC_YSTRIDE0 + idx); + ystride1 = DPU_REG_READ(&ctx->hw, SSPP_SRC_YSTRIDE1 + idx); + + if (pipe->multirect_index == DPU_SSPP_RECT_0) { + ystride0 = (ystride0 & 0xFFFF0000) | + (layout->plane_pitch[0] & 0x0000FFFF); + ystride1 = (ystride1 & 0xFFFF0000)| + (layout->plane_pitch[2] & 0x0000FFFF); + } else { + ystride0 = (ystride0 & 0x0000FFFF) | + ((layout->plane_pitch[0] << 16) & + 0xFFFF0000); + ystride1 = (ystride1 & 0x0000FFFF) | + ((layout->plane_pitch[2] << 16) & + 0xFFFF0000); + } + } + + DPU_REG_WRITE(&ctx->hw, SSPP_SRC_YSTRIDE0 + idx, ystride0); + DPU_REG_WRITE(&ctx->hw, SSPP_SRC_YSTRIDE1 + idx, ystride1); } -static void dpu_hw_sspp_setup_csc(struct dpu_hw_pipe *ctx, +static void dpu_hw_sspp_setup_csc(struct dpu_hw_sspp *ctx, const struct dpu_csc_cfg *data) { u32 idx; @@ -560,22 +561,28 @@ static void dpu_hw_sspp_setup_csc(struct dpu_hw_pipe *ctx, dpu_hw_csc_setup(&ctx->hw, idx, data, csc10); } -static void dpu_hw_sspp_setup_solidfill(struct dpu_hw_pipe *ctx, u32 color, enum - dpu_sspp_multirect_index rect_index) +static void dpu_hw_sspp_setup_solidfill(struct dpu_sw_pipe *pipe, u32 color) { + struct dpu_hw_sspp *ctx = pipe->sspp; + struct dpu_hw_fmt_layout cfg; u32 idx; if (_sspp_subblk_offset(ctx, DPU_SSPP_SRC, &idx)) return; - if (rect_index == DPU_SSPP_RECT_SOLO || rect_index == DPU_SSPP_RECT_0) + /* cleanup source addresses */ + memset(&cfg, 0, sizeof(cfg)); + ctx->ops.setup_sourceaddress(pipe, &cfg); + + if (pipe->multirect_index == DPU_SSPP_RECT_SOLO || + pipe->multirect_index == DPU_SSPP_RECT_0) DPU_REG_WRITE(&ctx->hw, SSPP_SRC_CONSTANT_COLOR + idx, color); else DPU_REG_WRITE(&ctx->hw, SSPP_SRC_CONSTANT_COLOR_REC1 + idx, color); } -static void dpu_hw_sspp_setup_danger_safe_lut(struct dpu_hw_pipe *ctx, +static void dpu_hw_sspp_setup_danger_safe_lut(struct dpu_hw_sspp *ctx, u32 danger_lut, u32 safe_lut) { @@ -588,7 +595,7 @@ static void dpu_hw_sspp_setup_danger_safe_lut(struct dpu_hw_pipe *ctx, DPU_REG_WRITE(&ctx->hw, SSPP_SAFE_LUT + idx, safe_lut); } -static void dpu_hw_sspp_setup_creq_lut(struct dpu_hw_pipe *ctx, +static void dpu_hw_sspp_setup_creq_lut(struct dpu_hw_sspp *ctx, u64 creq_lut) { u32 idx; @@ -605,7 +612,7 @@ static void dpu_hw_sspp_setup_creq_lut(struct dpu_hw_pipe *ctx, } } -static void dpu_hw_sspp_setup_qos_ctrl(struct dpu_hw_pipe *ctx, +static void dpu_hw_sspp_setup_qos_ctrl(struct dpu_hw_sspp *ctx, struct dpu_hw_pipe_qos_cfg *cfg) { u32 idx; @@ -630,10 +637,10 @@ static void dpu_hw_sspp_setup_qos_ctrl(struct dpu_hw_pipe *ctx, DPU_REG_WRITE(&ctx->hw, SSPP_QOS_CTRL + idx, qos_ctrl); } -static void dpu_hw_sspp_setup_cdp(struct dpu_hw_pipe *ctx, - struct dpu_hw_cdp_cfg *cfg, - enum dpu_sspp_multirect_index index) +static void dpu_hw_sspp_setup_cdp(struct dpu_sw_pipe *pipe, + struct dpu_hw_cdp_cfg *cfg) { + struct dpu_hw_sspp *ctx = pipe->sspp; u32 idx; u32 cdp_cntl = 0; u32 cdp_cntl_offset = 0; @@ -644,7 +651,8 @@ static void dpu_hw_sspp_setup_cdp(struct dpu_hw_pipe *ctx, if (_sspp_subblk_offset(ctx, DPU_SSPP_SRC, &idx)) return; - if (index == DPU_SSPP_RECT_SOLO || index == DPU_SSPP_RECT_0) + if (pipe->multirect_index == DPU_SSPP_RECT_SOLO || + pipe->multirect_index == DPU_SSPP_RECT_0) cdp_cntl_offset = SSPP_CDP_CNTL; else cdp_cntl_offset = SSPP_CDP_CNTL_REC1; @@ -661,7 +669,7 @@ static void dpu_hw_sspp_setup_cdp(struct dpu_hw_pipe *ctx, DPU_REG_WRITE(&ctx->hw, cdp_cntl_offset, cdp_cntl); } -static void _setup_layer_ops(struct dpu_hw_pipe *c, +static void _setup_layer_ops(struct dpu_hw_sspp *c, unsigned long features) { if (test_bit(DPU_SSPP_SRC, &features)) { @@ -699,7 +707,8 @@ static void _setup_layer_ops(struct dpu_hw_pipe *c, } #ifdef CONFIG_DEBUG_FS -int _dpu_hw_sspp_init_debugfs(struct dpu_hw_pipe *hw_pipe, struct dpu_kms *kms, struct dentry *entry) +int _dpu_hw_sspp_init_debugfs(struct dpu_hw_sspp *hw_pipe, struct dpu_kms *kms, + struct dentry *entry) { const struct dpu_sspp_cfg *cfg = hw_pipe->cap; const struct dpu_sspp_sub_blks *sblk = cfg->sblk; @@ -783,10 +792,10 @@ static const struct dpu_sspp_cfg *_sspp_offset(enum dpu_sspp sspp, return ERR_PTR(-ENOMEM); } -struct dpu_hw_pipe *dpu_hw_sspp_init(enum dpu_sspp idx, +struct dpu_hw_sspp *dpu_hw_sspp_init(enum dpu_sspp idx, void __iomem *addr, const struct dpu_mdss_cfg *catalog) { - struct dpu_hw_pipe *hw_pipe; + struct dpu_hw_sspp *hw_pipe; const struct dpu_sspp_cfg *cfg; if (!addr || !catalog) @@ -804,7 +813,7 @@ struct dpu_hw_pipe *dpu_hw_sspp_init(enum dpu_sspp idx, /* Assign ops */ hw_pipe->catalog = catalog; - hw_pipe->mdp = &catalog->mdp[0]; + hw_pipe->ubwc = catalog->ubwc; hw_pipe->idx = idx; hw_pipe->cap = cfg; _setup_layer_ops(hw_pipe, hw_pipe->cap->features); @@ -812,7 +821,7 @@ struct dpu_hw_pipe *dpu_hw_sspp_init(enum dpu_sspp idx, return hw_pipe; } -void dpu_hw_sspp_destroy(struct dpu_hw_pipe *ctx) +void dpu_hw_sspp_destroy(struct dpu_hw_sspp *ctx) { kfree(ctx); } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h index 0c95b7e64f6c..74b98b6b3bc3 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h @@ -10,7 +10,7 @@ #include "dpu_hw_util.h" #include "dpu_formats.h" -struct dpu_hw_pipe; +struct dpu_hw_sspp; /** * Flags @@ -153,20 +153,14 @@ struct dpu_hw_pixel_ext { }; /** - * struct dpu_hw_pipe_cfg : Pipe description - * @layout: format layout information for programming buffer to hardware + * struct dpu_sw_pipe_cfg : software pipe configuration * @src_rect: src ROI, caller takes into account the different operations * such as decimation, flip etc to program this field * @dest_rect: destination ROI. - * @index: index of the rectangle of SSPP - * @mode: parallel or time multiplex multirect mode */ -struct dpu_hw_pipe_cfg { - struct dpu_hw_fmt_layout layout; +struct dpu_sw_pipe_cfg { struct drm_rect src_rect; struct drm_rect dst_rect; - enum dpu_sspp_multirect_index index; - enum dpu_sspp_multirect_mode mode; }; /** @@ -202,6 +196,18 @@ struct dpu_hw_pipe_ts_cfg { }; /** + * struct dpu_sw_pipe - software pipe description + * @sspp: backing SSPP pipe + * @index: index of the rectangle of SSPP + * @mode: parallel or time multiplex multirect mode + */ +struct dpu_sw_pipe { + struct dpu_hw_sspp *sspp; + enum dpu_sspp_multirect_index multirect_index; + enum dpu_sspp_multirect_mode multirect_mode; +}; + +/** * struct dpu_hw_sspp_ops - interface to the SSPP Hw driver functions * Caller must call the init function to get the pipe context for each pipe * Assumption is these functions will be called after clocks are enabled @@ -209,77 +215,65 @@ struct dpu_hw_pipe_ts_cfg { struct dpu_hw_sspp_ops { /** * setup_format - setup pixel format cropping rectangle, flip - * @ctx: Pointer to pipe context + * @pipe: Pointer to software pipe context * @cfg: Pointer to pipe config structure * @flags: Extra flags for format config - * @index: rectangle index in multirect */ - void (*setup_format)(struct dpu_hw_pipe *ctx, - const struct dpu_format *fmt, u32 flags, - enum dpu_sspp_multirect_index index); + void (*setup_format)(struct dpu_sw_pipe *pipe, + const struct dpu_format *fmt, u32 flags); /** * setup_rects - setup pipe ROI rectangles - * @ctx: Pointer to pipe context + * @pipe: Pointer to software pipe context * @cfg: Pointer to pipe config structure - * @index: rectangle index in multirect */ - void (*setup_rects)(struct dpu_hw_pipe *ctx, - struct dpu_hw_pipe_cfg *cfg, - enum dpu_sspp_multirect_index index); + void (*setup_rects)(struct dpu_sw_pipe *pipe, + struct dpu_sw_pipe_cfg *cfg); /** * setup_pe - setup pipe pixel extension * @ctx: Pointer to pipe context * @pe_ext: Pointer to pixel ext settings */ - void (*setup_pe)(struct dpu_hw_pipe *ctx, + void (*setup_pe)(struct dpu_hw_sspp *ctx, struct dpu_hw_pixel_ext *pe_ext); /** * setup_sourceaddress - setup pipe source addresses - * @ctx: Pointer to pipe context - * @cfg: Pointer to pipe config structure - * @index: rectangle index in multirect + * @pipe: Pointer to software pipe context + * @layout: format layout information for programming buffer to hardware */ - void (*setup_sourceaddress)(struct dpu_hw_pipe *ctx, - struct dpu_hw_pipe_cfg *cfg, - enum dpu_sspp_multirect_index index); + void (*setup_sourceaddress)(struct dpu_sw_pipe *ctx, + struct dpu_hw_fmt_layout *layout); /** * setup_csc - setup color space coversion * @ctx: Pointer to pipe context * @data: Pointer to config structure */ - void (*setup_csc)(struct dpu_hw_pipe *ctx, const struct dpu_csc_cfg *data); + void (*setup_csc)(struct dpu_hw_sspp *ctx, const struct dpu_csc_cfg *data); /** * setup_solidfill - enable/disable colorfill - * @ctx: Pointer to pipe context + * @pipe: Pointer to software pipe context * @const_color: Fill color value * @flags: Pipe flags - * @index: rectangle index in multirect */ - void (*setup_solidfill)(struct dpu_hw_pipe *ctx, u32 color, - enum dpu_sspp_multirect_index index); + void (*setup_solidfill)(struct dpu_sw_pipe *pipe, u32 color); /** * setup_multirect - setup multirect configuration - * @ctx: Pointer to pipe context - * @index: rectangle index in multirect - * @mode: parallel fetch / time multiplex multirect mode + * @pipe: Pointer to software pipe context */ - void (*setup_multirect)(struct dpu_hw_pipe *ctx, - enum dpu_sspp_multirect_index index, - enum dpu_sspp_multirect_mode mode); + void (*setup_multirect)(struct dpu_sw_pipe *pipe); /** * setup_sharpening - setup sharpening * @ctx: Pointer to pipe context * @cfg: Pointer to config structure */ - void (*setup_sharpening)(struct dpu_hw_pipe *ctx, + void (*setup_sharpening)(struct dpu_hw_sspp *ctx, struct dpu_hw_sharp_cfg *cfg); /** @@ -289,7 +283,7 @@ struct dpu_hw_sspp_ops { * @safe_lut: LUT for generate safe level based on fill level * */ - void (*setup_danger_safe_lut)(struct dpu_hw_pipe *ctx, + void (*setup_danger_safe_lut)(struct dpu_hw_sspp *ctx, u32 danger_lut, u32 safe_lut); @@ -299,7 +293,7 @@ struct dpu_hw_sspp_ops { * @creq_lut: LUT for generate creq level based on fill level * */ - void (*setup_creq_lut)(struct dpu_hw_pipe *ctx, + void (*setup_creq_lut)(struct dpu_hw_sspp *ctx, u64 creq_lut); /** @@ -308,7 +302,7 @@ struct dpu_hw_sspp_ops { * @cfg: Pointer to pipe QoS configuration * */ - void (*setup_qos_ctrl)(struct dpu_hw_pipe *ctx, + void (*setup_qos_ctrl)(struct dpu_hw_sspp *ctx, struct dpu_hw_pipe_qos_cfg *cfg); /** @@ -316,51 +310,48 @@ struct dpu_hw_sspp_ops { * @ctx: Pointer to pipe context * @cfg: Pointer to histogram configuration */ - void (*setup_histogram)(struct dpu_hw_pipe *ctx, + void (*setup_histogram)(struct dpu_hw_sspp *ctx, void *cfg); /** * setup_scaler - setup scaler - * @ctx: Pointer to pipe context - * @pipe_cfg: Pointer to pipe configuration - * @scaler_cfg: Pointer to scaler configuration + * @scaler3_cfg: Pointer to scaler configuration + * @format: pixel format parameters */ - void (*setup_scaler)(struct dpu_hw_pipe *ctx, - struct dpu_hw_pipe_cfg *pipe_cfg, - void *scaler_cfg); + void (*setup_scaler)(struct dpu_hw_sspp *ctx, + struct dpu_hw_scaler3_cfg *scaler3_cfg, + const struct dpu_format *format); /** * get_scaler_ver - get scaler h/w version * @ctx: Pointer to pipe context */ - u32 (*get_scaler_ver)(struct dpu_hw_pipe *ctx); + u32 (*get_scaler_ver)(struct dpu_hw_sspp *ctx); /** * setup_cdp - setup client driven prefetch - * @ctx: Pointer to pipe context + * @pipe: Pointer to software pipe context * @cfg: Pointer to cdp configuration - * @index: rectangle index in multirect */ - void (*setup_cdp)(struct dpu_hw_pipe *ctx, - struct dpu_hw_cdp_cfg *cfg, - enum dpu_sspp_multirect_index index); + void (*setup_cdp)(struct dpu_sw_pipe *pipe, + struct dpu_hw_cdp_cfg *cfg); }; /** - * struct dpu_hw_pipe - pipe description + * struct dpu_hw_sspp - pipe description * @base: hardware block base structure * @hw: block hardware details * @catalog: back pointer to catalog - * @mdp: pointer to associated mdp portion of the catalog + * @ubwc: ubwc configuration data * @idx: pipe index * @cap: pointer to layer_cfg * @ops: pointer to operations possible for this pipe */ -struct dpu_hw_pipe { +struct dpu_hw_sspp { struct dpu_hw_blk base; struct dpu_hw_blk_reg_map hw; const struct dpu_mdss_cfg *catalog; - const struct dpu_mdp_cfg *mdp; + const struct dpu_ubwc_cfg *ubwc; /* Pipe */ enum dpu_sspp idx; @@ -378,7 +369,7 @@ struct dpu_kms; * @addr: Mapped register io address of MDP * @catalog : Pointer to mdss catalog data */ -struct dpu_hw_pipe *dpu_hw_sspp_init(enum dpu_sspp idx, +struct dpu_hw_sspp *dpu_hw_sspp_init(enum dpu_sspp idx, void __iomem *addr, const struct dpu_mdss_cfg *catalog); /** @@ -386,10 +377,10 @@ struct dpu_hw_pipe *dpu_hw_sspp_init(enum dpu_sspp idx, * should be called during Hw pipe cleanup. * @ctx: Pointer to SSPP driver context returned by dpu_hw_sspp_init */ -void dpu_hw_sspp_destroy(struct dpu_hw_pipe *ctx); +void dpu_hw_sspp_destroy(struct dpu_hw_sspp *ctx); -void dpu_debugfs_sspp_init(struct dpu_kms *dpu_kms, struct dentry *debugfs_root); -int _dpu_hw_sspp_init_debugfs(struct dpu_hw_pipe *hw_pipe, struct dpu_kms *kms, struct dentry *entry); +int _dpu_hw_sspp_init_debugfs(struct dpu_hw_sspp *hw_pipe, struct dpu_kms *kms, + struct dentry *entry); #endif /*_DPU_HW_SSPP_H */ diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c index 2d28afdf860e..a3e413d27717 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c @@ -61,6 +61,7 @@ static const struct dpu_wb_cfg *_wb_offset(enum dpu_wb wb, for (i = 0; i < m->wb_count; i++) { if (wb == m->wb[i].id) { b->blk_addr = addr + m->wb[i].base; + b->log_mask = DPU_DBG_MASK_WB; return &m->wb[i]; } } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hwio.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hwio.h index feb9a729844a..5acd5683d25a 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hwio.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hwio.h @@ -21,9 +21,6 @@ #define HIST_INTR_EN 0x01c #define HIST_INTR_STATUS 0x020 #define HIST_INTR_CLEAR 0x024 -#define INTF_INTR_EN 0x1C0 -#define INTF_INTR_STATUS 0x1C4 -#define INTF_INTR_CLEAR 0x1C8 #define SPLIT_DISPLAY_EN 0x2F4 #define SPLIT_DISPLAY_UPPER_PIPE_CTRL 0x2F8 #define DSPP_IGC_COLOR0_RAM_LUTN 0x300 diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c index a683bd9b5a04..0e7a68714e9e 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -250,6 +250,24 @@ void dpu_debugfs_create_regset32(const char *name, umode_t mode, debugfs_create_file(name, mode, parent, regset, &dpu_regset32_fops); } +static void dpu_debugfs_sspp_init(struct dpu_kms *dpu_kms, struct dentry *debugfs_root) +{ + struct dentry *entry = debugfs_create_dir("sspp", debugfs_root); + int i; + + if (IS_ERR(entry)) + return; + + for (i = SSPP_NONE; i < SSPP_MAX; i++) { + struct dpu_hw_sspp *hw = dpu_rm_get_sspp(&dpu_kms->rm, i); + + if (!hw) + continue; + + _dpu_hw_sspp_init_debugfs(hw, dpu_kms, entry); + } +} + static int dpu_kms_debugfs_init(struct msm_kms *kms, struct drm_minor *minor) { struct dpu_kms *dpu_kms = to_dpu_kms(kms); @@ -411,40 +429,6 @@ static void dpu_kms_disable_commit(struct msm_kms *kms) pm_runtime_put_sync(&dpu_kms->pdev->dev); } -static ktime_t dpu_kms_vsync_time(struct msm_kms *kms, struct drm_crtc *crtc) -{ - struct drm_encoder *encoder; - - drm_for_each_encoder_mask(encoder, crtc->dev, crtc->state->encoder_mask) { - ktime_t vsync_time; - - if (dpu_encoder_vsync_time(encoder, &vsync_time) == 0) - return vsync_time; - } - - return ktime_get(); -} - -static void dpu_kms_prepare_commit(struct msm_kms *kms, - struct drm_atomic_state *state) -{ - struct drm_crtc *crtc; - struct drm_crtc_state *crtc_state; - struct drm_encoder *encoder; - int i; - - if (!kms) - return; - - /* Call prepare_commit for all affected encoders */ - for_each_new_crtc_in_state(state, crtc, crtc_state, i) { - drm_for_each_encoder_mask(encoder, crtc->dev, - crtc_state->encoder_mask) { - dpu_encoder_prepare_commit(encoder); - } - } -} - static void dpu_kms_flush_commit(struct msm_kms *kms, unsigned crtc_mask) { struct dpu_kms *dpu_kms = to_dpu_kms(kms); @@ -491,7 +475,7 @@ static void dpu_kms_wait_for_commit_done(struct msm_kms *kms, return; } - if (!crtc->state->active) { + if (!drm_atomic_crtc_effectively_active(crtc->state)) { DPU_DEBUG("[crtc:%d] not active\n", crtc->base.id); return; } @@ -953,8 +937,6 @@ static const struct msm_kms_funcs kms_funcs = { .irq = dpu_core_irq, .enable_commit = dpu_kms_enable_commit, .disable_commit = dpu_kms_disable_commit, - .vsync_time = dpu_kms_vsync_time, - .prepare_commit = dpu_kms_prepare_commit, .flush_commit = dpu_kms_flush_commit, .wait_flush = dpu_kms_wait_flush, .complete_commit = dpu_kms_complete_commit, @@ -1013,6 +995,7 @@ static int dpu_kms_hw_init(struct msm_kms *kms) struct dpu_kms *dpu_kms; struct drm_device *dev; int i, rc = -EINVAL; + u32 core_rev; if (!kms) { DPU_ERROR("invalid kms\n"); @@ -1062,17 +1045,14 @@ static int dpu_kms_hw_init(struct msm_kms *kms) if (rc < 0) goto error; - dpu_kms->core_rev = readl_relaxed(dpu_kms->mmio + 0x0); + core_rev = readl_relaxed(dpu_kms->mmio + 0x0); - pr_info("dpu hardware revision:0x%x\n", dpu_kms->core_rev); + pr_info("dpu hardware revision:0x%x\n", core_rev); - dpu_kms->catalog = dpu_hw_catalog_init(dpu_kms->core_rev); - if (IS_ERR_OR_NULL(dpu_kms->catalog)) { - rc = PTR_ERR(dpu_kms->catalog); - if (!dpu_kms->catalog) - rc = -EINVAL; - DPU_ERROR("catalog init failed: %d\n", rc); - dpu_kms->catalog = NULL; + dpu_kms->catalog = of_device_get_match_data(dev->dev); + if (!dpu_kms->catalog) { + DPU_ERROR("device config not known!\n"); + rc = -EINVAL; goto power_error; } @@ -1298,19 +1278,19 @@ static const struct dev_pm_ops dpu_pm_ops = { }; static const struct of_device_id dpu_dt_match[] = { - { .compatible = "qcom,msm8998-dpu", }, - { .compatible = "qcom,qcm2290-dpu", }, - { .compatible = "qcom,sdm845-dpu", }, - { .compatible = "qcom,sc7180-dpu", }, - { .compatible = "qcom,sc7280-dpu", }, - { .compatible = "qcom,sc8180x-dpu", }, - { .compatible = "qcom,sc8280xp-dpu", }, - { .compatible = "qcom,sm6115-dpu", }, - { .compatible = "qcom,sm8150-dpu", }, - { .compatible = "qcom,sm8250-dpu", }, - { .compatible = "qcom,sm8350-dpu", }, - { .compatible = "qcom,sm8450-dpu", }, - { .compatible = "qcom,sm8550-dpu", }, + { .compatible = "qcom,msm8998-dpu", .data = &dpu_msm8998_cfg, }, + { .compatible = "qcom,qcm2290-dpu", .data = &dpu_qcm2290_cfg, }, + { .compatible = "qcom,sdm845-dpu", .data = &dpu_sdm845_cfg, }, + { .compatible = "qcom,sc7180-dpu", .data = &dpu_sc7180_cfg, }, + { .compatible = "qcom,sc7280-dpu", .data = &dpu_sc7280_cfg, }, + { .compatible = "qcom,sc8180x-dpu", .data = &dpu_sc8180x_cfg, }, + { .compatible = "qcom,sc8280xp-dpu", .data = &dpu_sc8280xp_cfg, }, + { .compatible = "qcom,sm6115-dpu", .data = &dpu_sm6115_cfg, }, + { .compatible = "qcom,sm8150-dpu", .data = &dpu_sm8150_cfg, }, + { .compatible = "qcom,sm8250-dpu", .data = &dpu_sm8250_cfg, }, + { .compatible = "qcom,sm8350-dpu", .data = &dpu_sm8350_cfg, }, + { .compatible = "qcom,sm8450-dpu", .data = &dpu_sm8450_cfg, }, + { .compatible = "qcom,sm8550-dpu", .data = &dpu_sm8550_cfg, }, {} }; MODULE_DEVICE_TABLE(of, dpu_dt_match); diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h index ed80ed6784ee..aca39a4689f4 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h @@ -68,7 +68,6 @@ struct dpu_kms { struct msm_kms base; struct drm_device *dev; - int core_rev; const struct dpu_mdss_cfg *catalog; /* io/register spaces: */ diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c index bfd5be89e8b8..14b5cfe30611 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -47,13 +47,6 @@ #define DPU_PLANE_COLOR_FILL_FLAG BIT(31) #define DPU_ZPOS_MAX 255 -/* multirect rect index */ -enum { - R0, - R1, - R_MAX -}; - /* * Default Preload Values */ @@ -69,6 +62,7 @@ static const uint32_t qcom_compressed_supported_formats[] = { DRM_FORMAT_ARGB8888, DRM_FORMAT_XBGR8888, DRM_FORMAT_XRGB8888, + DRM_FORMAT_ARGB2101010, DRM_FORMAT_XRGB2101010, DRM_FORMAT_BGR565, @@ -104,7 +98,6 @@ struct dpu_plane { enum dpu_sspp pipe; - struct dpu_hw_pipe *pipe_hw; uint32_t color_fill; bool is_error; bool is_rt_pipe; @@ -128,21 +121,19 @@ static struct dpu_kms *_dpu_plane_get_kms(struct drm_plane *plane) /** * _dpu_plane_calc_bw - calculate bandwidth required for a plane - * @plane: Pointer to drm plane. - * @fb: Pointer to framebuffer associated with the given plane + * @catalog: Points to dpu catalog structure + * @fmt: Pointer to source buffer format + * @mode: Pointer to drm display mode * @pipe_cfg: Pointer to pipe configuration * Result: Updates calculated bandwidth in the plane state. * BW Equation: src_w * src_h * bpp * fps * (v_total / v_dest) * Prefill BW Equation: line src bytes * line_time */ -static void _dpu_plane_calc_bw(struct drm_plane *plane, - struct drm_framebuffer *fb, - struct dpu_hw_pipe_cfg *pipe_cfg) +static u64 _dpu_plane_calc_bw(const struct dpu_mdss_cfg *catalog, + const struct dpu_format *fmt, + const struct drm_display_mode *mode, + struct dpu_sw_pipe_cfg *pipe_cfg) { - struct dpu_plane_state *pstate; - struct drm_display_mode *mode; - const struct dpu_format *fmt = NULL; - struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane); int src_width, src_height, dst_height, fps; u64 plane_prefill_bw; u64 plane_bw; @@ -150,11 +141,6 @@ static void _dpu_plane_calc_bw(struct drm_plane *plane, u64 scale_factor; int vbp, vpw, vfp; - pstate = to_dpu_plane_state(plane->state); - mode = &plane->state->crtc->mode; - - fmt = dpu_get_dpu_format_ext(fb->format->format, fb->modifier); - src_width = drm_rect_width(&pipe_cfg->src_rect); src_height = drm_rect_height(&pipe_cfg->src_rect); dst_height = drm_rect_height(&pipe_cfg->dst_rect); @@ -162,7 +148,7 @@ static void _dpu_plane_calc_bw(struct drm_plane *plane, vbp = mode->vtotal - mode->vsync_end; vpw = mode->vsync_end - mode->vsync_start; vfp = mode->vsync_start - mode->vdisplay; - hw_latency_lines = dpu_kms->catalog->perf->min_prefill_lines; + hw_latency_lines = catalog->perf->min_prefill_lines; scale_factor = src_height > dst_height ? mult_frac(src_height, 1, dst_height) : 1; @@ -182,61 +168,60 @@ static void _dpu_plane_calc_bw(struct drm_plane *plane, do_div(plane_prefill_bw, hw_latency_lines); - pstate->plane_fetch_bw = max(plane_bw, plane_prefill_bw); + return max(plane_bw, plane_prefill_bw); } /** * _dpu_plane_calc_clk - calculate clock required for a plane - * @plane: Pointer to drm plane. + * @mode: Pointer to drm display mode * @pipe_cfg: Pointer to pipe configuration * Result: Updates calculated clock in the plane state. * Clock equation: dst_w * v_total * fps * (src_h / dst_h) */ -static void _dpu_plane_calc_clk(struct drm_plane *plane, struct dpu_hw_pipe_cfg *pipe_cfg) +static u64 _dpu_plane_calc_clk(const struct drm_display_mode *mode, + struct dpu_sw_pipe_cfg *pipe_cfg) { - struct dpu_plane_state *pstate; - struct drm_display_mode *mode; int dst_width, src_height, dst_height, fps; - - pstate = to_dpu_plane_state(plane->state); - mode = &plane->state->crtc->mode; + u64 plane_clk; src_height = drm_rect_height(&pipe_cfg->src_rect); dst_width = drm_rect_width(&pipe_cfg->dst_rect); dst_height = drm_rect_height(&pipe_cfg->dst_rect); fps = drm_mode_vrefresh(mode); - pstate->plane_clk = + plane_clk = dst_width * mode->vtotal * fps; if (src_height > dst_height) { - pstate->plane_clk *= src_height; - do_div(pstate->plane_clk, dst_height); + plane_clk *= src_height; + do_div(plane_clk, dst_height); } + + return plane_clk; } /** * _dpu_plane_calc_fill_level - calculate fill level of the given source format * @plane: Pointer to drm plane + * @pipe: Pointer to software pipe * @fmt: Pointer to source buffer format * @src_width: width of source buffer * Return: fill level corresponding to the source buffer/format or 0 if error */ static int _dpu_plane_calc_fill_level(struct drm_plane *plane, + struct dpu_sw_pipe *pipe, const struct dpu_format *fmt, u32 src_width) { struct dpu_plane *pdpu; - struct dpu_plane_state *pstate; u32 fixed_buff_size; u32 total_fl; - if (!fmt || !plane->state || !src_width || !fmt->bpp) { + if (!fmt || !pipe || !src_width || !fmt->bpp) { DPU_ERROR("invalid arguments\n"); return 0; } pdpu = to_dpu_plane(plane); - pstate = to_dpu_plane_state(plane->state); fixed_buff_size = pdpu->catalog->caps->pixel_ram_size; /* FIXME: in multirect case account for the src_width of all the planes */ @@ -252,7 +237,7 @@ static int _dpu_plane_calc_fill_level(struct drm_plane *plane, ((src_width + 32) * fmt->bpp); } } else { - if (pstate->multirect_mode == DPU_SSPP_MULTIRECT_PARALLEL) { + if (pipe->multirect_mode == DPU_SSPP_MULTIRECT_PARALLEL) { total_fl = (fixed_buff_size / 2) * 2 / ((src_width + 32) * fmt->bpp); } else { @@ -262,7 +247,7 @@ static int _dpu_plane_calc_fill_level(struct drm_plane *plane, } DPU_DEBUG_PLANE(pdpu, "pnum:%d fmt: %4.4s w:%u fl:%u\n", - pdpu->pipe - SSPP_VIG0, + pipe->sspp->idx - SSPP_VIG0, (char *)&fmt->base.pixel_format, src_width, total_fl); @@ -272,24 +257,22 @@ static int _dpu_plane_calc_fill_level(struct drm_plane *plane, /** * _dpu_plane_set_qos_lut - set QoS LUT of the given plane * @plane: Pointer to drm plane - * @fb: Pointer to framebuffer associated with the given plane + * @pipe: Pointer to software pipe + * @fmt: Pointer to source buffer format * @pipe_cfg: Pointer to pipe configuration */ static void _dpu_plane_set_qos_lut(struct drm_plane *plane, - struct drm_framebuffer *fb, struct dpu_hw_pipe_cfg *pipe_cfg) + struct dpu_sw_pipe *pipe, + const struct dpu_format *fmt, struct dpu_sw_pipe_cfg *pipe_cfg) { struct dpu_plane *pdpu = to_dpu_plane(plane); - const struct dpu_format *fmt = NULL; u64 qos_lut; u32 total_fl = 0, lut_usage; if (!pdpu->is_rt_pipe) { lut_usage = DPU_QOS_LUT_USAGE_NRT; } else { - fmt = dpu_get_dpu_format_ext( - fb->format->format, - fb->modifier); - total_fl = _dpu_plane_calc_fill_level(plane, fmt, + total_fl = _dpu_plane_calc_fill_level(plane, pipe, fmt, drm_rect_width(&pipe_cfg->src_rect)); if (fmt && DPU_FORMAT_IS_LINEAR(fmt)) @@ -301,7 +284,7 @@ static void _dpu_plane_set_qos_lut(struct drm_plane *plane, qos_lut = _dpu_hw_get_qos_lut( &pdpu->catalog->perf->qos_lut_tbl[lut_usage], total_fl); - trace_dpu_perf_set_qos_luts(pdpu->pipe - SSPP_VIG0, + trace_dpu_perf_set_qos_luts(pipe->sspp->idx - SSPP_VIG0, (fmt) ? fmt->base.pixel_format : 0, pdpu->is_rt_pipe, total_fl, qos_lut, lut_usage); @@ -310,19 +293,20 @@ static void _dpu_plane_set_qos_lut(struct drm_plane *plane, fmt ? (char *)&fmt->base.pixel_format : NULL, pdpu->is_rt_pipe, total_fl, qos_lut); - pdpu->pipe_hw->ops.setup_creq_lut(pdpu->pipe_hw, qos_lut); + pipe->sspp->ops.setup_creq_lut(pipe->sspp, qos_lut); } /** * _dpu_plane_set_danger_lut - set danger/safe LUT of the given plane * @plane: Pointer to drm plane - * @fb: Pointer to framebuffer associated with the given plane + * @pipe: Pointer to software pipe + * @fmt: Pointer to source buffer format */ static void _dpu_plane_set_danger_lut(struct drm_plane *plane, - struct drm_framebuffer *fb) + struct dpu_sw_pipe *pipe, + const struct dpu_format *fmt) { struct dpu_plane *pdpu = to_dpu_plane(plane); - const struct dpu_format *fmt = NULL; u32 danger_lut, safe_lut; if (!pdpu->is_rt_pipe) { @@ -331,10 +315,6 @@ static void _dpu_plane_set_danger_lut(struct drm_plane *plane, safe_lut = pdpu->catalog->perf->safe_lut_tbl [DPU_QOS_LUT_USAGE_NRT]; } else { - fmt = dpu_get_dpu_format_ext( - fb->format->format, - fb->modifier); - if (fmt && DPU_FORMAT_IS_LINEAR(fmt)) { danger_lut = pdpu->catalog->perf->danger_lut_tbl [DPU_QOS_LUT_USAGE_LINEAR]; @@ -361,17 +341,19 @@ static void _dpu_plane_set_danger_lut(struct drm_plane *plane, danger_lut, safe_lut); - pdpu->pipe_hw->ops.setup_danger_safe_lut(pdpu->pipe_hw, + pipe->sspp->ops.setup_danger_safe_lut(pipe->sspp, danger_lut, safe_lut); } /** * _dpu_plane_set_qos_ctrl - set QoS control of the given plane * @plane: Pointer to drm plane + * @pipe: Pointer to software pipe * @enable: true to enable QoS control * @flags: QoS control mode (enum dpu_plane_qos) */ static void _dpu_plane_set_qos_ctrl(struct drm_plane *plane, + struct dpu_sw_pipe *pipe, bool enable, u32 flags) { struct dpu_plane *pdpu = to_dpu_plane(plane); @@ -380,9 +362,9 @@ static void _dpu_plane_set_qos_ctrl(struct drm_plane *plane, memset(&pipe_qos_cfg, 0, sizeof(pipe_qos_cfg)); if (flags & DPU_PLANE_QOS_VBLANK_CTRL) { - pipe_qos_cfg.creq_vblank = pdpu->pipe_hw->cap->sblk->creq_vblank; + pipe_qos_cfg.creq_vblank = pipe->sspp->cap->sblk->creq_vblank; pipe_qos_cfg.danger_vblank = - pdpu->pipe_hw->cap->sblk->danger_vblank; + pipe->sspp->cap->sblk->danger_vblank; pipe_qos_cfg.vblank_en = enable; } @@ -408,32 +390,35 @@ static void _dpu_plane_set_qos_ctrl(struct drm_plane *plane, pipe_qos_cfg.danger_vblank, pdpu->is_rt_pipe); - pdpu->pipe_hw->ops.setup_qos_ctrl(pdpu->pipe_hw, + pipe->sspp->ops.setup_qos_ctrl(pipe->sspp, &pipe_qos_cfg); } /** * _dpu_plane_set_ot_limit - set OT limit for the given plane * @plane: Pointer to drm plane - * @crtc: Pointer to drm crtc + * @pipe: Pointer to software pipe * @pipe_cfg: Pointer to pipe configuration + * @frame_rate: CRTC's frame rate */ static void _dpu_plane_set_ot_limit(struct drm_plane *plane, - struct drm_crtc *crtc, struct dpu_hw_pipe_cfg *pipe_cfg) + struct dpu_sw_pipe *pipe, + struct dpu_sw_pipe_cfg *pipe_cfg, + int frame_rate) { struct dpu_plane *pdpu = to_dpu_plane(plane); struct dpu_vbif_set_ot_params ot_params; struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane); memset(&ot_params, 0, sizeof(ot_params)); - ot_params.xin_id = pdpu->pipe_hw->cap->xin_id; - ot_params.num = pdpu->pipe_hw->idx - SSPP_NONE; + ot_params.xin_id = pipe->sspp->cap->xin_id; + ot_params.num = pipe->sspp->idx - SSPP_NONE; ot_params.width = drm_rect_width(&pipe_cfg->src_rect); ot_params.height = drm_rect_height(&pipe_cfg->src_rect); ot_params.is_wfd = !pdpu->is_rt_pipe; - ot_params.frame_rate = drm_mode_vrefresh(&crtc->mode); + ot_params.frame_rate = frame_rate; ot_params.vbif_idx = VBIF_RT; - ot_params.clk_ctrl = pdpu->pipe_hw->cap->clk_ctrl; + ot_params.clk_ctrl = pipe->sspp->cap->clk_ctrl; ot_params.rd = true; dpu_vbif_set_ot_limit(dpu_kms, &ot_params); @@ -442,8 +427,10 @@ static void _dpu_plane_set_ot_limit(struct drm_plane *plane, /** * _dpu_plane_set_qos_remap - set vbif QoS for the given plane * @plane: Pointer to drm plane + * @pipe: Pointer to software pipe */ -static void _dpu_plane_set_qos_remap(struct drm_plane *plane) +static void _dpu_plane_set_qos_remap(struct drm_plane *plane, + struct dpu_sw_pipe *pipe) { struct dpu_plane *pdpu = to_dpu_plane(plane); struct dpu_vbif_set_qos_params qos_params; @@ -451,9 +438,9 @@ static void _dpu_plane_set_qos_remap(struct drm_plane *plane) memset(&qos_params, 0, sizeof(qos_params)); qos_params.vbif_idx = VBIF_RT; - qos_params.clk_ctrl = pdpu->pipe_hw->cap->clk_ctrl; - qos_params.xin_id = pdpu->pipe_hw->cap->xin_id; - qos_params.num = pdpu->pipe_hw->idx - SSPP_VIG0; + qos_params.clk_ctrl = pipe->sspp->cap->clk_ctrl; + qos_params.xin_id = pipe->sspp->cap->xin_id; + qos_params.num = pipe->sspp->idx - SSPP_VIG0; qos_params.is_rt = pdpu->is_rt_pipe; DPU_DEBUG_PLANE(pdpu, "pipe:%d vbif:%d xin:%d rt:%d, clk_ctrl:%d\n", @@ -465,39 +452,15 @@ static void _dpu_plane_set_qos_remap(struct drm_plane *plane) dpu_vbif_set_qos_remap(dpu_kms, &qos_params); } -static void _dpu_plane_set_scanout(struct drm_plane *plane, - struct dpu_plane_state *pstate, - struct dpu_hw_pipe_cfg *pipe_cfg, - struct drm_framebuffer *fb) -{ - struct dpu_plane *pdpu = to_dpu_plane(plane); - struct dpu_kms *kms = _dpu_plane_get_kms(&pdpu->base); - struct msm_gem_address_space *aspace = kms->base.aspace; - int ret; - - ret = dpu_format_populate_layout(aspace, fb, &pipe_cfg->layout); - if (ret == -EAGAIN) - DPU_DEBUG_PLANE(pdpu, "not updating same src addrs\n"); - else if (ret) - DPU_ERROR_PLANE(pdpu, "failed to get format layout, %d\n", ret); - else if (pdpu->pipe_hw->ops.setup_sourceaddress) { - trace_dpu_plane_set_scanout(pdpu->pipe_hw->idx, - &pipe_cfg->layout, - pstate->multirect_index); - pdpu->pipe_hw->ops.setup_sourceaddress(pdpu->pipe_hw, pipe_cfg, - pstate->multirect_index); - } -} - -static void _dpu_plane_setup_scaler3(struct dpu_plane *pdpu, - struct dpu_plane_state *pstate, +static void _dpu_plane_setup_scaler3(struct dpu_hw_sspp *pipe_hw, uint32_t src_w, uint32_t src_h, uint32_t dst_w, uint32_t dst_h, struct dpu_hw_scaler3_cfg *scale_cfg, const struct dpu_format *fmt, - uint32_t chroma_subsmpl_h, uint32_t chroma_subsmpl_v) + uint32_t chroma_subsmpl_h, uint32_t chroma_subsmpl_v, + unsigned int rotation) { uint32_t i; - bool inline_rotation = pstate->rotation & DRM_MODE_ROTATE_90; + bool inline_rotation = rotation & DRM_MODE_ROTATE_90; /* * For inline rotation cases, scaler config is post-rotation, @@ -536,7 +499,7 @@ static void _dpu_plane_setup_scaler3(struct dpu_plane *pdpu, scale_cfg->src_height[i] /= chroma_subsmpl_v; } - if (pdpu->pipe_hw->cap->features & + if (pipe_hw->cap->features & BIT(DPU_SSPP_SCALER_QSEED4)) { scale_cfg->preload_x[i] = DPU_QSEED4_DEFAULT_PRELOAD_H; scale_cfg->preload_y[i] = DPU_QSEED4_DEFAULT_PRELOAD_V; @@ -607,36 +570,28 @@ static const struct dpu_csc_cfg dpu_csc10_YUV2RGB_601L = { { 0x00, 0x3ff, 0x00, 0x3ff, 0x00, 0x3ff,}, }; -static const struct dpu_csc_cfg *_dpu_plane_get_csc(struct dpu_plane *pdpu, const struct dpu_format *fmt) +static const struct dpu_csc_cfg *_dpu_plane_get_csc(struct dpu_sw_pipe *pipe, + const struct dpu_format *fmt) { const struct dpu_csc_cfg *csc_ptr; - if (!pdpu) { - DPU_ERROR("invalid plane\n"); - return NULL; - } - if (!DPU_FORMAT_IS_YUV(fmt)) return NULL; - if (BIT(DPU_SSPP_CSC_10BIT) & pdpu->pipe_hw->cap->features) + if (BIT(DPU_SSPP_CSC_10BIT) & pipe->sspp->cap->features) csc_ptr = &dpu_csc10_YUV2RGB_601L; else csc_ptr = &dpu_csc_YUV2RGB_601L; - DPU_DEBUG_PLANE(pdpu, "using 0x%X 0x%X 0x%X...\n", - csc_ptr->csc_mv[0], - csc_ptr->csc_mv[1], - csc_ptr->csc_mv[2]); - return csc_ptr; } -static void _dpu_plane_setup_scaler(struct dpu_plane *pdpu, - struct dpu_plane_state *pstate, +static void _dpu_plane_setup_scaler(struct dpu_sw_pipe *pipe, const struct dpu_format *fmt, bool color_fill, - struct dpu_hw_pipe_cfg *pipe_cfg) + struct dpu_sw_pipe_cfg *pipe_cfg, + unsigned int rotation) { + struct dpu_hw_sspp *pipe_hw = pipe->sspp; const struct drm_format_info *info = drm_format_info(fmt->base.pixel_format); struct dpu_hw_scaler3_cfg scaler3_cfg; struct dpu_hw_pixel_ext pixel_ext; @@ -650,20 +605,21 @@ static void _dpu_plane_setup_scaler(struct dpu_plane *pdpu, /* don't chroma subsample if decimating */ /* update scaler. calculate default config for QSEED3 */ - _dpu_plane_setup_scaler3(pdpu, pstate, + _dpu_plane_setup_scaler3(pipe_hw, src_width, src_height, dst_width, dst_height, &scaler3_cfg, fmt, - info->hsub, info->vsub); + info->hsub, info->vsub, + rotation); /* configure pixel extension based on scalar config */ _dpu_plane_setup_pixel_ext(&scaler3_cfg, &pixel_ext, src_width, src_height, info->hsub, info->vsub); - if (pdpu->pipe_hw->ops.setup_pe) - pdpu->pipe_hw->ops.setup_pe(pdpu->pipe_hw, + if (pipe_hw->ops.setup_pe) + pipe_hw->ops.setup_pe(pipe_hw, &pixel_ext); /** @@ -671,11 +627,44 @@ static void _dpu_plane_setup_scaler(struct dpu_plane *pdpu, * bypassed. Still we need to update alpha and bitwidth * ONLY for RECT0 */ - if (pdpu->pipe_hw->ops.setup_scaler && - pstate->multirect_index != DPU_SSPP_RECT_1) - pdpu->pipe_hw->ops.setup_scaler(pdpu->pipe_hw, - pipe_cfg, - &scaler3_cfg); + if (pipe_hw->ops.setup_scaler && + pipe->multirect_index != DPU_SSPP_RECT_1) + pipe_hw->ops.setup_scaler(pipe_hw, + &scaler3_cfg, + fmt); +} + +static void _dpu_plane_color_fill_pipe(struct dpu_plane_state *pstate, + struct dpu_sw_pipe *pipe, + struct drm_rect *dst_rect, + u32 fill_color, + const struct dpu_format *fmt) +{ + struct dpu_sw_pipe_cfg pipe_cfg; + + /* update sspp */ + if (!pipe->sspp->ops.setup_solidfill) + return; + + pipe->sspp->ops.setup_solidfill(pipe, fill_color); + + /* override scaler/decimation if solid fill */ + pipe_cfg.dst_rect = *dst_rect; + + pipe_cfg.src_rect.x1 = 0; + pipe_cfg.src_rect.y1 = 0; + pipe_cfg.src_rect.x2 = + drm_rect_width(&pipe_cfg.dst_rect); + pipe_cfg.src_rect.y2 = + drm_rect_height(&pipe_cfg.dst_rect); + + if (pipe->sspp->ops.setup_format) + pipe->sspp->ops.setup_format(pipe, fmt, DPU_SSPP_SOLID_FILL); + + if (pipe->sspp->ops.setup_rects) + pipe->sspp->ops.setup_rects(pipe, &pipe_cfg); + + _dpu_plane_setup_scaler(pipe, fmt, true, &pipe_cfg, pstate->rotation); } /** @@ -683,15 +672,14 @@ static void _dpu_plane_setup_scaler(struct dpu_plane *pdpu, * @pdpu: Pointer to DPU plane object * @color: RGB fill color value, [23..16] Blue, [15..8] Green, [7..0] Red * @alpha: 8-bit fill alpha value, 255 selects 100% alpha - * Returns: 0 on success */ -static int _dpu_plane_color_fill(struct dpu_plane *pdpu, +static void _dpu_plane_color_fill(struct dpu_plane *pdpu, uint32_t color, uint32_t alpha) { const struct dpu_format *fmt; const struct drm_plane *plane = &pdpu->base; struct dpu_plane_state *pstate = to_dpu_plane_state(plane->state); - struct dpu_hw_pipe_cfg pipe_cfg; + u32 fill_color = (color & 0xFFFFFF) | ((alpha & 0xFF) << 24); DPU_DEBUG_PLANE(pdpu, "\n"); @@ -700,156 +688,17 @@ static int _dpu_plane_color_fill(struct dpu_plane *pdpu, * h/w only supports RGB variants */ fmt = dpu_get_dpu_format(DRM_FORMAT_ABGR8888); + /* should not happen ever */ + if (!fmt) + return; /* update sspp */ - if (fmt && pdpu->pipe_hw->ops.setup_solidfill) { - pdpu->pipe_hw->ops.setup_solidfill(pdpu->pipe_hw, - (color & 0xFFFFFF) | ((alpha & 0xFF) << 24), - pstate->multirect_index); - - /* override scaler/decimation if solid fill */ - pipe_cfg.dst_rect = pstate->base.dst; - - pipe_cfg.src_rect.x1 = 0; - pipe_cfg.src_rect.y1 = 0; - pipe_cfg.src_rect.x2 = - drm_rect_width(&pipe_cfg.dst_rect); - pipe_cfg.src_rect.y2 = - drm_rect_height(&pipe_cfg.dst_rect); - - if (pdpu->pipe_hw->ops.setup_format) - pdpu->pipe_hw->ops.setup_format(pdpu->pipe_hw, - fmt, DPU_SSPP_SOLID_FILL, - pstate->multirect_index); - - if (pdpu->pipe_hw->ops.setup_rects) - pdpu->pipe_hw->ops.setup_rects(pdpu->pipe_hw, - &pipe_cfg, - pstate->multirect_index); - - _dpu_plane_setup_scaler(pdpu, pstate, fmt, true, &pipe_cfg); - } - - return 0; -} - -void dpu_plane_clear_multirect(const struct drm_plane_state *drm_state) -{ - struct dpu_plane_state *pstate = to_dpu_plane_state(drm_state); - - pstate->multirect_index = DPU_SSPP_RECT_SOLO; - pstate->multirect_mode = DPU_SSPP_MULTIRECT_NONE; -} - -int dpu_plane_validate_multirect_v2(struct dpu_multirect_plane_states *plane) -{ - struct dpu_plane_state *pstate[R_MAX]; - const struct drm_plane_state *drm_state[R_MAX]; - struct drm_rect src[R_MAX], dst[R_MAX]; - struct dpu_plane *dpu_plane[R_MAX]; - const struct dpu_format *fmt[R_MAX]; - int i, buffer_lines; - unsigned int max_tile_height = 1; - bool parallel_fetch_qualified = true; - bool has_tiled_rect = false; - - for (i = 0; i < R_MAX; i++) { - const struct msm_format *msm_fmt; - - drm_state[i] = i ? plane->r1 : plane->r0; - msm_fmt = msm_framebuffer_format(drm_state[i]->fb); - fmt[i] = to_dpu_format(msm_fmt); - - if (DPU_FORMAT_IS_UBWC(fmt[i])) { - has_tiled_rect = true; - if (fmt[i]->tile_height > max_tile_height) - max_tile_height = fmt[i]->tile_height; - } - } - - for (i = 0; i < R_MAX; i++) { - int width_threshold; - - pstate[i] = to_dpu_plane_state(drm_state[i]); - dpu_plane[i] = to_dpu_plane(drm_state[i]->plane); - - if (pstate[i] == NULL) { - DPU_ERROR("DPU plane state of plane id %d is NULL\n", - drm_state[i]->plane->base.id); - return -EINVAL; - } - - src[i].x1 = drm_state[i]->src_x >> 16; - src[i].y1 = drm_state[i]->src_y >> 16; - src[i].x2 = src[i].x1 + (drm_state[i]->src_w >> 16); - src[i].y2 = src[i].y1 + (drm_state[i]->src_h >> 16); - - dst[i] = drm_plane_state_dest(drm_state[i]); - - if (drm_rect_calc_hscale(&src[i], &dst[i], 1, 1) != 1 || - drm_rect_calc_vscale(&src[i], &dst[i], 1, 1) != 1) { - DPU_ERROR_PLANE(dpu_plane[i], - "scaling is not supported in multirect mode\n"); - return -EINVAL; - } - - if (DPU_FORMAT_IS_YUV(fmt[i])) { - DPU_ERROR_PLANE(dpu_plane[i], - "Unsupported format for multirect mode\n"); - return -EINVAL; - } - - /** - * SSPP PD_MEM is split half - one for each RECT. - * Tiled formats need 5 lines of buffering while fetching - * whereas linear formats need only 2 lines. - * So we cannot support more than half of the supported SSPP - * width for tiled formats. - */ - width_threshold = dpu_plane[i]->catalog->caps->max_linewidth; - if (has_tiled_rect) - width_threshold /= 2; - - if (parallel_fetch_qualified && - drm_rect_width(&src[i]) > width_threshold) - parallel_fetch_qualified = false; - - } - - /* Validate RECT's and set the mode */ - - /* Prefer PARALLEL FETCH Mode over TIME_MX Mode */ - if (parallel_fetch_qualified) { - pstate[R0]->multirect_mode = DPU_SSPP_MULTIRECT_PARALLEL; - pstate[R1]->multirect_mode = DPU_SSPP_MULTIRECT_PARALLEL; - - goto done; - } - - /* TIME_MX Mode */ - buffer_lines = 2 * max_tile_height; + _dpu_plane_color_fill_pipe(pstate, &pstate->pipe, &pstate->pipe_cfg.dst_rect, + fill_color, fmt); - if (dst[R1].y1 >= dst[R0].y2 + buffer_lines || - dst[R0].y1 >= dst[R1].y2 + buffer_lines) { - pstate[R0]->multirect_mode = DPU_SSPP_MULTIRECT_TIME_MX; - pstate[R1]->multirect_mode = DPU_SSPP_MULTIRECT_TIME_MX; - } else { - DPU_ERROR( - "No multirect mode possible for the planes (%d - %d)\n", - drm_state[R0]->plane->base.id, - drm_state[R1]->plane->base.id); - return -EINVAL; - } - -done: - pstate[R0]->multirect_index = DPU_SSPP_RECT_0; - pstate[R1]->multirect_index = DPU_SSPP_RECT_1; - - DPU_DEBUG_PLANE(dpu_plane[R0], "R0: %d - %d\n", - pstate[R0]->multirect_mode, pstate[R0]->multirect_index); - DPU_DEBUG_PLANE(dpu_plane[R1], "R1: %d - %d\n", - pstate[R1]->multirect_mode, pstate[R1]->multirect_index); - return 0; + if (pstate->r_pipe.sspp) + _dpu_plane_color_fill_pipe(pstate, &pstate->r_pipe, &pstate->r_pipe_cfg.dst_rect, + fill_color, fmt); } static int dpu_plane_prepare_fb(struct drm_plane *plane, @@ -914,25 +763,6 @@ static void dpu_plane_cleanup_fb(struct drm_plane *plane, old_pstate->needs_dirtyfb); } -static bool dpu_plane_validate_src(struct drm_rect *src, - struct drm_rect *fb_rect, - uint32_t min_src_size) -{ - /* Ensure fb size is supported */ - if (drm_rect_width(fb_rect) > MAX_IMG_WIDTH || - drm_rect_height(fb_rect) > MAX_IMG_HEIGHT) - return false; - - /* Ensure src rect is above the minimum size */ - if (drm_rect_width(src) < min_src_size || - drm_rect_height(src) < min_src_size) - return false; - - /* Ensure src is fully encapsulated in fb */ - return drm_rect_intersect(fb_rect, src) && - drm_rect_equals(fb_rect, src); -} - static int dpu_plane_check_inline_rotation(struct dpu_plane *pdpu, const struct dpu_sspp_sub_blks *sblk, struct drm_rect src, const struct dpu_format *fmt) @@ -961,6 +791,53 @@ static int dpu_plane_check_inline_rotation(struct dpu_plane *pdpu, return 0; } +static int dpu_plane_atomic_check_pipe(struct dpu_plane *pdpu, + struct dpu_sw_pipe *pipe, + struct dpu_sw_pipe_cfg *pipe_cfg, + const struct dpu_format *fmt) +{ + uint32_t min_src_size; + + min_src_size = DPU_FORMAT_IS_YUV(fmt) ? 2 : 1; + + if (DPU_FORMAT_IS_YUV(fmt) && + (!(pipe->sspp->cap->features & DPU_SSPP_SCALER) || + !(pipe->sspp->cap->features & DPU_SSPP_CSC_ANY))) { + DPU_DEBUG_PLANE(pdpu, + "plane doesn't have scaler/csc for yuv\n"); + return -EINVAL; + } + + /* check src bounds */ + if (drm_rect_width(&pipe_cfg->src_rect) < min_src_size || + drm_rect_height(&pipe_cfg->src_rect) < min_src_size) { + DPU_DEBUG_PLANE(pdpu, "invalid source " DRM_RECT_FMT "\n", + DRM_RECT_ARG(&pipe_cfg->src_rect)); + return -E2BIG; + } + + /* valid yuv image */ + if (DPU_FORMAT_IS_YUV(fmt) && + (pipe_cfg->src_rect.x1 & 0x1 || + pipe_cfg->src_rect.y1 & 0x1 || + drm_rect_width(&pipe_cfg->src_rect) & 0x1 || + drm_rect_height(&pipe_cfg->src_rect) & 0x1)) { + DPU_DEBUG_PLANE(pdpu, "invalid yuv source " DRM_RECT_FMT "\n", + DRM_RECT_ARG(&pipe_cfg->src_rect)); + return -EINVAL; + } + + /* min dst support */ + if (drm_rect_width(&pipe_cfg->dst_rect) < 0x1 || + drm_rect_height(&pipe_cfg->dst_rect) < 0x1) { + DPU_DEBUG_PLANE(pdpu, "invalid dest rect " DRM_RECT_FMT "\n", + DRM_RECT_ARG(&pipe_cfg->dst_rect)); + return -EINVAL; + } + + return 0; +} + static int dpu_plane_atomic_check(struct drm_plane *plane, struct drm_atomic_state *state) { @@ -969,14 +846,18 @@ static int dpu_plane_atomic_check(struct drm_plane *plane, int ret = 0, min_scale; struct dpu_plane *pdpu = to_dpu_plane(plane); struct dpu_plane_state *pstate = to_dpu_plane_state(new_plane_state); + struct dpu_sw_pipe *pipe = &pstate->pipe; + struct dpu_sw_pipe *r_pipe = &pstate->r_pipe; const struct drm_crtc_state *crtc_state = NULL; const struct dpu_format *fmt; - struct drm_rect src, dst, fb_rect = { 0 }; - uint32_t min_src_size, max_linewidth; + struct dpu_sw_pipe_cfg *pipe_cfg = &pstate->pipe_cfg; + struct dpu_sw_pipe_cfg *r_pipe_cfg = &pstate->r_pipe_cfg; + struct drm_rect fb_rect = { 0 }; + uint32_t max_linewidth; unsigned int rotation; uint32_t supported_rotations; - const struct dpu_sspp_cfg *pipe_hw_caps = pdpu->pipe_hw->cap; - const struct dpu_sspp_sub_blks *sblk = pdpu->pipe_hw->cap->sblk; + const struct dpu_sspp_cfg *pipe_hw_caps = pstate->pipe.sspp->cap; + const struct dpu_sspp_sub_blks *sblk = pstate->pipe.sspp->cap->sblk; if (new_plane_state->crtc) crtc_state = drm_atomic_get_new_crtc_state(state, @@ -994,55 +875,99 @@ static int dpu_plane_atomic_check(struct drm_plane *plane, if (!new_plane_state->visible) return 0; - src.x1 = new_plane_state->src_x >> 16; - src.y1 = new_plane_state->src_y >> 16; - src.x2 = src.x1 + (new_plane_state->src_w >> 16); - src.y2 = src.y1 + (new_plane_state->src_h >> 16); + pipe->multirect_index = DPU_SSPP_RECT_SOLO; + pipe->multirect_mode = DPU_SSPP_MULTIRECT_NONE; + r_pipe->multirect_index = DPU_SSPP_RECT_SOLO; + r_pipe->multirect_mode = DPU_SSPP_MULTIRECT_NONE; + r_pipe->sspp = NULL; + + pstate->stage = DPU_STAGE_0 + pstate->base.normalized_zpos; + if (pstate->stage >= pdpu->catalog->caps->max_mixer_blendstages) { + DPU_ERROR("> %d plane stages assigned\n", + pdpu->catalog->caps->max_mixer_blendstages - DPU_STAGE_0); + return -EINVAL; + } + + pipe_cfg->src_rect = new_plane_state->src; + + /* state->src is 16.16, src_rect is not */ + pipe_cfg->src_rect.x1 >>= 16; + pipe_cfg->src_rect.x2 >>= 16; + pipe_cfg->src_rect.y1 >>= 16; + pipe_cfg->src_rect.y2 >>= 16; - dst = drm_plane_state_dest(new_plane_state); + pipe_cfg->dst_rect = new_plane_state->dst; fb_rect.x2 = new_plane_state->fb->width; fb_rect.y2 = new_plane_state->fb->height; - max_linewidth = pdpu->catalog->caps->max_linewidth; + /* Ensure fb size is supported */ + if (drm_rect_width(&fb_rect) > MAX_IMG_WIDTH || + drm_rect_height(&fb_rect) > MAX_IMG_HEIGHT) { + DPU_DEBUG_PLANE(pdpu, "invalid framebuffer " DRM_RECT_FMT "\n", + DRM_RECT_ARG(&fb_rect)); + return -E2BIG; + } fmt = to_dpu_format(msm_framebuffer_format(new_plane_state->fb)); - min_src_size = DPU_FORMAT_IS_YUV(fmt) ? 2 : 1; + max_linewidth = pdpu->catalog->caps->max_linewidth; - if (DPU_FORMAT_IS_YUV(fmt) && - (!(pipe_hw_caps->features & DPU_SSPP_SCALER) || - !(pipe_hw_caps->features & DPU_SSPP_CSC_ANY))) { - DPU_DEBUG_PLANE(pdpu, - "plane doesn't have scaler/csc for yuv\n"); - return -EINVAL; + if (drm_rect_width(&pipe_cfg->src_rect) > max_linewidth) { + /* + * In parallel multirect case only the half of the usual width + * is supported for tiled formats. If we are here, we know that + * full width is more than max_linewidth, thus each rect is + * wider than allowed. + */ + if (DPU_FORMAT_IS_UBWC(fmt)) { + DPU_DEBUG_PLANE(pdpu, "invalid src " DRM_RECT_FMT " line:%u, tiled format\n", + DRM_RECT_ARG(&pipe_cfg->src_rect), max_linewidth); + return -E2BIG; + } - /* check src bounds */ - } else if (!dpu_plane_validate_src(&src, &fb_rect, min_src_size)) { - DPU_DEBUG_PLANE(pdpu, "invalid source " DRM_RECT_FMT "\n", - DRM_RECT_ARG(&src)); - return -E2BIG; + if (drm_rect_width(&pipe_cfg->src_rect) > 2 * max_linewidth) { + DPU_DEBUG_PLANE(pdpu, "invalid src " DRM_RECT_FMT " line:%u\n", + DRM_RECT_ARG(&pipe_cfg->src_rect), max_linewidth); + return -E2BIG; + } - /* valid yuv image */ - } else if (DPU_FORMAT_IS_YUV(fmt) && - (src.x1 & 0x1 || src.y1 & 0x1 || - drm_rect_width(&src) & 0x1 || - drm_rect_height(&src) & 0x1)) { - DPU_DEBUG_PLANE(pdpu, "invalid yuv source " DRM_RECT_FMT "\n", - DRM_RECT_ARG(&src)); - return -EINVAL; + if (drm_rect_width(&pipe_cfg->src_rect) != drm_rect_width(&pipe_cfg->dst_rect) || + drm_rect_height(&pipe_cfg->src_rect) != drm_rect_height(&pipe_cfg->dst_rect) || + (!test_bit(DPU_SSPP_SMART_DMA_V1, &pipe->sspp->cap->features) && + !test_bit(DPU_SSPP_SMART_DMA_V2, &pipe->sspp->cap->features)) || + DPU_FORMAT_IS_YUV(fmt)) { + DPU_DEBUG_PLANE(pdpu, "invalid src " DRM_RECT_FMT " line:%u, can't use split source\n", + DRM_RECT_ARG(&pipe_cfg->src_rect), max_linewidth); + return -E2BIG; + } - /* min dst support */ - } else if (drm_rect_width(&dst) < 0x1 || drm_rect_height(&dst) < 0x1) { - DPU_DEBUG_PLANE(pdpu, "invalid dest rect " DRM_RECT_FMT "\n", - DRM_RECT_ARG(&dst)); - return -EINVAL; + /* + * Use multirect for wide plane. We do not support dynamic + * assignment of SSPPs, so we know the configuration. + */ + pipe->multirect_index = DPU_SSPP_RECT_0; + pipe->multirect_mode = DPU_SSPP_MULTIRECT_PARALLEL; + + r_pipe->sspp = pipe->sspp; + r_pipe->multirect_index = DPU_SSPP_RECT_1; + r_pipe->multirect_mode = DPU_SSPP_MULTIRECT_PARALLEL; + + *r_pipe_cfg = *pipe_cfg; + pipe_cfg->src_rect.x2 = (pipe_cfg->src_rect.x1 + pipe_cfg->src_rect.x2) >> 1; + pipe_cfg->dst_rect.x2 = (pipe_cfg->dst_rect.x1 + pipe_cfg->dst_rect.x2) >> 1; + r_pipe_cfg->src_rect.x1 = pipe_cfg->src_rect.x2; + r_pipe_cfg->dst_rect.x1 = pipe_cfg->dst_rect.x2; + } - /* check decimated source width */ - } else if (drm_rect_width(&src) > max_linewidth) { - DPU_DEBUG_PLANE(pdpu, "invalid src " DRM_RECT_FMT " line:%u\n", - DRM_RECT_ARG(&src), max_linewidth); - return -E2BIG; + ret = dpu_plane_atomic_check_pipe(pdpu, pipe, pipe_cfg, fmt); + if (ret) + return ret; + + if (r_pipe->sspp) { + ret = dpu_plane_atomic_check_pipe(pdpu, r_pipe, r_pipe_cfg, fmt); + if (ret) + return ret; } supported_rotations = DRM_MODE_REFLECT_MASK | DRM_MODE_ROTATE_0; @@ -1055,7 +980,7 @@ static int dpu_plane_atomic_check(struct drm_plane *plane, if ((pipe_hw_caps->features & BIT(DPU_SSPP_INLINE_ROTATION)) && (rotation & DRM_MODE_ROTATE_90)) { - ret = dpu_plane_check_inline_rotation(pdpu, sblk, src, fmt); + ret = dpu_plane_check_inline_rotation(pdpu, sblk, pipe_cfg->src_rect, fmt); if (ret) return ret; } @@ -1066,6 +991,28 @@ static int dpu_plane_atomic_check(struct drm_plane *plane, return 0; } +static void dpu_plane_flush_csc(struct dpu_plane *pdpu, struct dpu_sw_pipe *pipe) +{ + const struct dpu_format *format = + to_dpu_format(msm_framebuffer_format(pdpu->base.state->fb)); + const struct dpu_csc_cfg *csc_ptr; + + if (!pipe->sspp || !pipe->sspp->ops.setup_csc) + return; + + csc_ptr = _dpu_plane_get_csc(pipe, format); + if (!csc_ptr) + return; + + DPU_DEBUG_PLANE(pdpu, "using 0x%X 0x%X 0x%X...\n", + csc_ptr->csc_mv[0], + csc_ptr->csc_mv[1], + csc_ptr->csc_mv[2]); + + pipe->sspp->ops.setup_csc(pipe->sspp, csc_ptr); + +} + void dpu_plane_flush(struct drm_plane *plane) { struct dpu_plane *pdpu; @@ -1089,12 +1036,9 @@ void dpu_plane_flush(struct drm_plane *plane) else if (pdpu->color_fill & DPU_PLANE_COLOR_FILL_FLAG) /* force 100% alpha */ _dpu_plane_color_fill(pdpu, pdpu->color_fill, 0xFF); - else if (pdpu->pipe_hw && pdpu->pipe_hw->ops.setup_csc) { - const struct dpu_format *fmt = to_dpu_format(msm_framebuffer_format(plane->state->fb)); - const struct dpu_csc_cfg *csc_ptr = _dpu_plane_get_csc(pdpu, fmt); - - if (csc_ptr) - pdpu->pipe_hw->ops.setup_csc(pdpu->pipe_hw, csc_ptr); + else { + dpu_plane_flush_csc(pdpu, &pstate->pipe); + dpu_plane_flush_csc(pdpu, &pstate->r_pipe); } /* flag h/w flush complete */ @@ -1118,45 +1062,24 @@ void dpu_plane_set_error(struct drm_plane *plane, bool error) pdpu->is_error = error; } -static void dpu_plane_sspp_atomic_update(struct drm_plane *plane) +static void dpu_plane_sspp_update_pipe(struct drm_plane *plane, + struct dpu_sw_pipe *pipe, + struct dpu_sw_pipe_cfg *pipe_cfg, + const struct dpu_format *fmt, + int frame_rate, + struct dpu_hw_fmt_layout *layout) { uint32_t src_flags; struct dpu_plane *pdpu = to_dpu_plane(plane); struct drm_plane_state *state = plane->state; struct dpu_plane_state *pstate = to_dpu_plane_state(state); - struct drm_crtc *crtc = state->crtc; - struct drm_framebuffer *fb = state->fb; - bool is_rt_pipe; - const struct dpu_format *fmt = - to_dpu_format(msm_framebuffer_format(fb)); - struct dpu_hw_pipe_cfg pipe_cfg; - - memset(&pipe_cfg, 0, sizeof(struct dpu_hw_pipe_cfg)); - _dpu_plane_set_scanout(plane, pstate, &pipe_cfg, fb); - - pstate->pending = true; - - is_rt_pipe = (dpu_crtc_get_client_type(crtc) != NRT_CLIENT); - pstate->needs_qos_remap |= (is_rt_pipe != pdpu->is_rt_pipe); - pdpu->is_rt_pipe = is_rt_pipe; - - _dpu_plane_set_qos_ctrl(plane, false, DPU_PLANE_QOS_PANIC_CTRL); - - DPU_DEBUG_PLANE(pdpu, "FB[%u] " DRM_RECT_FP_FMT "->crtc%u " DRM_RECT_FMT - ", %4.4s ubwc %d\n", fb->base.id, DRM_RECT_FP_ARG(&state->src), - crtc->base.id, DRM_RECT_ARG(&state->dst), - (char *)&fmt->base.pixel_format, DPU_FORMAT_IS_UBWC(fmt)); - - pipe_cfg.src_rect = state->src; - - /* state->src is 16.16, src_rect is not */ - pipe_cfg.src_rect.x1 >>= 16; - pipe_cfg.src_rect.x2 >>= 16; - pipe_cfg.src_rect.y1 >>= 16; - pipe_cfg.src_rect.y2 >>= 16; + if (layout && pipe->sspp->ops.setup_sourceaddress) { + trace_dpu_plane_set_scanout(pipe, layout); + pipe->sspp->ops.setup_sourceaddress(pipe, layout); + } - pipe_cfg.dst_rect = state->dst; + _dpu_plane_set_qos_ctrl(plane, pipe, false, DPU_PLANE_QOS_PANIC_CTRL); /* override for color fill */ if (pdpu->color_fill & DPU_PLANE_COLOR_FILL_FLAG) { @@ -1164,21 +1087,18 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane) return; } - if (pdpu->pipe_hw->ops.setup_rects) { - pdpu->pipe_hw->ops.setup_rects(pdpu->pipe_hw, - &pipe_cfg, - pstate->multirect_index); + if (pipe->sspp->ops.setup_rects) { + pipe->sspp->ops.setup_rects(pipe, + pipe_cfg); } - _dpu_plane_setup_scaler(pdpu, pstate, fmt, false, &pipe_cfg); + _dpu_plane_setup_scaler(pipe, fmt, false, pipe_cfg, pstate->rotation); - if (pdpu->pipe_hw->ops.setup_multirect) - pdpu->pipe_hw->ops.setup_multirect( - pdpu->pipe_hw, - pstate->multirect_index, - pstate->multirect_mode); + if (pipe->sspp->ops.setup_multirect) + pipe->sspp->ops.setup_multirect( + pipe); - if (pdpu->pipe_hw->ops.setup_format) { + if (pipe->sspp->ops.setup_format) { unsigned int rotation = pstate->rotation; src_flags = 0x0; @@ -1193,10 +1113,9 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane) src_flags |= DPU_SSPP_ROT_90; /* update format */ - pdpu->pipe_hw->ops.setup_format(pdpu->pipe_hw, fmt, src_flags, - pstate->multirect_index); + pipe->sspp->ops.setup_format(pipe, fmt, src_flags); - if (pdpu->pipe_hw->ops.setup_cdp) { + if (pipe->sspp->ops.setup_cdp) { struct dpu_hw_cdp_cfg cdp_cfg; memset(&cdp_cfg, 0, sizeof(struct dpu_hw_cdp_cfg)); @@ -1210,35 +1129,100 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane) DPU_FORMAT_IS_TILE(fmt); cdp_cfg.preload_ahead = DPU_SSPP_CDP_PRELOAD_AHEAD_64; - pdpu->pipe_hw->ops.setup_cdp(pdpu->pipe_hw, &cdp_cfg, pstate->multirect_index); + pipe->sspp->ops.setup_cdp(pipe, &cdp_cfg); } } - _dpu_plane_set_qos_lut(plane, fb, &pipe_cfg); - _dpu_plane_set_danger_lut(plane, fb); + _dpu_plane_set_qos_lut(plane, pipe, fmt, pipe_cfg); + _dpu_plane_set_danger_lut(plane, pipe, fmt); if (plane->type != DRM_PLANE_TYPE_CURSOR) { - _dpu_plane_set_qos_ctrl(plane, true, DPU_PLANE_QOS_PANIC_CTRL); - _dpu_plane_set_ot_limit(plane, crtc, &pipe_cfg); + _dpu_plane_set_qos_ctrl(plane, pipe, true, DPU_PLANE_QOS_PANIC_CTRL); + _dpu_plane_set_ot_limit(plane, pipe, pipe_cfg, frame_rate); } - if (pstate->needs_qos_remap) { - pstate->needs_qos_remap = false; - _dpu_plane_set_qos_remap(plane); + if (pstate->needs_qos_remap) + _dpu_plane_set_qos_remap(plane, pipe); +} + +static void dpu_plane_sspp_atomic_update(struct drm_plane *plane) +{ + struct dpu_plane *pdpu = to_dpu_plane(plane); + struct drm_plane_state *state = plane->state; + struct dpu_plane_state *pstate = to_dpu_plane_state(state); + struct dpu_sw_pipe *pipe = &pstate->pipe; + struct dpu_sw_pipe *r_pipe = &pstate->r_pipe; + struct drm_crtc *crtc = state->crtc; + struct drm_framebuffer *fb = state->fb; + bool is_rt_pipe; + const struct dpu_format *fmt = + to_dpu_format(msm_framebuffer_format(fb)); + struct dpu_sw_pipe_cfg *pipe_cfg = &pstate->pipe_cfg; + struct dpu_sw_pipe_cfg *r_pipe_cfg = &pstate->r_pipe_cfg; + struct dpu_kms *kms = _dpu_plane_get_kms(&pdpu->base); + struct msm_gem_address_space *aspace = kms->base.aspace; + struct dpu_hw_fmt_layout layout; + bool layout_valid = false; + int ret; + + ret = dpu_format_populate_layout(aspace, fb, &layout); + if (ret) + DPU_ERROR_PLANE(pdpu, "failed to get format layout, %d\n", ret); + else + layout_valid = true; + + pstate->pending = true; + + is_rt_pipe = (dpu_crtc_get_client_type(crtc) != NRT_CLIENT); + pstate->needs_qos_remap |= (is_rt_pipe != pdpu->is_rt_pipe); + pdpu->is_rt_pipe = is_rt_pipe; + + DPU_DEBUG_PLANE(pdpu, "FB[%u] " DRM_RECT_FP_FMT "->crtc%u " DRM_RECT_FMT + ", %4.4s ubwc %d\n", fb->base.id, DRM_RECT_FP_ARG(&state->src), + crtc->base.id, DRM_RECT_ARG(&state->dst), + (char *)&fmt->base.pixel_format, DPU_FORMAT_IS_UBWC(fmt)); + + dpu_plane_sspp_update_pipe(plane, pipe, pipe_cfg, fmt, + drm_mode_vrefresh(&crtc->mode), + layout_valid ? &layout : NULL); + + if (r_pipe->sspp) { + dpu_plane_sspp_update_pipe(plane, r_pipe, r_pipe_cfg, fmt, + drm_mode_vrefresh(&crtc->mode), + layout_valid ? &layout : NULL); } - _dpu_plane_calc_bw(plane, fb, &pipe_cfg); + if (pstate->needs_qos_remap) + pstate->needs_qos_remap = false; + + pstate->plane_fetch_bw = _dpu_plane_calc_bw(pdpu->catalog, fmt, + &crtc->mode, pipe_cfg); + + pstate->plane_clk = _dpu_plane_calc_clk(&crtc->mode, pipe_cfg); - _dpu_plane_calc_clk(plane, &pipe_cfg); + if (r_pipe->sspp) { + pstate->plane_fetch_bw += _dpu_plane_calc_bw(pdpu->catalog, fmt, &crtc->mode, r_pipe_cfg); + + pstate->plane_clk = max(pstate->plane_clk, _dpu_plane_calc_clk(&crtc->mode, r_pipe_cfg)); + } } static void _dpu_plane_atomic_disable(struct drm_plane *plane) { struct drm_plane_state *state = plane->state; struct dpu_plane_state *pstate = to_dpu_plane_state(state); + struct dpu_sw_pipe *r_pipe = &pstate->r_pipe; trace_dpu_plane_disable(DRMID(plane), false, - pstate->multirect_mode); + pstate->pipe.multirect_mode); + + if (r_pipe->sspp) { + r_pipe->multirect_index = DPU_SSPP_RECT_SOLO; + r_pipe->multirect_mode = DPU_SSPP_MULTIRECT_NONE; + + if (r_pipe->sspp->ops.setup_multirect) + r_pipe->sspp->ops.setup_multirect(r_pipe); + } pstate->pending = true; } @@ -1264,19 +1248,22 @@ static void dpu_plane_atomic_update(struct drm_plane *plane, static void dpu_plane_destroy(struct drm_plane *plane) { struct dpu_plane *pdpu = plane ? to_dpu_plane(plane) : NULL; + struct dpu_plane_state *pstate; DPU_DEBUG_PLANE(pdpu, "\n"); if (pdpu) { - _dpu_plane_set_qos_ctrl(plane, false, DPU_PLANE_QOS_PANIC_CTRL); + pstate = to_dpu_plane_state(plane->state); + _dpu_plane_set_qos_ctrl(plane, &pstate->pipe, false, DPU_PLANE_QOS_PANIC_CTRL); + + if (pstate->r_pipe.sspp) + _dpu_plane_set_qos_ctrl(plane, &pstate->r_pipe, false, DPU_PLANE_QOS_PANIC_CTRL); mutex_destroy(&pdpu->lock); /* this will destroy the states as well */ drm_plane_cleanup(plane); - dpu_hw_sspp_destroy(pdpu->pipe_hw); - kfree(pdpu); } } @@ -1352,18 +1339,36 @@ static void dpu_plane_atomic_print_state(struct drm_printer *p, const struct drm_plane_state *state) { const struct dpu_plane_state *pstate = to_dpu_plane_state(state); - const struct dpu_plane *pdpu = to_dpu_plane(state->plane); + const struct dpu_sw_pipe *pipe = &pstate->pipe; + const struct dpu_sw_pipe_cfg *pipe_cfg = &pstate->pipe_cfg; + const struct dpu_sw_pipe *r_pipe = &pstate->r_pipe; + const struct dpu_sw_pipe_cfg *r_pipe_cfg = &pstate->r_pipe_cfg; drm_printf(p, "\tstage=%d\n", pstate->stage); - drm_printf(p, "\tsspp=%s\n", pdpu->pipe_hw->cap->name); - drm_printf(p, "\tmultirect_mode=%s\n", dpu_get_multirect_mode(pstate->multirect_mode)); - drm_printf(p, "\tmultirect_index=%s\n", dpu_get_multirect_index(pstate->multirect_index)); + + drm_printf(p, "\tsspp[0]=%s\n", pipe->sspp->cap->name); + drm_printf(p, "\tmultirect_mode[0]=%s\n", dpu_get_multirect_mode(pipe->multirect_mode)); + drm_printf(p, "\tmultirect_index[0]=%s\n", + dpu_get_multirect_index(pipe->multirect_index)); + drm_printf(p, "\tsrc[0]=" DRM_RECT_FMT "\n", DRM_RECT_ARG(&pipe_cfg->src_rect)); + drm_printf(p, "\tdst[0]=" DRM_RECT_FMT "\n", DRM_RECT_ARG(&pipe_cfg->dst_rect)); + + if (r_pipe->sspp) { + drm_printf(p, "\tsspp[1]=%s\n", r_pipe->sspp->cap->name); + drm_printf(p, "\tmultirect_mode[1]=%s\n", + dpu_get_multirect_mode(r_pipe->multirect_mode)); + drm_printf(p, "\tmultirect_index[1]=%s\n", + dpu_get_multirect_index(r_pipe->multirect_index)); + drm_printf(p, "\tsrc[1]=" DRM_RECT_FMT "\n", DRM_RECT_ARG(&r_pipe_cfg->src_rect)); + drm_printf(p, "\tdst[1]=" DRM_RECT_FMT "\n", DRM_RECT_ARG(&r_pipe_cfg->dst_rect)); + } } static void dpu_plane_reset(struct drm_plane *plane) { struct dpu_plane *pdpu; struct dpu_plane_state *pstate; + struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane); if (!plane) { DPU_ERROR("invalid plane\n"); @@ -1385,6 +1390,16 @@ static void dpu_plane_reset(struct drm_plane *plane) return; } + /* + * Set the SSPP here until we have proper virtualized DPU planes. + * This is the place where the state is allocated, so fill it fully. + */ + pstate->pipe.sspp = dpu_rm_get_sspp(&dpu_kms->rm, pdpu->pipe); + pstate->pipe.multirect_index = DPU_SSPP_RECT_SOLO; + pstate->pipe.multirect_mode = DPU_SSPP_MULTIRECT_NONE; + + pstate->r_pipe.sspp = NULL; + __drm_atomic_helper_plane_reset(plane, &pstate->base); } @@ -1392,31 +1407,18 @@ static void dpu_plane_reset(struct drm_plane *plane) void dpu_plane_danger_signal_ctrl(struct drm_plane *plane, bool enable) { struct dpu_plane *pdpu = to_dpu_plane(plane); + struct dpu_plane_state *pstate = to_dpu_plane_state(plane->state); struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane); if (!pdpu->is_rt_pipe) return; pm_runtime_get_sync(&dpu_kms->pdev->dev); - _dpu_plane_set_qos_ctrl(plane, enable, DPU_PLANE_QOS_PANIC_CTRL); + _dpu_plane_set_qos_ctrl(plane, &pstate->pipe, enable, DPU_PLANE_QOS_PANIC_CTRL); + if (pstate->r_pipe.sspp) + _dpu_plane_set_qos_ctrl(plane, &pstate->r_pipe, enable, DPU_PLANE_QOS_PANIC_CTRL); pm_runtime_put_sync(&dpu_kms->pdev->dev); } - -/* SSPP live inside dpu_plane private data only. Enumerate them here. */ -void dpu_debugfs_sspp_init(struct dpu_kms *dpu_kms, struct dentry *debugfs_root) -{ - struct drm_plane *plane; - struct dentry *entry = debugfs_create_dir("sspp", debugfs_root); - - if (IS_ERR(entry)) - return; - - drm_for_each_plane(plane, dpu_kms->dev) { - struct dpu_plane *pdpu = to_dpu_plane(plane); - - _dpu_hw_sspp_init_debugfs(pdpu->pipe_hw, dpu_kms, entry); - } -} #endif static bool dpu_plane_format_mod_supported(struct drm_plane *plane, @@ -1450,11 +1452,6 @@ static const struct drm_plane_helper_funcs dpu_plane_helper_funcs = { .atomic_update = dpu_plane_atomic_update, }; -enum dpu_sspp dpu_plane_pipe(struct drm_plane *plane) -{ - return plane ? to_dpu_plane(plane)->pipe : SSPP_NONE; -} - /* initialize plane */ struct drm_plane *dpu_plane_init(struct drm_device *dev, uint32_t pipe, enum drm_plane_type type, @@ -1465,6 +1462,7 @@ struct drm_plane *dpu_plane_init(struct drm_device *dev, struct dpu_plane *pdpu; struct msm_drm_private *priv = dev->dev_private; struct dpu_kms *kms = to_dpu_kms(priv->kms); + struct dpu_hw_sspp *pipe_hw; uint32_t num_formats; uint32_t supported_rotations; int ret = -EINVAL; @@ -1482,24 +1480,20 @@ struct drm_plane *dpu_plane_init(struct drm_device *dev, pdpu->pipe = pipe; /* initialize underlying h/w driver */ - pdpu->pipe_hw = dpu_hw_sspp_init(pipe, kms->mmio, kms->catalog); - if (IS_ERR(pdpu->pipe_hw)) { - DPU_ERROR("[%u]SSPP init failed\n", pipe); - ret = PTR_ERR(pdpu->pipe_hw); + pipe_hw = dpu_rm_get_sspp(&kms->rm, pipe); + if (!pipe_hw || !pipe_hw->cap || !pipe_hw->cap->sblk) { + DPU_ERROR("[%u]SSPP is invalid\n", pipe); goto clean_plane; - } else if (!pdpu->pipe_hw->cap || !pdpu->pipe_hw->cap->sblk) { - DPU_ERROR("[%u]SSPP init returned invalid cfg\n", pipe); - goto clean_sspp; } - format_list = pdpu->pipe_hw->cap->sblk->format_list; - num_formats = pdpu->pipe_hw->cap->sblk->num_formats; + format_list = pipe_hw->cap->sblk->format_list; + num_formats = pipe_hw->cap->sblk->num_formats; ret = drm_universal_plane_init(dev, plane, 0xff, &dpu_plane_funcs, format_list, num_formats, supported_format_modifiers, type, NULL); if (ret) - goto clean_sspp; + goto clean_plane; pdpu->catalog = kms->catalog; @@ -1515,7 +1509,7 @@ struct drm_plane *dpu_plane_init(struct drm_device *dev, supported_rotations = DRM_MODE_REFLECT_MASK | DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180; - if (pdpu->pipe_hw->cap->features & BIT(DPU_SSPP_INLINE_ROTATION)) + if (pipe_hw->cap->features & BIT(DPU_SSPP_INLINE_ROTATION)) supported_rotations |= DRM_MODE_ROTATE_MASK; drm_plane_create_rotation_property(plane, @@ -1532,9 +1526,6 @@ struct drm_plane *dpu_plane_init(struct drm_device *dev, pipe, plane->base.id); return plane; -clean_sspp: - if (pdpu && pdpu->pipe_hw) - dpu_hw_sspp_destroy(pdpu->pipe_hw); clean_plane: kfree(pdpu); return ERR_PTR(ret); diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h index b7b1b05199c2..abd6b21a049b 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h @@ -18,6 +18,10 @@ * struct dpu_plane_state: Define dpu extension of drm plane state object * @base: base drm plane state object * @aspace: pointer to address space for input/output buffers + * @pipe: software pipe description + * @r_pipe: software pipe description of the second pipe + * @pipe_cfg: software pipe configuration + * @r_pipe_cfg: software pipe configuration for the second pipe * @stage: assigned by crtc blender * @needs_qos_remap: qos remap settings need to be updated * @multirect_index: index of the rectangle of SSPP @@ -31,10 +35,12 @@ struct dpu_plane_state { struct drm_plane_state base; struct msm_gem_address_space *aspace; + struct dpu_sw_pipe pipe; + struct dpu_sw_pipe r_pipe; + struct dpu_sw_pipe_cfg pipe_cfg; + struct dpu_sw_pipe_cfg r_pipe_cfg; enum dpu_stage stage; bool needs_qos_remap; - uint32_t multirect_index; - uint32_t multirect_mode; bool pending; u64 plane_fetch_bw; @@ -44,27 +50,10 @@ struct dpu_plane_state { unsigned int rotation; }; -/** - * struct dpu_multirect_plane_states: Defines multirect pair of drm plane states - * @r0: drm plane configured on rect 0 - * @r1: drm plane configured on rect 1 - */ -struct dpu_multirect_plane_states { - const struct drm_plane_state *r0; - const struct drm_plane_state *r1; -}; - #define to_dpu_plane_state(x) \ container_of(x, struct dpu_plane_state, base) /** - * dpu_plane_pipe - return sspp identifier for the given plane - * @plane: Pointer to DRM plane object - * Returns: sspp identifier of the given plane - */ -enum dpu_sspp dpu_plane_pipe(struct drm_plane *plane); - -/** * dpu_plane_flush - final plane operations before commit flush * @plane: Pointer to drm plane structure */ @@ -89,19 +78,6 @@ struct drm_plane *dpu_plane_init(struct drm_device *dev, unsigned long possible_crtcs); /** - * dpu_plane_validate_multirecti_v2 - validate the multirect planes - * against hw limitations - * @plane: drm plate states of the multirect pair - */ -int dpu_plane_validate_multirect_v2(struct dpu_multirect_plane_states *plane); - -/** - * dpu_plane_clear_multirect - clear multirect bits for the given pipe - * @drm_state: Pointer to DRM plane state - */ -void dpu_plane_clear_multirect(const struct drm_plane_state *drm_state); - -/** * dpu_plane_color_fill - enables color fill on plane * @plane: Pointer to DRM plane object * @color: RGB fill color value, [23..16] Blue, [15..8] Green, [7..0] Red diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c index 66c1b70d244f..f4dda88a73f7 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c @@ -8,6 +8,7 @@ #include "dpu_hw_lm.h" #include "dpu_hw_ctl.h" #include "dpu_hw_pingpong.h" +#include "dpu_hw_sspp.h" #include "dpu_hw_intf.h" #include "dpu_hw_wb.h" #include "dpu_hw_dspp.h" @@ -91,6 +92,9 @@ int dpu_rm_destroy(struct dpu_rm *rm) for (i = 0; i < ARRAY_SIZE(rm->hw_wb); i++) dpu_hw_wb_destroy(rm->hw_wb[i]); + for (i = 0; i < ARRAY_SIZE(rm->hw_sspp); i++) + dpu_hw_sspp_destroy(rm->hw_sspp[i]); + return 0; } @@ -255,6 +259,24 @@ int dpu_rm_init(struct dpu_rm *rm, rm->dsc_blks[dsc->id - DSC_0] = &hw->base; } + for (i = 0; i < cat->sspp_count; i++) { + struct dpu_hw_sspp *hw; + const struct dpu_sspp_cfg *sspp = &cat->sspp[i]; + + if (sspp->id < SSPP_NONE || sspp->id >= SSPP_MAX) { + DPU_ERROR("skip intf %d with invalid id\n", sspp->id); + continue; + } + + hw = dpu_hw_sspp_init(sspp->id, mmio, cat); + if (IS_ERR(hw)) { + rc = PTR_ERR(hw); + DPU_ERROR("failed sspp object creation: err %d\n", rc); + goto fail; + } + rm->hw_sspp[sspp->id - SSPP_NONE] = hw; + } + return 0; fail: diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h index 59de72b381f9..d62c2edb2460 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h @@ -21,6 +21,7 @@ struct dpu_global_state; * @hw_intf: array of intf hardware resources * @hw_wb: array of wb hardware resources * @dspp_blks: array of dspp hardware resources + * @hw_sspp: array of sspp hardware resources */ struct dpu_rm { struct dpu_hw_blk *pingpong_blks[PINGPONG_MAX - PINGPONG_0]; @@ -31,6 +32,7 @@ struct dpu_rm { struct dpu_hw_blk *dspp_blks[DSPP_MAX - DSPP_0]; struct dpu_hw_blk *merge_3d_blks[MERGE_3D_MAX - MERGE_3D_0]; struct dpu_hw_blk *dsc_blks[DSC_MAX - DSC_0]; + struct dpu_hw_sspp *hw_sspp[SSPP_MAX - SSPP_NONE]; }; /** @@ -108,5 +110,15 @@ static inline struct dpu_hw_wb *dpu_rm_get_wb(struct dpu_rm *rm, enum dpu_wb wb_ return rm->hw_wb[wb_idx - WB_0]; } +/** + * dpu_rm_get_sspp - Return a struct dpu_hw_sspp instance given it's index. + * @rm: DPU Resource Manager handle + * @sspp_idx: SSPP index + */ +static inline struct dpu_hw_sspp *dpu_rm_get_sspp(struct dpu_rm *rm, enum dpu_sspp sspp_idx) +{ + return rm->hw_sspp[sspp_idx - SSPP_NONE]; +} + #endif /* __DPU_RM_H__ */ diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h index 76169f406505..0ad148cc2fb8 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h @@ -633,9 +633,9 @@ TRACE_EVENT(dpu_enc_phys_vid_irq_ctrl, TRACE_EVENT(dpu_crtc_setup_mixer, TP_PROTO(uint32_t crtc_id, uint32_t plane_id, struct drm_plane_state *state, struct dpu_plane_state *pstate, - uint32_t stage_idx, enum dpu_sspp sspp, uint32_t pixel_format, + uint32_t stage_idx, uint32_t pixel_format, uint64_t modifier), - TP_ARGS(crtc_id, plane_id, state, pstate, stage_idx, sspp, + TP_ARGS(crtc_id, plane_id, state, pstate, stage_idx, pixel_format, modifier), TP_STRUCT__entry( __field( uint32_t, crtc_id ) @@ -659,9 +659,9 @@ TRACE_EVENT(dpu_crtc_setup_mixer, __entry->dst_rect = drm_plane_state_dest(state); __entry->stage_idx = stage_idx; __entry->stage = pstate->stage; - __entry->sspp = sspp; - __entry->multirect_idx = pstate->multirect_index; - __entry->multirect_mode = pstate->multirect_mode; + __entry->sspp = pstate->pipe.sspp->idx; + __entry->multirect_idx = pstate->pipe.multirect_index; + __entry->multirect_mode = pstate->pipe.multirect_mode; __entry->pixel_format = pixel_format; __entry->modifier = modifier; ), @@ -762,18 +762,17 @@ TRACE_EVENT(dpu_crtc_disable_frame_pending, ); TRACE_EVENT(dpu_plane_set_scanout, - TP_PROTO(enum dpu_sspp index, struct dpu_hw_fmt_layout *layout, - enum dpu_sspp_multirect_index multirect_index), - TP_ARGS(index, layout, multirect_index), + TP_PROTO(struct dpu_sw_pipe *pipe, struct dpu_hw_fmt_layout *layout), + TP_ARGS(pipe, layout), TP_STRUCT__entry( __field( enum dpu_sspp, index ) __field_struct( struct dpu_hw_fmt_layout, layout ) __field( enum dpu_sspp_multirect_index, multirect_index) ), TP_fast_assign( - __entry->index = index; + __entry->index = pipe->sspp->idx; __entry->layout = *layout; - __entry->multirect_index = multirect_index; + __entry->multirect_index = pipe->multirect_index; ), TP_printk("index:%d layout:{%ux%u @ [%u/%u, %u/%u, %u/%u, %u/%u]} " "multirect_index:%d", __entry->index, __entry->layout.width, diff --git a/drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h b/drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h index a2b6422948ec..cc8fde450884 100644 --- a/drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h +++ b/drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h @@ -8,26 +8,26 @@ http://github.com/freedreno/envytools/ git clone https://github.com/freedreno/envytools.git The rules-ng-ng source files this header was generated from are: -- /home/robclark/tmp/mesa/src/freedreno/registers/msm.xml ( 944 bytes, from 2022-03-03 01:18:13) -- /home/robclark/tmp/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2020-12-31 19:26:32) -- /home/robclark/tmp/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2021-01-30 18:25:22) -- /home/robclark/tmp/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2021-01-30 18:25:22) -- /home/robclark/tmp/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2021-01-30 18:25:22) -- /home/robclark/tmp/mesa/src/freedreno/registers/dsi/dsi.xml ( 17560 bytes, from 2021-09-16 22:37:02) -- /home/robclark/tmp/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2021-07-22 15:21:56) -- /home/robclark/tmp/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2021-07-22 15:21:56) -- /home/robclark/tmp/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2021-07-22 15:21:56) -- /home/robclark/tmp/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2021-07-22 15:21:56) -- /home/robclark/tmp/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2021-07-22 15:21:56) -- /home/robclark/tmp/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2021-07-22 15:21:56) -- /home/robclark/tmp/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 11007 bytes, from 2022-03-03 01:18:13) -- /home/robclark/tmp/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2021-01-30 18:25:22) -- /home/robclark/tmp/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2021-01-30 18:25:22) -- /home/robclark/tmp/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2021-01-30 18:25:22) -- /home/robclark/tmp/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 41874 bytes, from 2021-01-30 18:25:22) -- /home/robclark/tmp/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2021-01-30 18:25:22) - -Copyright (C) 2013-2021 by the following authors: +- /home/robclark/src/mesa/mesa/src/freedreno/registers/msm.xml ( 944 bytes, from 2022-07-23 20:21:46) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2022-07-23 20:21:46) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2022-03-08 17:40:42) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2022-03-08 17:40:42) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2022-03-08 17:40:42) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi.xml ( 18746 bytes, from 2022-04-28 17:29:36) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2022-03-08 17:40:42) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2022-03-08 17:40:42) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2022-03-08 17:40:42) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2022-03-08 17:40:42) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2022-03-08 17:40:42) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2022-03-08 17:40:42) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 11007 bytes, from 2022-03-08 17:40:42) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2022-03-08 17:40:42) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2022-03-08 17:40:42) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2022-03-08 17:40:42) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 42350 bytes, from 2022-09-20 17:45:56) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2022-03-08 17:40:42) + +Copyright (C) 2013-2022 by the following authors: - Rob Clark <robdclark@gmail.com> (robclark) - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin) diff --git a/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c b/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c index 9a1a0769575d..6e37072ed302 100644 --- a/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c +++ b/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c @@ -84,10 +84,6 @@ static void mdp4_disable_commit(struct msm_kms *kms) mdp4_disable(mdp4_kms); } -static void mdp4_prepare_commit(struct msm_kms *kms, struct drm_atomic_state *state) -{ -} - static void mdp4_flush_commit(struct msm_kms *kms, unsigned crtc_mask) { /* TODO */ @@ -154,7 +150,6 @@ static const struct mdp_kms_funcs kms_funcs = { .disable_vblank = mdp4_disable_vblank, .enable_commit = mdp4_enable_commit, .disable_commit = mdp4_disable_commit, - .prepare_commit = mdp4_prepare_commit, .flush_commit = mdp4_flush_commit, .wait_flush = mdp4_wait_flush, .complete_commit = mdp4_complete_commit, diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h b/drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h index 86fc44b518cb..270e11c904bd 100644 --- a/drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h +++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h @@ -8,26 +8,26 @@ http://github.com/freedreno/envytools/ git clone https://github.com/freedreno/envytools.git The rules-ng-ng source files this header was generated from are: -- /home/robclark/tmp/mesa/src/freedreno/registers/msm.xml ( 944 bytes, from 2022-03-03 01:18:13) -- /home/robclark/tmp/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2020-12-31 19:26:32) -- /home/robclark/tmp/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2021-01-30 18:25:22) -- /home/robclark/tmp/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2021-01-30 18:25:22) -- /home/robclark/tmp/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2021-01-30 18:25:22) -- /home/robclark/tmp/mesa/src/freedreno/registers/dsi/dsi.xml ( 17560 bytes, from 2021-09-16 22:37:02) -- /home/robclark/tmp/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2021-07-22 15:21:56) -- /home/robclark/tmp/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2021-07-22 15:21:56) -- /home/robclark/tmp/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2021-07-22 15:21:56) -- /home/robclark/tmp/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2021-07-22 15:21:56) -- /home/robclark/tmp/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2021-07-22 15:21:56) -- /home/robclark/tmp/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2021-07-22 15:21:56) -- /home/robclark/tmp/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 11007 bytes, from 2022-03-03 01:18:13) -- /home/robclark/tmp/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2021-01-30 18:25:22) -- /home/robclark/tmp/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2021-01-30 18:25:22) -- /home/robclark/tmp/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2021-01-30 18:25:22) -- /home/robclark/tmp/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 41874 bytes, from 2021-01-30 18:25:22) -- /home/robclark/tmp/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2021-01-30 18:25:22) - -Copyright (C) 2013-2021 by the following authors: +- /home/robclark/src/mesa/mesa/src/freedreno/registers/msm.xml ( 944 bytes, from 2022-07-23 20:21:46) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2022-07-23 20:21:46) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2022-03-08 17:40:42) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2022-03-08 17:40:42) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2022-03-08 17:40:42) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi.xml ( 18746 bytes, from 2022-04-28 17:29:36) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2022-03-08 17:40:42) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2022-03-08 17:40:42) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2022-03-08 17:40:42) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2022-03-08 17:40:42) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2022-03-08 17:40:42) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2022-03-08 17:40:42) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 11007 bytes, from 2022-03-08 17:40:42) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2022-03-08 17:40:42) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2022-03-08 17:40:42) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2022-03-08 17:40:42) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 42350 bytes, from 2022-09-20 17:45:56) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2022-03-08 17:40:42) + +Copyright (C) 2013-2022 by the following authors: - Rob Clark <robdclark@gmail.com> (robclark) - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin) diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c b/drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c index 1f1555aa02d2..2eec2d78f32a 100644 --- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c +++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c @@ -655,7 +655,7 @@ static const struct mdp5_cfg_hw msm8x96_config = { .max_clk = 412500000, }; -const struct mdp5_cfg_hw msm8x76_config = { +static const struct mdp5_cfg_hw msm8x76_config = { .name = "msm8x76", .mdp = { .count = 1, diff --git a/drivers/gpu/drm/msm/disp/mdp_common.xml.h b/drivers/gpu/drm/msm/disp/mdp_common.xml.h index be759106b621..4dd8d7db2862 100644 --- a/drivers/gpu/drm/msm/disp/mdp_common.xml.h +++ b/drivers/gpu/drm/msm/disp/mdp_common.xml.h @@ -8,26 +8,26 @@ http://github.com/freedreno/envytools/ git clone https://github.com/freedreno/envytools.git The rules-ng-ng source files this header was generated from are: -- /home/robclark/tmp/mesa/src/freedreno/registers/msm.xml ( 944 bytes, from 2022-03-03 01:18:13) -- /home/robclark/tmp/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2020-12-31 19:26:32) -- /home/robclark/tmp/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2021-01-30 18:25:22) -- /home/robclark/tmp/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2021-01-30 18:25:22) -- /home/robclark/tmp/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2021-01-30 18:25:22) -- /home/robclark/tmp/mesa/src/freedreno/registers/dsi/dsi.xml ( 17560 bytes, from 2021-09-16 22:37:02) -- /home/robclark/tmp/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2021-07-22 15:21:56) -- /home/robclark/tmp/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2021-07-22 15:21:56) -- /home/robclark/tmp/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2021-07-22 15:21:56) -- /home/robclark/tmp/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2021-07-22 15:21:56) -- /home/robclark/tmp/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2021-07-22 15:21:56) -- /home/robclark/tmp/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2021-07-22 15:21:56) -- /home/robclark/tmp/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 11007 bytes, from 2022-03-03 01:18:13) -- /home/robclark/tmp/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2021-01-30 18:25:22) -- /home/robclark/tmp/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2021-01-30 18:25:22) -- /home/robclark/tmp/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2021-01-30 18:25:22) -- /home/robclark/tmp/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 41874 bytes, from 2021-01-30 18:25:22) -- /home/robclark/tmp/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2021-01-30 18:25:22) - -Copyright (C) 2013-2021 by the following authors: +- /home/robclark/src/mesa/mesa/src/freedreno/registers/msm.xml ( 944 bytes, from 2022-07-23 20:21:46) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2022-07-23 20:21:46) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2022-03-08 17:40:42) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2022-03-08 17:40:42) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2022-03-08 17:40:42) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi.xml ( 18746 bytes, from 2022-04-28 17:29:36) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2022-03-08 17:40:42) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2022-03-08 17:40:42) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2022-03-08 17:40:42) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2022-03-08 17:40:42) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2022-03-08 17:40:42) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2022-03-08 17:40:42) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 11007 bytes, from 2022-03-08 17:40:42) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2022-03-08 17:40:42) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2022-03-08 17:40:42) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2022-03-08 17:40:42) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 42350 bytes, from 2022-09-20 17:45:56) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2022-03-08 17:40:42) + +Copyright (C) 2013-2022 by the following authors: - Rob Clark <robdclark@gmail.com> (robclark) - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin) diff --git a/drivers/gpu/drm/msm/disp/msm_disp_snapshot.c b/drivers/gpu/drm/msm/disp/msm_disp_snapshot.c index b73031cd48e4..e75b97127c0d 100644 --- a/drivers/gpu/drm/msm/disp/msm_disp_snapshot.c +++ b/drivers/gpu/drm/msm/disp/msm_disp_snapshot.c @@ -129,9 +129,6 @@ void msm_disp_snapshot_destroy(struct drm_device *drm_dev) } priv = drm_dev->dev_private; - if (!priv->kms) - return; - kms = priv->kms; if (kms->dump_worker) |