diff options
Diffstat (limited to 'drivers/gpu/drm/nouveau/include/nvif')
-rw-r--r-- | drivers/gpu/drm/nouveau/include/nvif/cl0080.h | 3 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/include/nvif/class.h | 21 |
2 files changed, 24 insertions, 0 deletions
diff --git a/drivers/gpu/drm/nouveau/include/nvif/cl0080.h b/drivers/gpu/drm/nouveau/include/nvif/cl0080.h index 8b5a240d57e4..fa161b74d967 100644 --- a/drivers/gpu/drm/nouveau/include/nvif/cl0080.h +++ b/drivers/gpu/drm/nouveau/include/nvif/cl0080.h @@ -35,6 +35,7 @@ struct nv_device_info_v0 { #define NV_DEVICE_INFO_V0_VOLTA 0x0b #define NV_DEVICE_INFO_V0_TURING 0x0c #define NV_DEVICE_INFO_V0_AMPERE 0x0d +#define NV_DEVICE_INFO_V0_ADA 0x0e __u8 family; __u8 pad06[2]; __u64 ram_size; @@ -90,6 +91,8 @@ struct nv_device_time_v0 { #define NV_DEVICE_HOST_RUNLIST_ENGINES_SEC2 0x00004000 #define NV_DEVICE_HOST_RUNLIST_ENGINES_NVDEC 0x00008000 #define NV_DEVICE_HOST_RUNLIST_ENGINES_NVENC 0x00010000 +#define NV_DEVICE_HOST_RUNLIST_ENGINES_NVJPG 0x00020000 +#define NV_DEVICE_HOST_RUNLIST_ENGINES_OFA 0x00040000 /* Returns the number of available channels on runlist(data). */ #define NV_DEVICE_HOST_RUNLIST_CHANNELS NV_DEVICE_HOST(0x00000101) #endif diff --git a/drivers/gpu/drm/nouveau/include/nvif/class.h b/drivers/gpu/drm/nouveau/include/nvif/class.h index ad1e5de84e80..e668ab1664f0 100644 --- a/drivers/gpu/drm/nouveau/include/nvif/class.h +++ b/drivers/gpu/drm/nouveau/include/nvif/class.h @@ -104,6 +104,7 @@ #define GV100_DISP /* if0010.h */ 0x0000c370 #define TU102_DISP /* if0010.h */ 0x0000c570 #define GA102_DISP /* if0010.h */ 0x0000c670 +#define AD102_DISP /* if0010.h */ 0x0000c770 #define GV100_DISP_CAPS 0x0000c373 @@ -154,6 +155,7 @@ #define GV100_DISP_CORE_CHANNEL_DMA /* if0014.h */ 0x0000c37d #define TU102_DISP_CORE_CHANNEL_DMA /* if0014.h */ 0x0000c57d #define GA102_DISP_CORE_CHANNEL_DMA /* if0014.h */ 0x0000c67d +#define AD102_DISP_CORE_CHANNEL_DMA /* if0014.h */ 0x0000c77d #define NV50_DISP_OVERLAY_CHANNEL_DMA /* if0014.h */ 0x0000507e #define G82_DISP_OVERLAY_CHANNEL_DMA /* if0014.h */ 0x0000827e @@ -192,8 +194,15 @@ #define AMPERE_B /* cl9097.h */ 0x0000c797 +#define ADA_A /* cl9097.h */ 0x0000c997 + #define NV74_BSP 0x000074b0 +#define NVC4B0_VIDEO_DECODER 0x0000c4b0 +#define NVC6B0_VIDEO_DECODER 0x0000c6b0 +#define NVC7B0_VIDEO_DECODER 0x0000c7b0 +#define NVC9B0_VIDEO_DECODER 0x0000c9b0 + #define GT212_MSVLD 0x000085b1 #define IGT21A_MSVLD 0x000086b1 #define G98_MSVLD 0x000088b1 @@ -222,6 +231,10 @@ #define AMPERE_DMA_COPY_A 0x0000c6b5 #define AMPERE_DMA_COPY_B 0x0000c7b5 +#define NVC4B7_VIDEO_ENCODER 0x0000c4b7 +#define NVC7B7_VIDEO_ENCODER 0x0000c7b7 +#define NVC9B7_VIDEO_ENCODER 0x0000c9b7 + #define FERMI_DECOMPRESS 0x000090b8 #define NV50_COMPUTE 0x000050c0 @@ -237,6 +250,14 @@ #define VOLTA_COMPUTE_A 0x0000c3c0 #define TURING_COMPUTE_A 0x0000c5c0 #define AMPERE_COMPUTE_B 0x0000c7c0 +#define ADA_COMPUTE_A 0x0000c9c0 #define NV74_CIPHER 0x000074c1 + +#define NVC4D1_VIDEO_NVJPG 0x0000c4d1 +#define NVC9D1_VIDEO_NVJPG 0x0000c9d1 + +#define NVC6FA_VIDEO_OFA 0x0000c6fa +#define NVC7FA_VIDEO_OFA 0x0000c7fa +#define NVC9FA_VIDEO_OFA 0x0000c9fa #endif |