diff options
Diffstat (limited to 'drivers/gpu/drm/xe/regs/xe_guc_regs.h')
| -rw-r--r-- | drivers/gpu/drm/xe/regs/xe_guc_regs.h | 32 |
1 files changed, 15 insertions, 17 deletions
diff --git a/drivers/gpu/drm/xe/regs/xe_guc_regs.h b/drivers/gpu/drm/xe/regs/xe_guc_regs.h index 1960f9e78ec4..bc9b42b38795 100644 --- a/drivers/gpu/drm/xe/regs/xe_guc_regs.h +++ b/drivers/gpu/drm/xe/regs/xe_guc_regs.h @@ -54,23 +54,21 @@ #define HUC_STATUS2 _MMIO(0xd3b0) #define HUC_FW_VERIFIED REG_BIT(7) -#define GEN11_HUC_KERNEL_LOAD_INFO _MMIO(0xc1dc) +#define HUC_KERNEL_LOAD_INFO _MMIO(0xc1dc) #define HUC_LOAD_SUCCESSFUL REG_BIT(0) #define GUC_WOPCM_SIZE _MMIO(0xc050) #define GUC_WOPCM_SIZE_MASK REG_GENMASK(31, 12) #define GUC_WOPCM_SIZE_LOCKED REG_BIT(0) -#define GEN8_GT_PM_CONFIG _MMIO(0x138140) -#define GEN9LP_GT_PM_CONFIG _MMIO(0x138140) -#define GEN9_GT_PM_CONFIG _MMIO(0x13816c) +#define GT_PM_CONFIG _MMIO(0x13816c) #define GT_DOORBELL_ENABLE REG_BIT(0) -#define GEN8_GTCR _MMIO(0x4274) -#define GEN8_GTCR_INVALIDATE REG_BIT(0) +#define GTCR _MMIO(0x4274) +#define GTCR_INVALIDATE REG_BIT(0) -#define GEN12_GUC_TLB_INV_CR _MMIO(0xcee8) -#define GEN12_GUC_TLB_INV_CR_INVALIDATE REG_BIT(0) +#define GUC_TLB_INV_CR _MMIO(0xcee8) +#define GUC_TLB_INV_CR_INVALIDATE REG_BIT(0) #define GUC_ARAT_C6DIS _MMIO(0xa178) @@ -79,11 +77,11 @@ #define PVC_GUC_MOCS_UC_INDEX 1 #define PVC_GUC_MOCS_INDEX(index) REG_FIELD_PREP(PVC_GUC_MOCS_INDEX_MASK, \ index) -#define GUC_GEN10_SHIM_WC_ENABLE REG_BIT(21) +#define GUC_SHIM_WC_ENABLE REG_BIT(21) #define GUC_ENABLE_MIA_CLOCK_GATING REG_BIT(15) #define GUC_ENABLE_READ_CACHE_FOR_WOPCM_DATA REG_BIT(10) #define GUC_ENABLE_READ_CACHE_FOR_SRAM_DATA REG_BIT(9) -#define GUC_GEN10_MSGCH_ENABLE REG_BIT(4) +#define GUC_MSGCH_ENABLE REG_BIT(4) #define GUC_ENABLE_MIA_CACHING REG_BIT(2) #define GUC_ENABLE_READ_CACHE_LOGIC REG_BIT(1) #define GUC_DISABLE_SRAM_INIT_TO_ZEROES REG_BIT(0) @@ -91,7 +89,7 @@ #define GUC_SEND_INTERRUPT _MMIO(0xc4c8) #define GUC_SEND_TRIGGER REG_BIT(0) -#define GEN11_GUC_HOST_INTERRUPT _MMIO(0x1901f0) +#define GUC_HOST_INTERRUPT _MMIO(0x1901f0) #define GUC_NUM_DOORBELLS 256 @@ -105,13 +103,13 @@ struct guc_doorbell_info { u32 reserved[14]; } __packed; -#define GEN8_DRBREGL(x) _MMIO(0x1000 + (x) * 8) -#define GEN8_DRB_VALID REG_BIT(0) -#define GEN8_DRBREGU(x) _MMIO(0x1000 + (x) * 8 + 4) +#define DRBREGL(x) _MMIO(0x1000 + (x) * 8) +#define DRB_VALID REG_BIT(0) +#define DRBREGU(x) _MMIO(0x1000 + (x) * 8 + 4) -#define GEN12_DIST_DBS_POPULATED _MMIO(0xd08) -#define GEN12_DOORBELLS_PER_SQIDI_MASK REG_GENMASK(23, 16) -#define GEN12_SQIDIS_DOORBELL_EXIST_MASK REG_GENMASK(15, 0) +#define DIST_DBS_POPULATED _MMIO(0xd08) +#define DOORBELLS_PER_SQIDI_MASK REG_GENMASK(23, 16) +#define SQIDIS_DOORBELL_EXIST_MASK REG_GENMASK(15, 0) #define GUC_BCS_RCS_IER _MMIO(0xC550) #define GUC_VCS2_VCS1_IER _MMIO(0xC554) |