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path: root/drivers/net/wireless/realtek/rtw89/core.h
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Diffstat (limited to 'drivers/net/wireless/realtek/rtw89/core.h')
-rw-r--r--drivers/net/wireless/realtek/rtw89/core.h407
1 files changed, 364 insertions, 43 deletions
diff --git a/drivers/net/wireless/realtek/rtw89/core.h b/drivers/net/wireless/realtek/rtw89/core.h
index 04ce221730f9..d5272a82ff8b 100644
--- a/drivers/net/wireless/realtek/rtw89/core.h
+++ b/drivers/net/wireless/realtek/rtw89/core.h
@@ -37,7 +37,14 @@ extern const struct ieee80211_ops rtw89_ops;
#define RSSI_FACTOR 1
#define RTW89_RSSI_RAW_TO_DBM(rssi) ((s8)((rssi) >> RSSI_FACTOR) - MAX_RSSI)
#define RTW89_TX_DIV_RSSI_RAW_TH (2 << RSSI_FACTOR)
-#define RTW89_RADIOTAP_ROOM ALIGN(sizeof(struct ieee80211_radiotap_he), 64)
+#define RTW89_RADIOTAP_ROOM_HE sizeof(struct ieee80211_radiotap_he)
+#define RTW89_RADIOTAP_ROOM_EHT \
+ (sizeof(struct ieee80211_radiotap_tlv) + \
+ ALIGN(struct_size((struct ieee80211_radiotap_eht *)0, user_info, 1), 4) + \
+ sizeof(struct ieee80211_radiotap_tlv) + \
+ ALIGN(sizeof(struct ieee80211_radiotap_eht_usig), 4))
+#define RTW89_RADIOTAP_ROOM \
+ ALIGN(max(RTW89_RADIOTAP_ROOM_HE, RTW89_RADIOTAP_ROOM_EHT), 64)
#define RTW89_HTC_MASK_VARIANT GENMASK(1, 0)
#define RTW89_HTC_VARIANT_HE 3
@@ -640,12 +647,29 @@ enum rtw89_rate_section {
RTW89_RS_TX_SHAPE_NUM = RTW89_RS_OFDM + 1,
};
+enum rtw89_rate_offset_indexes {
+ RTW89_RATE_OFFSET_HE,
+ RTW89_RATE_OFFSET_VHT,
+ RTW89_RATE_OFFSET_HT,
+ RTW89_RATE_OFFSET_OFDM,
+ RTW89_RATE_OFFSET_CCK,
+ RTW89_RATE_OFFSET_DLRU_EHT,
+ RTW89_RATE_OFFSET_DLRU_HE,
+ RTW89_RATE_OFFSET_EHT,
+ __RTW89_RATE_OFFSET_NUM,
+
+ RTW89_RATE_OFFSET_NUM_AX = RTW89_RATE_OFFSET_CCK + 1,
+ RTW89_RATE_OFFSET_NUM_BE = RTW89_RATE_OFFSET_EHT + 1,
+};
+
enum rtw89_rate_num {
RTW89_RATE_CCK_NUM = 4,
RTW89_RATE_OFDM_NUM = 8,
- RTW89_RATE_MCS_NUM = 12,
RTW89_RATE_HEDCM_NUM = 4, /* for HEDCM MCS0/1/3/4 */
- RTW89_RATE_OFFSET_NUM = 5, /* for HE(HEDCM)/VHT/HT/OFDM/CCK offset */
+
+ RTW89_RATE_MCS_NUM_AX = 12,
+ RTW89_RATE_MCS_NUM_BE = 16,
+ __RTW89_RATE_MCS_NUM = 16,
};
enum rtw89_nss {
@@ -670,6 +694,12 @@ enum rtw89_beamforming_type {
RTW89_BF_NUM,
};
+enum rtw89_ofdma_type {
+ RTW89_NON_OFDMA = 0,
+ RTW89_OFDMA = 1,
+ RTW89_OFDMA_NUM,
+};
+
enum rtw89_regulation_type {
RTW89_WW = 0,
RTW89_ETSI = 1,
@@ -686,6 +716,7 @@ enum rtw89_regulation_type {
RTW89_CN = 12,
RTW89_QATAR = 13,
RTW89_UK = 14,
+ RTW89_THAILAND = 15,
RTW89_REGD_NUM,
};
@@ -715,44 +746,16 @@ enum rtw89_fw_pkt_ofld_type {
struct rtw89_txpwr_byrate {
s8 cck[RTW89_RATE_CCK_NUM];
s8 ofdm[RTW89_RATE_OFDM_NUM];
- s8 mcs[RTW89_NSS_NUM][RTW89_RATE_MCS_NUM];
- s8 hedcm[RTW89_NSS_HEDCM_NUM][RTW89_RATE_HEDCM_NUM];
- s8 offset[RTW89_RATE_OFFSET_NUM];
-};
-
-enum rtw89_bandwidth_section_num {
- RTW89_BW20_SEC_NUM = 8,
- RTW89_BW40_SEC_NUM = 4,
- RTW89_BW80_SEC_NUM = 2,
-};
-
-#define RTW89_TXPWR_LMT_PAGE_SIZE 40
-
-struct rtw89_txpwr_limit {
- s8 cck_20m[RTW89_BF_NUM];
- s8 cck_40m[RTW89_BF_NUM];
- s8 ofdm[RTW89_BF_NUM];
- s8 mcs_20m[RTW89_BW20_SEC_NUM][RTW89_BF_NUM];
- s8 mcs_40m[RTW89_BW40_SEC_NUM][RTW89_BF_NUM];
- s8 mcs_80m[RTW89_BW80_SEC_NUM][RTW89_BF_NUM];
- s8 mcs_160m[RTW89_BF_NUM];
- s8 mcs_40m_0p5[RTW89_BF_NUM];
- s8 mcs_40m_2p5[RTW89_BF_NUM];
-};
-
-#define RTW89_RU_SEC_NUM 8
-
-#define RTW89_TXPWR_LMT_RU_PAGE_SIZE 24
-
-struct rtw89_txpwr_limit_ru {
- s8 ru26[RTW89_RU_SEC_NUM];
- s8 ru52[RTW89_RU_SEC_NUM];
- s8 ru106[RTW89_RU_SEC_NUM];
+ s8 mcs[RTW89_OFDMA_NUM][RTW89_NSS_NUM][__RTW89_RATE_MCS_NUM];
+ s8 hedcm[RTW89_OFDMA_NUM][RTW89_NSS_HEDCM_NUM][RTW89_RATE_HEDCM_NUM];
+ s8 offset[__RTW89_RATE_OFFSET_NUM];
+ s8 trap;
};
struct rtw89_rate_desc {
enum rtw89_nss nss;
enum rtw89_rate_section rs;
+ enum rtw89_ofdma_type ofdma;
u8 idx;
};
@@ -841,9 +844,14 @@ enum rtw89_bandwidth {
RTW89_CHANNEL_WIDTH_40 = 1,
RTW89_CHANNEL_WIDTH_80 = 2,
RTW89_CHANNEL_WIDTH_160 = 3,
- RTW89_CHANNEL_WIDTH_80_80 = 4,
- RTW89_CHANNEL_WIDTH_5 = 5,
- RTW89_CHANNEL_WIDTH_10 = 6,
+ RTW89_CHANNEL_WIDTH_320 = 4,
+
+ /* keep index order above */
+ RTW89_CHANNEL_WIDTH_ORDINARY_NUM = 5,
+
+ RTW89_CHANNEL_WIDTH_80_80 = 5,
+ RTW89_CHANNEL_WIDTH_5 = 6,
+ RTW89_CHANNEL_WIDTH_10 = 7,
};
enum rtw89_ps_mode {
@@ -855,13 +863,16 @@ enum rtw89_ps_mode {
#define RTW89_2G_BW_NUM (RTW89_CHANNEL_WIDTH_40 + 1)
#define RTW89_5G_BW_NUM (RTW89_CHANNEL_WIDTH_160 + 1)
-#define RTW89_6G_BW_NUM (RTW89_CHANNEL_WIDTH_160 + 1)
+#define RTW89_6G_BW_NUM (RTW89_CHANNEL_WIDTH_320 + 1)
+#define RTW89_BYR_BW_NUM (RTW89_CHANNEL_WIDTH_320 + 1)
#define RTW89_PPE_BW_NUM (RTW89_CHANNEL_WIDTH_160 + 1)
enum rtw89_ru_bandwidth {
RTW89_RU26 = 0,
RTW89_RU52 = 1,
RTW89_RU106 = 2,
+ RTW89_RU52_26 = 3,
+ RTW89_RU106_26 = 4,
RTW89_RU_NUM,
};
@@ -898,6 +909,7 @@ struct rtw89_chan {
u32 freq;
enum rtw89_subband subband_type;
enum rtw89_sc_offset pri_ch_idx;
+ u8 pri_sb_idx;
};
struct rtw89_chan_rcd {
@@ -926,6 +938,12 @@ struct rtw89_port_reg {
u32 bcn_cnt_tmr;
u32 tsftr_l;
u32 tsftr_h;
+ u32 md_tsft;
+ u32 bss_color;
+ u32 mbssid;
+ u32 mbssid_drop;
+ u32 tsf_sync;
+ u32 hiq_win[RTW89_PORT_NUM];
};
struct rtw89_txwd_body {
@@ -948,6 +966,17 @@ struct rtw89_txwd_body_v1 {
__le32 dword7;
} __packed;
+struct rtw89_txwd_body_v2 {
+ __le32 dword0;
+ __le32 dword1;
+ __le32 dword2;
+ __le32 dword3;
+ __le32 dword4;
+ __le32 dword5;
+ __le32 dword6;
+ __le32 dword7;
+} __packed;
+
struct rtw89_txwd_info {
__le32 dword0;
__le32 dword1;
@@ -957,10 +986,23 @@ struct rtw89_txwd_info {
__le32 dword5;
} __packed;
+struct rtw89_txwd_info_v2 {
+ __le32 dword0;
+ __le32 dword1;
+ __le32 dword2;
+ __le32 dword3;
+ __le32 dword4;
+ __le32 dword5;
+ __le32 dword6;
+ __le32 dword7;
+} __packed;
+
struct rtw89_rx_desc_info {
u16 pkt_size;
u8 pkt_type;
u8 drv_info_size;
+ u8 phy_rpt_size;
+ u8 hdr_cnv_size;
u8 shift;
u8 wl_hd_iv_len;
bool long_rxdesc;
@@ -999,6 +1041,15 @@ struct rtw89_rxdesc_short {
__le32 dword3;
} __packed;
+struct rtw89_rxdesc_short_v2 {
+ __le32 dword0;
+ __le32 dword1;
+ __le32 dword2;
+ __le32 dword3;
+ __le32 dword4;
+ __le32 dword5;
+} __packed;
+
struct rtw89_rxdesc_long {
__le32 dword0;
__le32 dword1;
@@ -1010,6 +1061,19 @@ struct rtw89_rxdesc_long {
__le32 dword7;
} __packed;
+struct rtw89_rxdesc_long_v2 {
+ __le32 dword0;
+ __le32 dword1;
+ __le32 dword2;
+ __le32 dword3;
+ __le32 dword4;
+ __le32 dword5;
+ __le32 dword6;
+ __le32 dword7;
+ __le32 dword8;
+ __le32 dword9;
+} __packed;
+
struct rtw89_tx_desc_info {
u16 pkt_size;
u8 wp_offset;
@@ -2677,6 +2741,7 @@ enum rtw89_ra_mode {
RTW89_RA_MODE_HT = BIT(2),
RTW89_RA_MODE_VHT = BIT(3),
RTW89_RA_MODE_HE = BIT(4),
+ RTW89_RA_MODE_EHT = BIT(5),
};
enum rtw89_ra_report_mode {
@@ -2684,6 +2749,7 @@ enum rtw89_ra_report_mode {
RTW89_RA_RPT_MODE_HT,
RTW89_RA_RPT_MODE_VHT,
RTW89_RA_RPT_MODE_HE,
+ RTW89_RA_RPT_MODE_EHT,
};
enum rtw89_dig_noisy_level {
@@ -2930,6 +2996,7 @@ struct rtw89_vif {
struct list_head list;
struct rtw89_dev *rtwdev;
struct rtw89_roc roc;
+ bool chanctx_assigned; /* only valid when running with chanctx_ops */
enum rtw89_sub_entity_idx sub_entity_idx;
enum rtw89_reg_6ghz_power reg_6ghz_power;
@@ -2957,6 +3024,8 @@ struct rtw89_vif {
bool is_hesta;
bool last_a_ctrl;
bool dyn_tb_bedge_en;
+ bool pre_pwr_diff_en;
+ bool pwr_diff_en;
u8 def_tri_idx;
u32 tdls_peer;
struct work_struct update_beacon_work;
@@ -3032,6 +3101,7 @@ struct rtw89_hci_info {
struct rtw89_chip_ops {
int (*enable_bb_rf)(struct rtw89_dev *rtwdev);
int (*disable_bb_rf)(struct rtw89_dev *rtwdev);
+ void (*bb_preinit)(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx);
void (*bb_reset)(struct rtw89_dev *rtwdev,
enum rtw89_phy_idx phy_idx);
void (*bb_sethw)(struct rtw89_dev *rtwdev);
@@ -3294,10 +3364,17 @@ struct rtw89_txpwr_rule_6ghz {
[RTW89_6G_CH_NUM];
};
+struct rtw89_tx_shape {
+ const u8 (*lmt)[RTW89_BAND_NUM][RTW89_RS_TX_SHAPE_NUM][RTW89_REGD_NUM];
+ const u8 (*lmt_ru)[RTW89_BAND_NUM][RTW89_REGD_NUM];
+};
+
struct rtw89_rfe_parms {
+ const struct rtw89_txpwr_table *byr_tbl;
struct rtw89_txpwr_rule_2ghz rule_2ghz;
struct rtw89_txpwr_rule_5ghz rule_5ghz;
struct rtw89_txpwr_rule_6ghz rule_6ghz;
+ struct rtw89_tx_shape tx_shape;
};
struct rtw89_rfe_parms_conf {
@@ -3305,6 +3382,95 @@ struct rtw89_rfe_parms_conf {
u8 rfe_type;
};
+#define RTW89_TXPWR_CONF_DFLT_RFE_TYPE 0x0
+
+struct rtw89_txpwr_conf {
+ u8 rfe_type;
+ u8 ent_sz;
+ u32 num_ents;
+ const void *data;
+};
+
+#define rtw89_txpwr_conf_valid(conf) (!!(conf)->data)
+
+#define rtw89_for_each_in_txpwr_conf(entry, cursor, conf) \
+ for (typecheck(const void *, cursor), (cursor) = (conf)->data, \
+ memcpy(&(entry), cursor, \
+ min_t(u8, sizeof(entry), (conf)->ent_sz)); \
+ (cursor) < (conf)->data + (conf)->num_ents * (conf)->ent_sz; \
+ (cursor) += (conf)->ent_sz, \
+ memcpy(&(entry), cursor, \
+ min_t(u8, sizeof(entry), (conf)->ent_sz)))
+
+struct rtw89_txpwr_byrate_data {
+ struct rtw89_txpwr_conf conf;
+ struct rtw89_txpwr_table tbl;
+};
+
+struct rtw89_txpwr_lmt_2ghz_data {
+ struct rtw89_txpwr_conf conf;
+ s8 v[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
+ [RTW89_RS_LMT_NUM][RTW89_BF_NUM]
+ [RTW89_REGD_NUM][RTW89_2G_CH_NUM];
+};
+
+struct rtw89_txpwr_lmt_5ghz_data {
+ struct rtw89_txpwr_conf conf;
+ s8 v[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
+ [RTW89_RS_LMT_NUM][RTW89_BF_NUM]
+ [RTW89_REGD_NUM][RTW89_5G_CH_NUM];
+};
+
+struct rtw89_txpwr_lmt_6ghz_data {
+ struct rtw89_txpwr_conf conf;
+ s8 v[RTW89_6G_BW_NUM][RTW89_NTX_NUM]
+ [RTW89_RS_LMT_NUM][RTW89_BF_NUM]
+ [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER]
+ [RTW89_6G_CH_NUM];
+};
+
+struct rtw89_txpwr_lmt_ru_2ghz_data {
+ struct rtw89_txpwr_conf conf;
+ s8 v[RTW89_RU_NUM][RTW89_NTX_NUM]
+ [RTW89_REGD_NUM][RTW89_2G_CH_NUM];
+};
+
+struct rtw89_txpwr_lmt_ru_5ghz_data {
+ struct rtw89_txpwr_conf conf;
+ s8 v[RTW89_RU_NUM][RTW89_NTX_NUM]
+ [RTW89_REGD_NUM][RTW89_5G_CH_NUM];
+};
+
+struct rtw89_txpwr_lmt_ru_6ghz_data {
+ struct rtw89_txpwr_conf conf;
+ s8 v[RTW89_RU_NUM][RTW89_NTX_NUM]
+ [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER]
+ [RTW89_6G_CH_NUM];
+};
+
+struct rtw89_tx_shape_lmt_data {
+ struct rtw89_txpwr_conf conf;
+ u8 v[RTW89_BAND_NUM][RTW89_RS_TX_SHAPE_NUM][RTW89_REGD_NUM];
+};
+
+struct rtw89_tx_shape_lmt_ru_data {
+ struct rtw89_txpwr_conf conf;
+ u8 v[RTW89_BAND_NUM][RTW89_REGD_NUM];
+};
+
+struct rtw89_rfe_data {
+ struct rtw89_txpwr_byrate_data byrate;
+ struct rtw89_txpwr_lmt_2ghz_data lmt_2ghz;
+ struct rtw89_txpwr_lmt_5ghz_data lmt_5ghz;
+ struct rtw89_txpwr_lmt_6ghz_data lmt_6ghz;
+ struct rtw89_txpwr_lmt_ru_2ghz_data lmt_ru_2ghz;
+ struct rtw89_txpwr_lmt_ru_5ghz_data lmt_ru_5ghz;
+ struct rtw89_txpwr_lmt_ru_6ghz_data lmt_ru_6ghz;
+ struct rtw89_tx_shape_lmt_data tx_shape_lmt;
+ struct rtw89_tx_shape_lmt_ru_data tx_shape_lmt_ru;
+ struct rtw89_rfe_parms rfe_parms;
+};
+
struct rtw89_page_regs {
u32 hci_fc_ctrl;
u32 ch_page_ctrl;
@@ -3428,6 +3594,7 @@ enum rtw89_chanctx_state {
enum rtw89_chanctx_callbacks {
RTW89_CHANCTX_CALLBACK_PLACEHOLDER,
+ RTW89_CHANCTX_CALLBACK_RFK,
NUM_OF_RTW89_CHANCTX_CALLBACKS,
};
@@ -3446,6 +3613,7 @@ struct rtw89_chip_info {
const char *fw_basename;
u8 fw_format_max;
bool try_ce_fw;
+ u8 bbmcu_nr;
u32 needed_fw_elms;
u32 fifo_size;
bool small_fifo_size;
@@ -3462,7 +3630,8 @@ struct rtw89_chip_info {
u8 support_bands;
bool support_bw160;
bool support_unii4;
- bool support_ul_tb_ctrl;
+ bool ul_tb_waveform_ctrl;
+ bool ul_tb_pwr_diff;
bool hw_sec_hdr;
u8 rf_path_num;
u8 tx_nss;
@@ -3490,7 +3659,6 @@ struct rtw89_chip_info {
const struct rtw89_phy_table *rf_table[RF_PATH_MAX];
const struct rtw89_phy_table *nctl_table;
const struct rtw89_rfk_tbl *nctl_post_table;
- const struct rtw89_txpwr_table *byr_table;
const struct rtw89_phy_dig_gain_table *dig_table;
const struct rtw89_dig_regs *dig_regs;
const struct rtw89_phy_tssi_dbw_table *tssi_dbw_table;
@@ -3527,6 +3695,7 @@ struct rtw89_chip_info {
u32 hci_func_en_addr;
u32 h2c_desc_size;
u32 txwd_body_size;
+ u32 txwd_info_size;
u32 h2c_ctrl_reg;
const u32 *h2c_regs;
struct rtw89_reg_def h2c_counter_reg;
@@ -3610,6 +3779,14 @@ struct rtw89_mac_info {
struct rtw89_wait_info fw_ofld_wait;
};
+enum rtw89_fwdl_check_type {
+ RTW89_FWDL_CHECK_FREERTOS_DONE,
+ RTW89_FWDL_CHECK_WCPU_FWDL_DONE,
+ RTW89_FWDL_CHECK_DCPU_FWDL_DONE,
+ RTW89_FWDL_CHECK_BB0_FWDL_DONE,
+ RTW89_FWDL_CHECK_BB1_FWDL_DONE,
+};
+
enum rtw89_fw_type {
RTW89_FW_NORMAL = 1,
RTW89_FW_WOWLAN = 3,
@@ -3776,6 +3953,17 @@ struct rtw89_chanctx_cfg {
enum rtw89_sub_entity_idx idx;
};
+enum rtw89_chanctx_changes {
+ RTW89_CHANCTX_REMOTE_STA_CHANGE,
+ RTW89_CHANCTX_BCN_OFFSET_CHANGE,
+ RTW89_CHANCTX_P2P_PS_CHANGE,
+ RTW89_CHANCTX_BT_SLOT_CHANGE,
+ RTW89_CHANCTX_TSF32_TOGGLE_CHANGE,
+
+ NUM_OF_RTW89_CHANCTX_CHANGES,
+ RTW89_CHANCTX_CHANGE_DFLT = NUM_OF_RTW89_CHANCTX_CHANGES,
+};
+
enum rtw89_entity_mode {
RTW89_ENTITY_MODE_SCC,
RTW89_ENTITY_MODE_MCC_PREPARE,
@@ -3807,11 +3995,13 @@ struct rtw89_hal {
bool support_igi;
atomic_t roc_entity_idx;
+ DECLARE_BITMAP(changes, NUM_OF_RTW89_CHANCTX_CHANGES);
DECLARE_BITMAP(entity_map, NUM_OF_RTW89_SUB_ENTITY);
struct rtw89_sub_entity sub[NUM_OF_RTW89_SUB_ENTITY];
struct cfg80211_chan_def roc_chandef;
bool entity_active;
+ bool entity_pause;
enum rtw89_entity_mode entity_mode;
u32 edcca_bak;
@@ -4357,8 +4547,95 @@ struct rtw89_wow_param {
u8 pattern_cnt;
};
+struct rtw89_mcc_limit {
+ bool enable;
+ u16 max_tob; /* TU; max time offset behind */
+ u16 max_toa; /* TU; max time offset ahead */
+ u16 max_dur; /* TU */
+};
+
+struct rtw89_mcc_policy {
+ u8 c2h_rpt;
+ u8 tx_null_early;
+ u8 dis_tx_null;
+ u8 in_curr_ch;
+ u8 dis_sw_retry;
+ u8 sw_retry_count;
+};
+
+struct rtw89_mcc_role {
+ struct rtw89_vif *rtwvif;
+ struct rtw89_mcc_policy policy;
+ struct rtw89_mcc_limit limit;
+
+ /* byte-array in LE order for FW */
+ u8 macid_bitmap[BITS_TO_BYTES(RTW89_MAX_MAC_ID_NUM)];
+
+ u16 duration; /* TU */
+ u16 beacon_interval; /* TU */
+ bool is_2ghz;
+ bool is_go;
+ bool is_gc;
+};
+
+struct rtw89_mcc_bt_role {
+ u16 duration; /* TU */
+};
+
+struct rtw89_mcc_courtesy {
+ bool enable;
+ u8 slot_num;
+ u8 macid_src;
+ u8 macid_tgt;
+};
+
+enum rtw89_mcc_plan {
+ RTW89_MCC_PLAN_TAIL_BT,
+ RTW89_MCC_PLAN_MID_BT,
+ RTW89_MCC_PLAN_NO_BT,
+
+ NUM_OF_RTW89_MCC_PLAN,
+};
+
+struct rtw89_mcc_pattern {
+ s16 tob_ref; /* TU; time offset behind of reference role */
+ s16 toa_ref; /* TU; time offset ahead of reference role */
+ s16 tob_aux; /* TU; time offset behind of auxiliary role */
+ s16 toa_aux; /* TU; time offset ahead of auxiliary role */
+
+ enum rtw89_mcc_plan plan;
+ struct rtw89_mcc_courtesy courtesy;
+};
+
+struct rtw89_mcc_sync {
+ bool enable;
+ u16 offset; /* TU */
+ u8 macid_src;
+ u8 macid_tgt;
+};
+
+struct rtw89_mcc_config {
+ struct rtw89_mcc_pattern pattern;
+ struct rtw89_mcc_sync sync;
+ u64 start_tsf;
+ u16 mcc_interval; /* TU */
+ u16 beacon_offset; /* TU */
+};
+
+enum rtw89_mcc_mode {
+ RTW89_MCC_MODE_GO_STA,
+ RTW89_MCC_MODE_GC_STA,
+};
+
struct rtw89_mcc_info {
struct rtw89_wait_info wait;
+
+ u8 group;
+ enum rtw89_mcc_mode mode;
+ struct rtw89_mcc_role role_ref; /* reference role */
+ struct rtw89_mcc_role role_aux; /* auxiliary role */
+ struct rtw89_mcc_bt_role bt_role;
+ struct rtw89_mcc_config config;
};
struct rtw89_dev {
@@ -4378,6 +4655,7 @@ struct rtw89_dev {
struct rtw89_hci_info hci;
struct rtw89_efuse efuse;
struct rtw89_traffic_stats stats;
+ struct rtw89_rfe_data *rfe_data;
/* ensures exclusive access from mac80211 callbacks */
struct mutex mutex;
@@ -4425,7 +4703,7 @@ struct rtw89_dev {
bool is_bt_iqk_timeout;
struct rtw89_fem_info fem;
- struct rtw89_txpwr_byrate byr[RTW89_BAND_NUM];
+ struct rtw89_txpwr_byrate byr[RTW89_BAND_NUM][RTW89_BYR_BW_NUM];
struct rtw89_tssi_info tssi;
struct rtw89_power_trim_info pwr_trim;
@@ -4911,6 +5189,30 @@ enum rtw89_bandwidth nl_to_rtw89_bandwidth(enum nl80211_chan_width width)
}
static inline
+enum nl80211_he_ru_alloc rtw89_he_rua_to_ru_alloc(u16 rua)
+{
+ switch (rua) {
+ default:
+ WARN(1, "Invalid RU allocation: %d\n", rua);
+ fallthrough;
+ case 0 ... 36:
+ return NL80211_RATE_INFO_HE_RU_ALLOC_26;
+ case 37 ... 52:
+ return NL80211_RATE_INFO_HE_RU_ALLOC_52;
+ case 53 ... 60:
+ return NL80211_RATE_INFO_HE_RU_ALLOC_106;
+ case 61 ... 64:
+ return NL80211_RATE_INFO_HE_RU_ALLOC_242;
+ case 65 ... 66:
+ return NL80211_RATE_INFO_HE_RU_ALLOC_484;
+ case 67:
+ return NL80211_RATE_INFO_HE_RU_ALLOC_996;
+ case 68:
+ return NL80211_RATE_INFO_HE_RU_ALLOC_2x996;
+ }
+}
+
+static inline
struct rtw89_addr_cam_entry *rtw89_get_addr_cam_of(struct rtw89_vif *rtwvif,
struct rtw89_sta *rtwsta)
{
@@ -5017,6 +5319,15 @@ static inline void rtw89_chip_rfe_gpio(struct rtw89_dev *rtwdev)
chip->ops->rfe_gpio(rtwdev);
}
+static inline
+void rtw89_chip_bb_preinit(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx)
+{
+ const struct rtw89_chip_info *chip = rtwdev->chip;
+
+ if (chip->ops->bb_preinit)
+ chip->ops->bb_preinit(rtwdev, phy_idx);
+}
+
static inline void rtw89_chip_bb_sethw(struct rtw89_dev *rtwdev)
{
const struct rtw89_chip_info *chip = rtwdev->chip;
@@ -5333,15 +5644,24 @@ void rtw89_core_fill_txdesc(struct rtw89_dev *rtwdev,
void rtw89_core_fill_txdesc_v1(struct rtw89_dev *rtwdev,
struct rtw89_tx_desc_info *desc_info,
void *txdesc);
+void rtw89_core_fill_txdesc_v2(struct rtw89_dev *rtwdev,
+ struct rtw89_tx_desc_info *desc_info,
+ void *txdesc);
void rtw89_core_fill_txdesc_fwcmd_v1(struct rtw89_dev *rtwdev,
struct rtw89_tx_desc_info *desc_info,
void *txdesc);
+void rtw89_core_fill_txdesc_fwcmd_v2(struct rtw89_dev *rtwdev,
+ struct rtw89_tx_desc_info *desc_info,
+ void *txdesc);
void rtw89_core_rx(struct rtw89_dev *rtwdev,
struct rtw89_rx_desc_info *desc_info,
struct sk_buff *skb);
void rtw89_core_query_rxdesc(struct rtw89_dev *rtwdev,
struct rtw89_rx_desc_info *desc_info,
u8 *data, u32 data_offset);
+void rtw89_core_query_rxdesc_v2(struct rtw89_dev *rtwdev,
+ struct rtw89_rx_desc_info *desc_info,
+ u8 *data, u32 data_offset);
void rtw89_core_napi_start(struct rtw89_dev *rtwdev);
void rtw89_core_napi_stop(struct rtw89_dev *rtwdev);
void rtw89_core_napi_init(struct rtw89_dev *rtwdev);
@@ -5410,6 +5730,7 @@ void rtw89_core_scan_complete(struct rtw89_dev *rtwdev,
struct ieee80211_vif *vif, bool hw_scan);
void rtw89_reg_6ghz_power_recalc(struct rtw89_dev *rtwdev,
struct rtw89_vif *rtwvif, bool active);
+void rtw89_core_update_p2p_ps(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif);
void rtw89_core_ntfy_btc_event(struct rtw89_dev *rtwdev, enum rtw89_btc_hmsg event);
#endif
generated by cgit v1.2.3 (git 2.39.0) at 2024-07-13 08:26:48 +0300