diff options
Diffstat (limited to 'drivers/net/wireless/realtek/rtw89/reg.h')
| -rw-r--r-- | drivers/net/wireless/realtek/rtw89/reg.h | 405 |
1 files changed, 403 insertions, 2 deletions
diff --git a/drivers/net/wireless/realtek/rtw89/reg.h b/drivers/net/wireless/realtek/rtw89/reg.h index c0aac4d3678a..2bf3c1bed6a2 100644 --- a/drivers/net/wireless/realtek/rtw89/reg.h +++ b/drivers/net/wireless/realtek/rtw89/reg.h @@ -3360,9 +3360,11 @@ #define R_AX_PWR_UL_TB_1T 0xD28C #define B_AX_PWR_UL_TB_1T_MASK GENMASK(4, 0) #define B_AX_PWR_UL_TB_1T_V1_MASK GENMASK(7, 0) +#define B_AX_PWR_UL_TB_1T_NORM_BW160 GENMASK(31, 24) #define R_AX_PWR_UL_TB_2T 0xD290 #define B_AX_PWR_UL_TB_2T_MASK GENMASK(4, 0) #define B_AX_PWR_UL_TB_2T_V1_MASK GENMASK(7, 0) +#define B_AX_PWR_UL_TB_2T_NORM_BW160 GENMASK(31, 24) #define R_AX_PWR_BY_RATE_TABLE0 0xD2C0 #define R_AX_PWR_BY_RATE_TABLE6 0xD2D8 #define R_AX_PWR_BY_RATE_TABLE10 0xD2E8 @@ -3390,11 +3392,13 @@ #define AX_PATH_COM0_PATHB 0x11111900 #define AX_PATH_COM0_PATHAB 0x19999980 #define R_AX_PATH_COM1 0xD804 +#define B_AX_PATH_COM1_NORM_1STS GENMASK(31, 28) #define AX_PATH_COM1_DFVAL 0x00000000 #define AX_PATH_COM1_PATHA 0x13111111 #define AX_PATH_COM1_PATHB 0x23222222 #define AX_PATH_COM1_PATHAB 0x33333333 #define R_AX_PATH_COM2 0xD808 +#define B_AX_PATH_COM2_RESP_1STS_PATH GENMASK(7, 4) #define AX_PATH_COM2_DFVAL 0x00000000 #define AX_PATH_COM2_PATHA 0x01209313 #define AX_PATH_COM2_PATHB 0x01209323 @@ -3581,8 +3585,8 @@ #define R_AX_MACID_ANT_TABLE 0xDC00 #define R_AX_MACID_ANT_TABLE_LAST 0xDDFC -#define CMAC1_START_ADDR 0xE000 -#define CMAC1_END_ADDR 0xFFFF +#define CMAC1_START_ADDR_AX 0xE000 +#define CMAC1_END_ADDR_AX 0xFFFF #define R_AX_CMAC_REG_END 0xFFFF #define R_AX_LTE_SW_CFG_1 0x0038 @@ -3625,8 +3629,369 @@ #define B_AX_GNT_BT_TX_SW_VAL BIT(1) #define B_AX_GNT_BT_TX_SW_CTRL BIT(0) +#define R_BE_SYS_CLK_CTRL 0x0008 +#define B_BE_CPU_CLK_EN BIT(14) +#define B_BE_SYMR_BE_CLK_EN BIT(13) +#define B_BE_MAC_CLK_EN BIT(11) +#define B_BE_EXT_32K_EN BIT(8) +#define B_BE_WL_CLK_TEST BIT(7) +#define B_BE_LOADER_CLK_EN BIT(5) +#define B_BE_ANA_CLK_DIVISION_2 BIT(1) +#define B_BE_CNTD16V_EN BIT(0) + +#define R_BE_PLATFORM_ENABLE 0x0088 +#define B_BE_HOLD_AFTER_RESET BIT(11) +#define B_BE_SYM_WLPLT_MEM_MUX_EN BIT(10) +#define B_BE_WCPU_WARM_EN BIT(9) +#define B_BE_SPIC_EN BIT(8) +#define B_BE_UART_EN BIT(7) +#define B_BE_IDDMA_EN BIT(6) +#define B_BE_IPSEC_EN BIT(5) +#define B_BE_HIOE_EN BIT(4) +#define B_BE_APB_WRAP_EN BIT(2) +#define B_BE_WCPU_EN BIT(1) +#define B_BE_PLATFORM_EN BIT(0) + +#define R_BE_HALT_H2C_CTRL 0x0160 +#define B_BE_HALT_H2C_TRIGGER BIT(0) + +#define R_BE_HALT_C2H_CTRL 0x0164 +#define B_BE_HALT_C2H_TRIGGER BIT(0) + +#define R_BE_HALT_H2C 0x0168 +#define B_BE_HALT_H2C_MASK GENMASK(31, 0) + +#define R_BE_HALT_C2H 0x016C +#define B_BE_HALT_C2H_ERROR_SENARIO_MASK GENMASK(31, 28) +#define B_BE_ERROR_CODE_MASK GENMASK(15, 0) + +#define R_BE_SYS_CFG5 0x0170 +#define B_BE_WDT_DATACPU_WAKE_PCIE_EN BIT(12) +#define B_BE_WDT_DATACPU_WAKE_USB_EN BIT(11) +#define B_BE_WDT_WAKE_PCIE_EN BIT(10) +#define B_BE_WDT_WAKE_USB_EN BIT(9) +#define B_BE_SYM_DIS_HC_ACCESS_MAC BIT(8) +#define B_BE_LPS_STATUS BIT(3) +#define B_BE_HCI_TXDMA_BUSY BIT(2) + +#define R_BE_SECURE_BOOT_MALLOC_INFO 0x0184 + +#define R_BE_WCPU_FW_CTRL 0x01E0 +#define B_BE_RUN_ENV_MASK GENMASK(31, 30) +#define B_BE_WCPU_FWDL_STATUS_MASK GENMASK(29, 26) +#define B_BE_WDT_PLT_RST_EN BIT(17) +#define B_BE_FW_SEC_AUTH_DONE BIT(14) +#define B_BE_FW_CPU_UTIL_STS_EN BIT(13) +#define B_BE_BBMCU1_FWDL_EN BIT(12) +#define B_BE_BBMCU0_FWDL_EN BIT(11) +#define B_BE_DATACPU_FWDL_EN BIT(10) +#define B_BE_WLANCPU_FWDL_EN BIT(9) +#define B_BE_WCPU_ROM_CUT_GET BIT(8) +#define B_BE_WCPU_ROM_CUT_VAL_MASK GENMASK(7, 4) +#define B_BE_FW_BOOT_MODE_MASK GENMASK(3, 2) +#define B_BE_H2C_PATH_RDY BIT(1) +#define B_BE_DLFW_PATH_RDY BIT(0) + +#define R_BE_BOOT_REASON 0x01E6 +#define B_BE_BOOT_REASON_MASK GENMASK(2, 0) + +#define R_BE_LDM 0x01E8 +#define B_BE_EN_32K BIT(31) +#define B_BE_LDM_MASK GENMASK(30, 0) + +#define R_BE_UDM0 0x01F0 +#define B_BE_UDM0_SEND2RA_CNT_MASK GENMASK(31, 28) +#define B_BE_UDM0_TX_RPT_CNT_MASK GENMASK(27, 24) +#define B_BE_UDM0_FS_CODE_MASK GENMASK(23, 8) +#define B_BE_NULL_POINTER_INDC BIT(7) +#define B_BE_ROM_ASSERT_INDC BIT(6) +#define B_BE_RAM_ASSERT_INDC BIT(5) +#define B_BE_FW_IMAGE_TYPE BIT(4) +#define B_BE_UDM0_TRAP_LOOP_CTRL BIT(2) +#define B_BE_UDM0_SEND_HALTC2H_CTRL BIT(1) +#define B_BE_UDM0_DBG_MODE_CTRL BIT(0) + +#define R_BE_UDM1 0x01F4 +#define B_BE_UDM1_ERROR_ADDR_MASK GENMASK(31, 16) +#define B_BE_UDM1_HALMAC_C2H_ENQ_CNT_MASK GENMASK(15, 12) +#define B_BE_UDM1_HALMAC_H2C_DEQ_CNT_MASK GENMASK(11, 8) +#define B_BE_UDM1_WCPU_C2H_ENQ_CNT_MASK GENMASK(7, 4) +#define B_BE_UDM1_WCPU_H2C_DEQ_CNT_MASK GENMASK(3, 0) + +#define R_BE_UDM2 0x01F8 +#define B_BE_UDM2_EPC_RA_MASK GENMASK(31, 0) + +#define R_BE_DCPU_PLATFORM_ENABLE 0x0888 +#define B_BE_DCPU_SYM_DPLT_MEM_MUX_EN BIT(10) +#define B_BE_DCPU_WARM_EN BIT(9) +#define B_BE_DCPU_UART_EN BIT(7) +#define B_BE_DCPU_IDDMA_EN BIT(6) +#define B_BE_DCPU_APB_WRAP_EN BIT(2) +#define B_BE_DCPU_EN BIT(1) +#define B_BE_DCPU_PLATFORM_EN BIT(0) + #define R_BE_FILTER_MODEL_ADDR 0x0C04 +#define R_BE_PLE_DBG_FUN_INTF_CTL 0x9110 +#define B_BE_PLE_DFI_ACTIVE BIT(31) +#define B_BE_PLE_DFI_TRGSEL_MASK GENMASK(19, 16) +#define B_BE_PLE_DFI_ADDR_MASK GENMASK(15, 0) + +#define R_BE_PLE_DBG_FUN_INTF_DATA 0x9114 +#define B_BE_PLE_DFI_DATA_MASK GENMASK(31, 0) + +#define R_BE_CMAC_FUNC_EN 0x10000 +#define R_BE_CMAC_FUNC_EN_C1 0x14000 +#define B_BE_CMAC_CRPRT BIT(31) +#define B_BE_CMAC_EN BIT(30) +#define B_BE_CMAC_TXEN BIT(29) +#define B_BE_CMAC_RXEN BIT(28) +#define B_BE_FORCE_RESP_PKTCTL_GCKEN BIT(26) +#define B_BE_FORCE_SIGB_REG_GCKEN BIT(25) +#define B_BE_FORCE_POWER_REG_GCKEN BIT(23) +#define B_BE_FORCE_RMAC_REG_GCKEN BIT(22) +#define B_BE_FORCE_TRXPTCL_REG_GCKEN BIT(21) +#define B_BE_FORCE_TMAC_REG_GCKEN BIT(20) +#define B_BE_FORCE_CMAC_DMA_REG_GCKEN BIT(19) +#define B_BE_FORCE_PTCL_REG_GCKEN BIT(18) +#define B_BE_FORCE_SCHEDULER_RREG_GCKEN BIT(17) +#define B_BE_FORCE_CMAC_COMMON_REG_GCKEN BIT(16) +#define B_BE_FORCE_CMACREG_GCKEN BIT(15) +#define B_BE_TXTIME_EN BIT(8) +#define B_BE_RESP_PKTCTL_EN BIT(7) +#define B_BE_SIGB_EN BIT(6) +#define B_BE_PHYINTF_EN BIT(5) +#define B_BE_CMAC_DMA_EN BIT(4) +#define B_BE_PTCLTOP_EN BIT(3) +#define B_BE_SCHEDULER_EN BIT(2) +#define B_BE_TMAC_EN BIT(1) +#define B_BE_RMAC_EN BIT(0) +#define B_BE_CMAC_FUNC_EN_SET (B_BE_CMAC_EN | B_BE_CMAC_TXEN | B_BE_CMAC_RXEN | \ + B_BE_PHYINTF_EN | B_BE_CMAC_DMA_EN | B_BE_PTCLTOP_EN | \ + B_BE_SCHEDULER_EN | B_BE_TMAC_EN | B_BE_RMAC_EN | \ + B_BE_CMAC_CRPRT | B_BE_TXTIME_EN | B_BE_RESP_PKTCTL_EN | \ + B_BE_SIGB_EN) + +#define R_BE_PORT_0_TSF_SYNC 0x102A0 +#define R_BE_PORT_0_TSF_SYNC_C1 0x142A0 +#define B_BE_P0_SYNC_NOW_P BIT(30) +#define B_BE_P0_SYNC_ONCE_P BIT(29) +#define B_BE_P0_AUTO_SYNC BIT(28) +#define B_BE_P0_SYNC_PORT_SRC_SEL_MASK GENMASK(26, 24) +#define B_BE_P0_TSFTR_SYNC_OFFSET_MASK GENMASK(18, 0) + +#define R_BE_MUEDCA_BE_PARAM_0 0x10350 +#define R_BE_MUEDCA_BK_PARAM_0 0x10354 +#define R_BE_MUEDCA_VI_PARAM_0 0x10358 +#define R_BE_MUEDCA_VO_PARAM_0 0x1035C + +#define R_BE_MUEDCA_EN 0x10370 +#define R_BE_MUEDCA_EN_C1 0x14370 +#define B_BE_MUEDCA_WMM_SEL BIT(8) +#define B_BE_SET_MUEDCATIMER_TF_1 BIT(5) +#define B_BE_SET_MUEDCATIMER_TF_0 BIT(4) +#define B_BE_MUEDCA_EN_0 BIT(0) + +#define R_BE_PORT_CFG_P0 0x10400 +#define R_BE_PORT_CFG_P0_C1 0x14400 +#define B_BE_BCN_ERLY_SORT_EN_P0 BIT(18) +#define B_BE_PROHIB_END_CAL_EN_P0 BIT(17) +#define B_BE_BRK_SETUP_P0 BIT(16) +#define B_BE_TBTT_UPD_SHIFT_SEL_P0 BIT(15) +#define B_BE_BCN_DROP_ALLOW_P0 BIT(14) +#define B_BE_TBTT_PROHIB_EN_P0 BIT(13) +#define B_BE_BCNTX_EN_P0 BIT(12) +#define B_BE_NET_TYPE_P0_MASK GENMASK(11, 10) +#define B_BE_BCN_FORCETX_EN_P0 BIT(9) +#define B_BE_TXBCN_BTCCA_EN_P0 BIT(8) +#define B_BE_BCNERR_CNT_EN_P0 BIT(7) +#define B_BE_BCN_AGRES_P0 BIT(6) +#define B_BE_TSFTR_RST_P0 BIT(5) +#define B_BE_RX_BSSID_FIT_EN_P0 BIT(4) +#define B_BE_TSF_UDT_EN_P0 BIT(3) +#define B_BE_PORT_FUNC_EN_P0 BIT(2) +#define B_BE_TXBCN_RPT_EN_P0 BIT(1) +#define B_BE_RXBCN_RPT_EN_P0 BIT(0) + +#define R_BE_TBTT_PROHIB_P0 0x10404 +#define R_BE_TBTT_PROHIB_P0_C1 0x14404 +#define B_BE_TBTT_HOLD_P0_MASK GENMASK(27, 16) +#define B_BE_TBTT_SETUP_P0_MASK GENMASK(7, 0) + +#define R_BE_BCN_AREA_P0 0x10408 +#define R_BE_BCN_AREA_P0_C1 0x14408 +#define B_BE_BCN_MSK_AREA_P0_MSK 0xfff +#define B_BE_BCN_CTN_AREA_P0_MASK GENMASK(11, 0) + +#define R_BE_BCNERLYINT_CFG_P0 0x1040C +#define R_BE_BCNERLYINT_CFG_P0_C1 0x1440C +#define B_BE_BCNERLY_P0_MASK GENMASK(11, 0) + +#define R_BE_TBTTERLYINT_CFG_P0 0x1040E +#define R_BE_TBTTERLYINT_CFG_P0_C1 0x1440E +#define B_BE_TBTTERLY_P0_MASK GENMASK(11, 0) + +#define R_BE_TBTT_AGG_P0 0x10412 +#define R_BE_TBTT_AGG_P0_C1 0x14412 +#define B_BE_TBTT_AGG_NUM_P0_MASK GENMASK(15, 8) + +#define R_BE_BCN_SPACE_CFG_P0 0x10414 +#define R_BE_BCN_SPACE_CFG_P0_C1 0x14414 +#define B_BE_SUB_BCN_SPACE_P0_MASK GENMASK(23, 16) +#define B_BE_BCN_SPACE_P0_MASK GENMASK(15, 0) + +#define R_BE_BCN_FORCETX_P0 0x10418 +#define R_BE_BCN_FORCETX_P0_C1 0x14418 +#define B_BE_FORCE_BCN_NUM_P0_MASK GENMASK(15, 8) +#define B_BE_BCN_MAX_ERR_P0_MASK GENMASK(7, 0) + +#define R_BE_BCN_ERR_CNT_P0 0x10420 +#define R_BE_BCN_ERR_CNT_P0_C1 0x14420 +#define B_BE_BCN_ERR_CNT_SUM_P0_MASK GENMASK(31, 24) +#define B_BE_BCN_ERR_CNT_NAV_P0_MASK GENMASK(23, 16) +#define B_BE_BCN_ERR_CNT_EDCCA_P0_MASK GENMASK(15, 8) +#define B_BE_BCN_ERR_CNT_CCA_P0_MASK GENMASK(7, 0) + +#define R_BE_BCN_ERR_FLAG_P0 0x10424 +#define R_BE_BCN_ERR_FLAG_P0_C1 0x14424 +#define B_BE_BCN_ERR_FLAG_SRCHEND_P0 BIT(3) +#define B_BE_BCN_ERR_FLAG_INVALID_P0 BIT(2) +#define B_BE_BCN_ERR_FLAG_CMP_P0 BIT(1) +#define B_BE_BCN_ERR_FLAG_LOCK_P0 BIT(0) + +#define R_BE_DTIM_CTRL_P0 0x10426 +#define R_BE_DTIM_CTRL_P0_C1 0x14426 +#define B_BE_DTIM_NUM_P0_MASK GENMASK(15, 8) +#define B_BE_DTIM_CURRCNT_P0_MASK GENMASK(7, 0) + +#define R_BE_TBTT_SHIFT_P0 0x10428 +#define R_BE_TBTT_SHIFT_P0_C1 0x14428 +#define B_BE_TBTT_SHIFT_OFST_P0_SH 0 +#define B_BE_TBTT_SHIFT_OFST_P0_MSK 0xfff + +#define R_BE_BCN_CNT_TMR_P0 0x10434 +#define R_BE_BCN_CNT_TMR_P0_C1 0x14434 +#define B_BE_BCN_CNT_TMR_P0_MASK GENMASK(31, 0) + +#define R_BE_TSFTR_LOW_P0 0x10438 +#define R_BE_TSFTR_LOW_P0_C1 0x14438 +#define B_BE_TSFTR_LOW_P0_MASK GENMASK(31, 0) + +#define R_BE_TSFTR_HIGH_P0 0x1043C +#define R_BE_TSFTR_HIGH_P0_C1 0x1443C +#define B_BE_TSFTR_HIGH_P0_MASK GENMASK(31, 0) + +#define R_BE_MBSSID_CTRL 0x10568 +#define R_BE_MBSSID_CTRL_C1 0x14568 +#define B_BE_MBSSID_MODE_SEL BIT(20) +#define B_BE_P0MB_NUM_MASK GENMASK(19, 16) +#define B_BE_P0MB15_EN BIT(15) +#define B_BE_P0MB14_EN BIT(14) +#define B_BE_P0MB13_EN BIT(13) +#define B_BE_P0MB12_EN BIT(12) +#define B_BE_P0MB11_EN BIT(11) +#define B_BE_P0MB10_EN BIT(10) +#define B_BE_P0MB9_EN BIT(9) +#define B_BE_P0MB8_EN BIT(8) +#define B_BE_P0MB7_EN BIT(7) +#define B_BE_P0MB6_EN BIT(6) +#define B_BE_P0MB5_EN BIT(5) +#define B_BE_P0MB4_EN BIT(4) +#define B_BE_P0MB3_EN BIT(3) +#define B_BE_P0MB2_EN BIT(2) +#define B_BE_P0MB1_EN BIT(1) + +#define R_BE_P0MB_HGQ_WINDOW_CFG_0 0x10590 +#define R_BE_P0MB_HGQ_WINDOW_CFG_0_C1 0x14590 +#define R_BE_PORT_HGQ_WINDOW_CFG 0x105A0 +#define R_BE_PORT_HGQ_WINDOW_CFG_C1 0x145A0 + +#define R_BE_AGG_LEN_HT_0 0x10814 +#define R_BE_AGG_LEN_HT_0_C1 0x14814 +#define B_BE_AMPDU_MAX_LEN_HT_MASK GENMASK(31, 16) +#define B_BE_RTS_TXTIME_TH_MASK GENMASK(15, 8) +#define B_BE_RTS_LEN_TH_MASK GENMASK(7, 0) + +#define R_BE_MBSSID_DROP_0 0x1083C +#define R_BE_MBSSID_DROP_0_C1 0x1483C +#define B_BE_GI_LTF_FB_SEL BIT(30) +#define B_BE_RATE_SEL_MASK GENMASK(29, 24) +#define B_BE_PORT_DROP_4_0_MASK GENMASK(20, 16) +#define B_BE_MBSSID_DROP_15_0_MASK GENMASK(15, 0) + +#define R_BE_PTCL_BSS_COLOR_0 0x108A0 +#define R_BE_PTCL_BSS_COLOR_0_C1 0x148A0 +#define B_BE_BSS_COLOB_BE_PORT_3_MASK GENMASK(29, 24) +#define B_BE_BSS_COLOB_BE_PORT_2_MASK GENMASK(21, 16) +#define B_BE_BSS_COLOB_BE_PORT_1_MASK GENMASK(13, 8) +#define B_BE_BSS_COLOB_BE_PORT_0_MASK GENMASK(5, 0) + +#define R_BE_PTCL_BSS_COLOR_1 0x108A4 +#define R_BE_PTCL_BSS_COLOR_1_C1 0x148A4 +#define B_BE_BSS_COLOB_BE_PORT_4_MASK GENMASK(5, 0) + +#define R_BE_WMTX_MOREDATA_TSFT_STMP_CTL 0x10E08 +#define R_BE_WMTX_MOREDATA_TSFT_STMP_CTL_C1 0x14E08 +#define B_BE_TSFT_OFS_MASK GENMASK(31, 16) +#define B_BE_STMP_THSD_MASK GENMASK(15, 8) +#define B_BE_UPD_HGQMD BIT(1) +#define B_BE_UPD_TIMIE BIT(0) + +#define R_BE_BFMEE_RESP_OPTION 0x11180 +#define R_BE_BFMEE_RESP_OPTION_C1 0x15180 +#define B_BE_BFMEE_CSI_SEC_TYPE_SH 20 +#define B_BE_BFMEE_CSI_SEC_TYPE_MSK 0xf +#define B_BE_BFMEE_BFRPT_SEG_SIZE_SH 16 +#define B_BE_BFMEE_BFRPT_SEG_SIZE_MSK 0x3 +#define B_BE_BFMEE_MIMO_EN_SEL BIT(8) +#define B_BE_BFMEE_MU_BFEE_DIS BIT(7) +#define B_BE_BFMEE_CHECK_RPTPOLL_MACID_DIS BIT(6) +#define B_BE_BFMEE_NOCHK_BFPOLL_BMP BIT(5) +#define B_BE_BFMEE_VHTBFRPT_CHK BIT(4) +#define B_BE_BFMEE_EHT_NDPA_EN BIT(3) +#define B_BE_BFMEE_HE_NDPA_EN BIT(2) +#define B_BE_BFMEE_VHT_NDPA_EN BIT(1) +#define B_BE_BFMEE_HT_NDPA_EN BIT(0) + +#define R_BE_TRXPTCL_RESP_CSI_CTRL_0 0x11188 +#define R_BE_TRXPTCL_RESP_CSI_CTRL_0_C1 0x15188 +#define B_BE_BFMEE_CSISEQ_SEL BIT(29) +#define B_BE_BFMEE_BFPARAM_SEL BIT(28) +#define B_BE_BFMEE_OFDM_LEN_TH_MASK GENMASK(27, 24) +#define B_BE_BFMEE_BF_PORT_SEL BIT(23) +#define B_BE_BFMEE_USE_NSTS BIT(22) +#define B_BE_BFMEE_CSI_RATE_FB_EN BIT(21) +#define B_BE_BFMEE_CSI_GID_SEL BIT(20) +#define B_BE_BFMEE_CSI_RSC_MASK GENMASK(19, 18) +#define B_BE_BFMEE_CSI_FORCE_RETE_EN BIT(17) +#define B_BE_BFMEE_CSI_USE_NDPARATE BIT(16) +#define B_BE_BFMEE_CSI_WITHHTC_EN BIT(15) +#define B_BE_BFMEE_CSIINFO0_BF_EN BIT(14) +#define B_BE_BFMEE_CSIINFO0_STBC_EN BIT(13) +#define B_BE_BFMEE_CSIINFO0_LDPC_EN BIT(12) +#define B_BE_BFMEE_CSIINFO0_CS_MASK GENMASK(11, 10) +#define B_BE_BFMEE_CSIINFO0_CB_MASK GENMASK(9, 8) +#define B_BE_BFMEE_CSIINFO0_NG_MASK GENMASK(7, 6) +#define B_BE_BFMEE_CSIINFO0_NR_MASK GENMASK(5, 3) +#define B_BE_BFMEE_CSIINFO0_NC_MASK GENMASK(2, 0) +#define CSI_RX_BW_CFG 0x1 +#define R_BE_TRXPTCL_RESP_CSI_CTRL_1 0x11194 +#define R_BE_TRXPTCL_RESP_CSI_CTRL_1_C1 0x15194 +#define B_BE_BFMEE_BE_CSI_RRSC_BITMAP_MASK GENMASK(31, 24) +#define CSI_RRSC_BITMAP_CFG 0x2A + +#define R_BE_TRXPTCL_RESP_CSI_RRSC 0x1118C +#define R_BE_TRXPTCL_RESP_CSI_RRSC_C1 0x1518C +#define CSI_RRSC_BMAP_BE 0x2A2AFF + +#define R_BE_TRXPTCL_RESP_CSI_RATE 0x11190 +#define R_BE_TRXPTCL_RESP_CSI_RATE_C1 0x15190 +#define B_BE_BFMEE_EHT_CSI_RATE_MASK GENMASK(31, 24) +#define B_BE_BFMEE_HE_CSI_RATE_MASK GENMASK(23, 16) +#define B_BE_BFMEE_VHT_CSI_RATE_MASK GENMASK(15, 8) +#define B_BE_BFMEE_HT_CSI_RATE_MASK GENMASK(7, 0) +#define CSI_INIT_RATE_EHT 0x3 + #define R_BE_RX_FLTR_OPT 0x11420 #define R_BE_RX_FLTR_OPT_C1 0x15420 #define B_BE_UID_FILTER_MASK GENMASK(31, 24) @@ -3646,6 +4011,26 @@ #define B_BE_A_A1_MATCH BIT(1) #define B_BE_SNIFFER_MODE BIT(0) +#define R_BE_CSIRPT_OPTION 0x11464 +#define R_BE_CSIRPT_OPTION_C1 0x15464 +#define B_BE_CSIPRT_EHTSU_AID_EN BIT(26) +#define B_BE_CSIPRT_HESU_AID_EN BIT(25) +#define B_BE_CSIPRT_VHTSU_AID_EN BIT(24) + +#define R_BE_PWR_MODULE 0x11900 +#define R_BE_PWR_MODULE_C1 0x15900 + +#define R_BE_PWR_RATE_OFST_CTRL 0x11A30 +#define R_BE_PWR_BY_RATE 0x11E00 +#define R_BE_PWR_BY_RATE_MAX 0x11FA8 +#define R_BE_PWR_LMT 0x11FAC +#define R_BE_PWR_LMT_MAX 0x12040 +#define R_BE_PWR_RU_LMT 0x12048 +#define R_BE_PWR_RU_LMT_MAX 0x120E4 + +#define CMAC1_START_ADDR_BE 0x14000 +#define CMAC1_END_ADDR_BE 0x17FFF + #define RR_MOD 0x00 #define RR_MOD_V1 0x10000 #define RR_MOD_IQK GENMASK(19, 4) @@ -4413,12 +4798,20 @@ #define B_ANT_RX_1RCCA_SEG1 GENMASK(21, 18) #define B_ANT_RX_1RCCA_SEG0 GENMASK(17, 14) #define B_FC0_BW_INV GENMASK(6, 0) +#define R_Q_MATRIX_00 0x497C +#define B_Q_MATRIX_00_IMAGINARY GENMASK(15, 0) +#define B_Q_MATRIX_00_REAL GENMASK(31, 16) #define R_CHBW_MOD 0x4978 #define R_CHBW_MOD_V1 0x49C4 #define B_BT_SHARE BIT(14) #define B_CHBW_MOD_SBW GENMASK(13, 12) #define B_CHBW_MOD_PRICH GENMASK(11, 8) #define B_ANT_RX_SEG0 GENMASK(3, 0) +#define R_Q_MATRIX_11 0x4988 +#define B_Q_MATRIX_11_IMAGINARY GENMASK(15, 0) +#define B_Q_MATRIX_11_REAL GENMASK(31, 16) +#define R_CUSTOMIZE_Q_MATRIX 0x498C +#define B_CUSTOMIZE_Q_MATRIX_EN BIT(0) #define R_P0_RPL1 0x49B0 #define B_P0_RPL1_41_MASK GENMASK(31, 24) #define B_P0_RPL1_40_MASK GENMASK(23, 16) @@ -4539,6 +4932,8 @@ #define B_P0_TSSI_ALIM2 GENMASK(29, 0) #define R_P0_TSSI_ALIM4 0x5640 #define R_TSSI_PA_K8 0x5644 +#define R_P0_TSSI_ADC_CLK 0x566c +#define B_P0_TSSI_ADC_CLK GENMASK(17, 16) #define R_UPD_CLK 0x5670 #define B_DAC_VAL BIT(31) #define B_ACK_VAL GENMASK(30, 29) @@ -4619,6 +5014,8 @@ #define R_TXGAIN_SCALE 0x58F0 #define B_TXGAIN_SCALE_EN BIT(19) #define B_TXGAIN_SCALE_OFT GENMASK(31, 24) +#define R_P0_DAC_COMP_POST_DPD_EN 0x58F8 +#define B_P0_DAC_COMP_POST_DPD_EN BIT(31) #define R_P0_TSSI_BASE 0x5C00 #define R_S0_DACKI 0x5E00 #define B_S0_DACKI_AR GENMASK(31, 28) @@ -4649,6 +5046,8 @@ #define B_P1_TSSI_ALIM31 GENMASK(9, 0) #define R_P1_TSSI_ALIM2 0x763c #define B_P1_TSSI_ALIM2 GENMASK(29, 0) +#define R_P1_TSSI_ADC_CLK 0x766c +#define B_P1_TSSI_ADC_CLK GENMASK(17, 16) #define R_P1_TSSIC 0x7814 #define B_P1_TSSIC_BYPASS BIT(11) #define R_P1_TMETER 0x7810 @@ -4675,6 +5074,8 @@ #define B_P1_TSSI_MV_MIX GENMASK(19, 11) #define B_P1_TSSI_MV_AVG GENMASK(13, 11) #define B_P1_TSSI_MV_CLR BIT(14) +#define R_P1_DAC_COMP_POST_DPD_EN 0x78F8 +#define B_P1_DAC_COMP_POST_DPD_EN BIT(31) #define R_TSSI_THOF 0x7C00 #define R_S1_DACKI 0x7E00 #define B_S1_DACKI_AR GENMASK(31, 28) |