diff options
Diffstat (limited to 'drivers/pinctrl/realtek')
| -rw-r--r-- | drivers/pinctrl/realtek/Kconfig | 23 | ||||
| -rw-r--r-- | drivers/pinctrl/realtek/Makefile | 6 | ||||
| -rw-r--r-- | drivers/pinctrl/realtek/pinctrl-rtd.c | 596 | ||||
| -rw-r--r-- | drivers/pinctrl/realtek/pinctrl-rtd.h | 124 | ||||
| -rw-r--r-- | drivers/pinctrl/realtek/pinctrl-rtd1315e.c | 1440 | ||||
| -rw-r--r-- | drivers/pinctrl/realtek/pinctrl-rtd1319d.c | 1610 | ||||
| -rw-r--r-- | drivers/pinctrl/realtek/pinctrl-rtd1619b.c | 1601 |
7 files changed, 5400 insertions, 0 deletions
diff --git a/drivers/pinctrl/realtek/Kconfig b/drivers/pinctrl/realtek/Kconfig new file mode 100644 index 000000000000..0fc6bd4fcb7e --- /dev/null +++ b/drivers/pinctrl/realtek/Kconfig @@ -0,0 +1,23 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +config PINCTRL_RTD + tristate "Realtek DHC core pin controller driver" + depends on ARCH_REALTEK + default y + select PINMUX + select GENERIC_PINCONF + +config PINCTRL_RTD1619B + tristate "Realtek DHC 1619B pin controller driver" + depends on PINCTRL_RTD + default y + +config PINCTRL_RTD1319D + tristate "Realtek DHC 1319D pin controller driver" + depends on PINCTRL_RTD + default y + +config PINCTRL_RTD1315E + tristate "Realtek DHC 1315E pin controller driver" + depends on PINCTRL_RTD + default y diff --git a/drivers/pinctrl/realtek/Makefile b/drivers/pinctrl/realtek/Makefile new file mode 100644 index 000000000000..c7bace0001e9 --- /dev/null +++ b/drivers/pinctrl/realtek/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# Realtek DHC pin control drivers +obj-$(CONFIG_PINCTRL_RTD) += pinctrl-rtd.o +obj-$(CONFIG_PINCTRL_RTD1619B) += pinctrl-rtd1619b.o +obj-$(CONFIG_PINCTRL_RTD1319D) += pinctrl-rtd1319d.o +obj-$(CONFIG_PINCTRL_RTD1315E) += pinctrl-rtd1315e.o diff --git a/drivers/pinctrl/realtek/pinctrl-rtd.c b/drivers/pinctrl/realtek/pinctrl-rtd.c new file mode 100644 index 000000000000..9c7a1af4ba69 --- /dev/null +++ b/drivers/pinctrl/realtek/pinctrl-rtd.c @@ -0,0 +1,596 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Realtek DHC pin controller driver + * + * Copyright (c) 2023 Realtek Semiconductor Corp. + */ + +#include <linux/bitops.h> +#include <linux/io.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/of_address.h> +#include <linux/pinctrl/machine.h> +#include <linux/pinctrl/pinconf.h> +#include <linux/pinctrl/pinconf-generic.h> +#include <linux/pinctrl/pinctrl.h> +#include <linux/pinctrl/pinmux.h> +#include <linux/platform_device.h> +#include <linux/seq_file.h> +#include <linux/regmap.h> +#include <linux/slab.h> +#include "../core.h" +#include "../pinctrl-utils.h" +#include "pinctrl-rtd.h" + +struct rtd_pinctrl { + struct device *dev; + struct pinctrl_dev *pcdev; + void __iomem *base; + struct pinctrl_desc desc; + const struct rtd_pinctrl_desc *info; + struct regmap *regmap_pinctrl; +}; + +/* custom pinconf parameters */ +#define RTD_DRIVE_STRENGH_P (PIN_CONFIG_END + 1) +#define RTD_DRIVE_STRENGH_N (PIN_CONFIG_END + 2) +#define RTD_DUTY_CYCLE (PIN_CONFIG_END + 3) + +static const struct pinconf_generic_params rtd_custom_bindings[] = { + {"realtek,drive-strength-p", RTD_DRIVE_STRENGH_P, 0}, + {"realtek,drive-strength-n", RTD_DRIVE_STRENGH_N, 0}, + {"realtek,duty-cycle", RTD_DUTY_CYCLE, 0}, +}; + +static int rtd_pinctrl_get_groups_count(struct pinctrl_dev *pcdev) +{ + struct rtd_pinctrl *data = pinctrl_dev_get_drvdata(pcdev); + + return data->info->num_groups; +} + +static const char *rtd_pinctrl_get_group_name(struct pinctrl_dev *pcdev, + unsigned int selector) +{ + struct rtd_pinctrl *data = pinctrl_dev_get_drvdata(pcdev); + + return data->info->groups[selector].name; +} + +static int rtd_pinctrl_get_group_pins(struct pinctrl_dev *pcdev, + unsigned int selector, + const unsigned int **pins, + unsigned int *num_pins) +{ + struct rtd_pinctrl *data = pinctrl_dev_get_drvdata(pcdev); + + *pins = data->info->groups[selector].pins; + *num_pins = data->info->groups[selector].num_pins; + + return 0; +} + +static void rtd_pinctrl_dbg_show(struct pinctrl_dev *pcdev, + struct seq_file *s, + unsigned int offset) +{ + struct rtd_pinctrl *data = pinctrl_dev_get_drvdata(pcdev); + const struct rtd_pin_desc *mux = &data->info->muxes[offset]; + const struct rtd_pin_mux_desc *func; + u32 val; + u32 mask; + u32 pin_val; + int is_map; + + if (!mux->name) { + seq_puts(s, "[not defined]"); + return; + } + val = readl_relaxed(data->base + mux->mux_offset); + mask = mux->mux_mask; + pin_val = val & mask; + + is_map = 0; + func = &mux->functions[0]; + seq_puts(s, "function: "); + while (func->name) { + if (func->mux_value == pin_val) { + is_map = 1; + seq_printf(s, "[%s] ", func->name); + } else { + seq_printf(s, "%s ", func->name); + } + func++; + } + if (!is_map) + seq_puts(s, "[not defined]"); +} + +static const struct pinctrl_ops rtd_pinctrl_ops = { + .dt_node_to_map = pinconf_generic_dt_node_to_map_all, + .dt_free_map = pinctrl_utils_free_map, + .get_groups_count = rtd_pinctrl_get_groups_count, + .get_group_name = rtd_pinctrl_get_group_name, + .get_group_pins = rtd_pinctrl_get_group_pins, + .pin_dbg_show = rtd_pinctrl_dbg_show, +}; + +static int rtd_pinctrl_get_functions_count(struct pinctrl_dev *pcdev) +{ + struct rtd_pinctrl *data = pinctrl_dev_get_drvdata(pcdev); + + return data->info->num_functions; +} + +static const char *rtd_pinctrl_get_function_name(struct pinctrl_dev *pcdev, + unsigned int selector) +{ + struct rtd_pinctrl *data = pinctrl_dev_get_drvdata(pcdev); + + return data->info->functions[selector].name; +} + +static int rtd_pinctrl_get_function_groups(struct pinctrl_dev *pcdev, + unsigned int selector, + const char * const **groups, + unsigned int * const num_groups) +{ + struct rtd_pinctrl *data = pinctrl_dev_get_drvdata(pcdev); + + *groups = data->info->functions[selector].groups; + *num_groups = data->info->functions[selector].num_groups; + + return 0; +} + +static const struct rtd_pin_desc *rtd_pinctrl_find_mux(struct rtd_pinctrl *data, unsigned int pin) +{ + if (!data->info->muxes[pin].name) + return &data->info->muxes[pin]; + + return NULL; +} + +static int rtd_pinctrl_set_one_mux(struct pinctrl_dev *pcdev, + unsigned int pin, const char *func_name) +{ + struct rtd_pinctrl *data = pinctrl_dev_get_drvdata(pcdev); + const struct rtd_pin_desc *mux; + int ret = 0; + int i; + + mux = rtd_pinctrl_find_mux(data, pin); + if (!mux) + return 0; + + if (!mux->functions) { + if (!mux->name) + dev_err(pcdev->dev, "NULL pin has no functions\n"); + else + dev_err(pcdev->dev, "No functions available for pin %s\n", mux->name); + return -ENOTSUPP; + } + + for (i = 0; mux->functions[i].name; i++) { + if (strcmp(mux->functions[i].name, func_name) != 0) + continue; + ret = regmap_update_bits(data->regmap_pinctrl, mux->mux_offset, mux->mux_mask, + mux->functions[i].mux_value); + return ret; + } + + if (!mux->name) { + dev_err(pcdev->dev, "NULL pin provided for function %s\n", func_name); + return -EINVAL; + } + + dev_err(pcdev->dev, "No function %s available for pin %s\n", func_name, mux->name); + + return -EINVAL; +} + +static int rtd_pinctrl_set_mux(struct pinctrl_dev *pcdev, + unsigned int function, unsigned int group) +{ + struct rtd_pinctrl *data = pinctrl_dev_get_drvdata(pcdev); + const unsigned int *pins; + unsigned int num_pins; + const char *func_name; + const char *group_name; + int i, ret; + + func_name = data->info->functions[function].name; + group_name = data->info->groups[group].name; + + ret = rtd_pinctrl_get_group_pins(pcdev, group, &pins, &num_pins); + if (ret) { + dev_err(pcdev->dev, "Getting pins for group %s failed\n", group_name); + return ret; + } + + for (i = 0; i < num_pins; i++) { + ret = rtd_pinctrl_set_one_mux(pcdev, pins[i], func_name); + if (ret) + return ret; + } + + return 0; +} + +static int rtd_pinctrl_gpio_request_enable(struct pinctrl_dev *pcdev, + struct pinctrl_gpio_range *range, + unsigned int offset) +{ + return rtd_pinctrl_set_one_mux(pcdev, offset, "gpio"); +} + +static const struct pinmux_ops rtd_pinmux_ops = { + .get_functions_count = rtd_pinctrl_get_functions_count, + .get_function_name = rtd_pinctrl_get_function_name, + .get_function_groups = rtd_pinctrl_get_function_groups, + .set_mux = rtd_pinctrl_set_mux, + .gpio_request_enable = rtd_pinctrl_gpio_request_enable, +}; + +static const struct pinctrl_pin_desc + *rtd_pinctrl_get_pin_by_number(struct rtd_pinctrl *data, int number) +{ + int i; + + for (i = 0; i < data->info->num_pins; i++) { + if (data->info->pins[i].number == number) + return &data->info->pins[i]; + } + + return NULL; +} + +static const struct rtd_pin_config_desc + *rtd_pinctrl_find_config(struct rtd_pinctrl *data, unsigned int pin) +{ + if (!data->info->configs[pin].name) + return &data->info->configs[pin]; + + return NULL; +} + +static const struct rtd_pin_sconfig_desc *rtd_pinctrl_find_sconfig(struct rtd_pinctrl *data, + unsigned int pin) +{ + int i; + const struct pinctrl_pin_desc *pin_desc; + const char *pin_name; + + pin_desc = rtd_pinctrl_get_pin_by_number(data, pin); + if (!pin_desc) + return NULL; + + pin_name = pin_desc->name; + + for (i = 0; i < data->info->num_sconfigs; i++) { + if (strcmp(data->info->sconfigs[i].name, pin_name) == 0) + return &data->info->sconfigs[i]; + } + + return NULL; +} + +static int rtd_pconf_parse_conf(struct rtd_pinctrl *data, + unsigned int pinnr, + enum pin_config_param param, + enum pin_config_param arg) +{ + const struct rtd_pin_config_desc *config_desc; + const struct rtd_pin_sconfig_desc *sconfig_desc; + u8 set_val = 0; + u16 strength; + u32 val; + u32 mask; + u32 pulsel_off, pulen_off, smt_off, curr_off, pow_off, reg_off, p_off, n_off; + const char *name = data->info->pins[pinnr].name; + int ret = 0; + + config_desc = rtd_pinctrl_find_config(data, pinnr); + if (!config_desc) { + dev_err(data->dev, "Not support pin config for pin: %s\n", name); + return -ENOTSUPP; + } + switch ((u32)param) { + case PIN_CONFIG_INPUT_SCHMITT: + case PIN_CONFIG_INPUT_SCHMITT_ENABLE: + if (config_desc->smt_offset == NA) { + dev_err(data->dev, "Not support input schmitt for pin: %s\n", name); + return -ENOTSUPP; + } + smt_off = config_desc->base_bit + config_desc->smt_offset; + reg_off = config_desc->reg_offset; + set_val = arg; + + mask = BIT(smt_off); + val = set_val ? BIT(smt_off) : 0; + break; + + case PIN_CONFIG_DRIVE_PUSH_PULL: + if (config_desc->pud_en_offset == NA) { + dev_err(data->dev, "Not support push pull for pin: %s\n", name); + return -ENOTSUPP; + } + pulen_off = config_desc->base_bit + config_desc->pud_en_offset; + reg_off = config_desc->reg_offset; + + mask = BIT(pulen_off); + val = 0; + break; + + case PIN_CONFIG_BIAS_DISABLE: + if (config_desc->pud_en_offset == NA) { + dev_err(data->dev, "Not support bias disable for pin: %s\n", name); + return -ENOTSUPP; + } + pulen_off = config_desc->base_bit + config_desc->pud_en_offset; + reg_off = config_desc->reg_offset; + + mask = BIT(pulen_off); + val = 0; + break; + + case PIN_CONFIG_BIAS_PULL_UP: + if (config_desc->pud_en_offset == NA) { + dev_err(data->dev, "Not support bias pull up for pin:%s\n", name); + return -ENOTSUPP; + } + pulen_off = config_desc->base_bit + config_desc->pud_en_offset; + pulsel_off = config_desc->base_bit + config_desc->pud_sel_offset; + reg_off = config_desc->reg_offset; + + mask = BIT(pulen_off) | BIT(pulsel_off); + val = mask; + break; + + case PIN_CONFIG_BIAS_PULL_DOWN: + if (config_desc->pud_en_offset == NA) { + dev_err(data->dev, "Not support bias pull down for pin: %s\n", name); + return -ENOTSUPP; + } + pulen_off = config_desc->base_bit + config_desc->pud_en_offset; + pulsel_off = config_desc->base_bit + config_desc->pud_sel_offset; + reg_off = config_desc->reg_offset; + + mask = BIT(pulen_off) | BIT(pulsel_off); + val = BIT(pulen_off); + break; + + case PIN_CONFIG_DRIVE_STRENGTH: + curr_off = config_desc->base_bit + config_desc->curr_offset; + reg_off = config_desc->reg_offset; + strength = arg; + val = 0; + switch (config_desc->curr_type) { + case PADDRI_4_8: + if (strength == 4) + val = 0; + else if (strength == 8) + val = BIT(curr_off); + else + return -EINVAL; + break; + case PADDRI_2_4: + if (strength == 2) + val = 0; + else if (strength == 4) + val = BIT(curr_off); + else + return -EINVAL; + break; + case NA: + dev_err(data->dev, "Not support drive strength for pin: %s\n", name); + return -ENOTSUPP; + default: + return -EINVAL; + } + mask = BIT(curr_off); + break; + + case PIN_CONFIG_POWER_SOURCE: + if (config_desc->power_offset == NA) { + dev_err(data->dev, "Not support power source for pin: %s\n", name); + return -ENOTSUPP; + } + reg_off = config_desc->reg_offset; + pow_off = config_desc->base_bit + config_desc->power_offset; + if (pow_off >= 32) { + reg_off += 0x4; + pow_off -= 32; + } + set_val = arg; + mask = BIT(pow_off); + val = set_val ? mask : 0; + break; + + case RTD_DRIVE_STRENGH_P: + sconfig_desc = rtd_pinctrl_find_sconfig(data, pinnr); + if (!sconfig_desc) { + dev_err(data->dev, "Not support P driving for pin: %s\n", name); + return -ENOTSUPP; + } + set_val = arg; + reg_off = sconfig_desc->reg_offset; + p_off = sconfig_desc->pdrive_offset; + if (p_off >= 32) { + reg_off += 0x4; + p_off -= 32; + } + mask = GENMASK(p_off + sconfig_desc->pdrive_maskbits - 1, p_off); + val = set_val << p_off; + break; + + case RTD_DRIVE_STRENGH_N: + sconfig_desc = rtd_pinctrl_find_sconfig(data, pinnr); + if (!sconfig_desc) { + dev_err(data->dev, "Not support N driving for pin: %s\n", name); + return -ENOTSUPP; + } + set_val = arg; + reg_off = sconfig_desc->reg_offset; + n_off = sconfig_desc->ndrive_offset; + if (n_off >= 32) { + reg_off += 0x4; + n_off -= 32; + } + mask = GENMASK(n_off + sconfig_desc->ndrive_maskbits - 1, n_off); + val = set_val << n_off; + break; + + case RTD_DUTY_CYCLE: + sconfig_desc = rtd_pinctrl_find_sconfig(data, pinnr); + if (!sconfig_desc || sconfig_desc->dcycle_offset == NA) { + dev_err(data->dev, "Not support duty cycle for pin: %s\n", name); + return -ENOTSUPP; + } + set_val = arg; + reg_off = config_desc->reg_offset; + mask = GENMASK(sconfig_desc->dcycle_offset + + sconfig_desc->dcycle_maskbits - 1, sconfig_desc->dcycle_offset); + val = set_val << sconfig_desc->dcycle_offset; + break; + + default: + dev_err(data->dev, "unsupported pinconf: %d\n", (u32)param); + return -EINVAL; + } + + ret = regmap_update_bits(data->regmap_pinctrl, reg_off, mask, val); + if (ret) + dev_err(data->dev, "could not update pinconf(%d) for pin(%s)\n", (u32)param, name); + + return ret; +} + +static int rtd_pin_config_get(struct pinctrl_dev *pcdev, unsigned int pinnr, + unsigned long *config) +{ + unsigned int param = pinconf_to_config_param(*config); + unsigned int arg = 0; + + switch (param) { + default: + return -ENOTSUPP; + } + + *config = pinconf_to_config_packed(param, arg); + return 0; +} + +static int rtd_pin_config_set(struct pinctrl_dev *pcdev, unsigned int pinnr, + unsigned long *configs, unsigned int num_configs) +{ + struct rtd_pinctrl *data = pinctrl_dev_get_drvdata(pcdev); + int i; + int ret = 0; + + for (i = 0; i < num_configs; i++) { + ret = rtd_pconf_parse_conf(data, pinnr, + pinconf_to_config_param(configs[i]), + pinconf_to_config_argument(configs[i])); + if (ret < 0) + return ret; + } + + return 0; +} + +static int rtd_pin_config_group_set(struct pinctrl_dev *pcdev, unsigned int group, + unsigned long *configs, unsigned int num_configs) +{ + struct rtd_pinctrl *data = pinctrl_dev_get_drvdata(pcdev); + const unsigned int *pins; + unsigned int num_pins; + const char *group_name; + int i, ret; + + group_name = data->info->groups[group].name; + + ret = rtd_pinctrl_get_group_pins(pcdev, group, &pins, &num_pins); + if (ret) { + dev_err(pcdev->dev, "Getting pins for group %s failed\n", group_name); + return ret; + } + + for (i = 0; i < num_pins; i++) { + ret = rtd_pin_config_set(pcdev, pins[i], configs, num_configs); + if (ret) + return ret; + } + + return 0; +} + +static const struct pinconf_ops rtd_pinconf_ops = { + .is_generic = true, + .pin_config_get = rtd_pin_config_get, + .pin_config_set = rtd_pin_config_set, + .pin_config_group_set = rtd_pin_config_group_set, +}; + +static struct regmap_config rtd_pinctrl_regmap_config = { + .reg_bits = 32, + .val_bits = 32, + .reg_stride = 4, + .use_relaxed_mmio = true, +}; + +int rtd_pinctrl_probe(struct platform_device *pdev, const struct rtd_pinctrl_desc *desc) +{ + struct rtd_pinctrl *data; + int ret; + + data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL); + if (!data) + return -ENOMEM; + + data->base = of_iomap(pdev->dev.of_node, 0); + if (!data->base) + return -ENOMEM; + + data->dev = &pdev->dev; + data->info = desc; + data->desc.name = dev_name(&pdev->dev); + data->desc.pins = data->info->pins; + data->desc.npins = data->info->num_pins; + data->desc.pctlops = &rtd_pinctrl_ops; + data->desc.pmxops = &rtd_pinmux_ops; + data->desc.confops = &rtd_pinconf_ops; + data->desc.custom_params = rtd_custom_bindings; + data->desc.num_custom_params = ARRAY_SIZE(rtd_custom_bindings); + data->desc.owner = THIS_MODULE; + data->regmap_pinctrl = devm_regmap_init_mmio(data->dev, data->base, + &rtd_pinctrl_regmap_config); + + if (IS_ERR(data->regmap_pinctrl)) { + dev_err(data->dev, "failed to init regmap: %ld\n", + PTR_ERR(data->regmap_pinctrl)); + ret = PTR_ERR(data->regmap_pinctrl); + goto unmap; + } + + data->pcdev = pinctrl_register(&data->desc, &pdev->dev, data); + if (IS_ERR(data->pcdev)) { + ret = PTR_ERR(data->pcdev); + goto unmap; + } + + platform_set_drvdata(pdev, data); + + dev_dbg(&pdev->dev, "probed\n"); + + return 0; + +unmap: + iounmap(data->base); + return ret; +} +EXPORT_SYMBOL(rtd_pinctrl_probe); + +MODULE_DESCRIPTION("Realtek DHC SoC pinctrl driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/realtek/pinctrl-rtd.h b/drivers/pinctrl/realtek/pinctrl-rtd.h new file mode 100644 index 000000000000..e15130896abc --- /dev/null +++ b/drivers/pinctrl/realtek/pinctrl-rtd.h @@ -0,0 +1,124 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (c) 2023 Realtek Semiconductor Corp. + */ + +#define NA 0xffffffff +#define PADDRI_4_8 1 +#define PADDRI_2_4 0 + +struct rtd_pin_group_desc { + const char *name; + const unsigned int *pins; + unsigned int num_pins; +}; + +struct rtd_pin_func_desc { + const char *name; + const char * const *groups; + unsigned int num_groups; +}; + +struct rtd_pin_mux_desc { + const char *name; + u32 mux_value; +}; + +struct rtd_pin_config_desc { + const char *name; + unsigned int reg_offset; + unsigned int base_bit; + unsigned int pud_en_offset; + unsigned int pud_sel_offset; + unsigned int curr_offset; + unsigned int smt_offset; + unsigned int power_offset; + unsigned int curr_type; +}; + +struct rtd_pin_sconfig_desc { + const char *name; + unsigned int reg_offset; + unsigned int dcycle_offset; + unsigned int dcycle_maskbits; + unsigned int ndrive_offset; + unsigned int ndrive_maskbits; + unsigned int pdrive_offset; + unsigned int pdrive_maskbits; +}; + +struct rtd_pin_desc { + const char *name; + unsigned int mux_offset; + u32 mux_mask; + const struct rtd_pin_mux_desc *functions; +}; + +struct rtd_pin_reg_list { + unsigned int reg_offset; + unsigned int val; +}; + +#define SHIFT_LEFT(_val, _shift) ((_val) << (_shift)) + +#define RTK_PIN_MUX(_name, _mux_off, _mux_mask, ...) \ + { \ + .name = # _name, \ + .mux_offset = _mux_off, \ + .mux_mask = _mux_mask, \ + .functions = (const struct rtd_pin_mux_desc []) { \ + __VA_ARGS__, { } \ + }, \ + } + +#define RTK_PIN_CONFIG(_name, _reg_off, _base_bit, _pud_en_off, \ + _pud_sel_off, _curr_off, _smt_off, _pow_off, _curr_type) \ + { \ + .name = # _name, \ + .reg_offset = _reg_off, \ + .base_bit = _base_bit, \ + .pud_en_offset = _pud_en_off, \ + .pud_sel_offset = _pud_sel_off, \ + .curr_offset = _curr_off, \ + .smt_offset = _smt_off, \ + .power_offset = _pow_off, \ + .curr_type = _curr_type, \ + } + +#define RTK_PIN_SCONFIG(_name, _reg_off, _d_offset, _d_mask, \ + _n_offset, _n_mask, _p_offset, _p_mask) \ + { \ + .name = # _name, \ + .reg_offset = _reg_off, \ + .dcycle_offset = _d_offset, \ + .dcycle_maskbits = _d_mask, \ + .ndrive_offset = _n_offset, \ + .ndrive_maskbits = _n_mask, \ + .pdrive_offset = _p_offset, \ + .pdrive_maskbits = _p_mask, \ + } + +#define RTK_PIN_FUNC(_mux_val, _name) \ + { \ + .name = _name, \ + .mux_value = _mux_val, \ + } + +struct rtd_pinctrl_desc { + const struct pinctrl_pin_desc *pins; + unsigned int num_pins; + const struct rtd_pin_group_desc *groups; + unsigned int num_groups; + const struct rtd_pin_func_desc *functions; + unsigned int num_functions; + const struct rtd_pin_desc *muxes; + unsigned int num_muxes; + const struct rtd_pin_config_desc *configs; + unsigned int num_configs; + const struct rtd_pin_sconfig_desc *sconfigs; + unsigned int num_sconfigs; + struct rtd_pin_reg_list *lists; + unsigned int num_regs; +}; + +int rtd_pinctrl_probe(struct platform_device *pdev, const struct rtd_pinctrl_desc *desc); diff --git a/drivers/pinctrl/realtek/pinctrl-rtd1315e.c b/drivers/pinctrl/realtek/pinctrl-rtd1315e.c new file mode 100644 index 000000000000..10afc736a52b --- /dev/null +++ b/drivers/pinctrl/realtek/pinctrl-rtd1315e.c @@ -0,0 +1,1440 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Realtek DHC 1315E pin controller driver + * + * Copyright (c) 2023 Realtek Semiconductor Corp. + * + */ + +#include <linux/module.h> +#include <linux/of.h> +#include <linux/platform_device.h> +#include <linux/pinctrl/pinctrl.h> + +#include "pinctrl-rtd.h" + +enum rtd13xxe_iso_pins { + RTD1315E_ISO_GPIO_0 = 0, + RTD1315E_ISO_GPIO_1, + RTD1315E_ISO_EMMC_RST_N, + RTD1315E_ISO_EMMC_DD_SB, + RTD1315E_ISO_EMMC_CLK, + RTD1315E_ISO_EMMC_CMD, + RTD1315E_ISO_GPIO_6, + RTD1315E_ISO_GPIO_7, + RTD1315E_ISO_GPIO_8, + RTD1315E_ISO_GPIO_9, + RTD1315E_ISO_GPIO_10, + RTD1315E_ISO_GPIO_11, + RTD1315E_ISO_GPIO_12, + RTD1315E_ISO_GPIO_13, + RTD1315E_ISO_GPIO_14, + RTD1315E_ISO_GPIO_15, + RTD1315E_ISO_GPIO_16, + RTD1315E_ISO_GPIO_17, + RTD1315E_ISO_GPIO_18, + RTD1315E_ISO_GPIO_19, + RTD1315E_ISO_GPIO_20, + RTD1315E_ISO_EMMC_DATA_0, + RTD1315E_ISO_EMMC_DATA_1, + RTD1315E_ISO_EMMC_DATA_2, + RTD1315E_ISO_USB_CC2, + RTD1315E_ISO_GPIO_25, + RTD1315E_ISO_GPIO_26, + RTD1315E_ISO_GPIO_27, + RTD1315E_ISO_GPIO_28, + RTD1315E_ISO_GPIO_29, + RTD1315E_ISO_GPIO_30, + RTD1315E_ISO_GPIO_31, + RTD1315E_ISO_GPIO_32, + RTD1315E_ISO_GPIO_33, + RTD1315E_ISO_GPIO_34, + RTD1315E_ISO_GPIO_35, + RTD1315E_ISO_HIF_DATA, + RTD1315E_ISO_HIF_EN, + RTD1315E_ISO_HIF_RDY, + RTD1315E_ISO_HIF_CLK, + RTD1315E_ISO_GPIO_DUMMY_40, + RTD1315E_ISO_GPIO_DUMMY_41, + RTD1315E_ISO_GPIO_DUMMY_42, + RTD1315E_ISO_GPIO_DUMMY_43, + RTD1315E_ISO_GPIO_DUMMY_44, + RTD1315E_ISO_GPIO_DUMMY_45, + RTD1315E_ISO_GPIO_46, + RTD1315E_ISO_GPIO_47, + RTD1315E_ISO_GPIO_48, + RTD1315E_ISO_GPIO_49, + RTD1315E_ISO_GPIO_50, + RTD1315E_ISO_USB_CC1, + RTD1315E_ISO_EMMC_DATA_3, + RTD1315E_ISO_EMMC_DATA_4, + RTD1315E_ISO_IR_RX, + RTD1315E_ISO_UR0_RX, + RTD1315E_ISO_UR0_TX, + RTD1315E_ISO_GPIO_57, + RTD1315E_ISO_GPIO_58, + RTD1315E_ISO_GPIO_59, + RTD1315E_ISO_GPIO_60, + RTD1315E_ISO_GPIO_61, + RTD1315E_ISO_GPIO_62, + RTD1315E_ISO_GPIO_DUMMY_63, + RTD1315E_ISO_GPIO_DUMMY_64, + RTD1315E_ISO_GPIO_DUMMY_65, + RTD1315E_ISO_GPIO_66, + RTD1315E_ISO_GPIO_67, + RTD1315E_ISO_GPIO_68, + RTD1315E_ISO_GPIO_69, + RTD1315E_ISO_GPIO_70, + RTD1315E_ISO_GPIO_71, + RTD1315E_ISO_GPIO_72, + RTD1315E_ISO_GPIO_DUMMY_73, + RTD1315E_ISO_EMMC_DATA_5, + RTD1315E_ISO_EMMC_DATA_6, + RTD1315E_ISO_EMMC_DATA_7, + RTD1315E_ISO_GPIO_DUMMY_77, + RTD1315E_ISO_GPIO_78, + RTD1315E_ISO_GPIO_79, + RTD1315E_ISO_GPIO_80, + RTD1315E_ISO_GPIO_81, + RTD1315E_ISO_UR2_LOC, + RTD1315E_ISO_GSPI_LOC, + RTD1315E_ISO_HI_WIDTH, + RTD1315E_ISO_SF_EN, + RTD1315E_ISO_ARM_TRACE_DBG_EN, + RTD1315E_ISO_EJTAG_AUCPU_LOC, + RTD1315E_ISO_EJTAG_ACPU_LOC, + RTD1315E_ISO_EJTAG_VCPU_LOC, + RTD1315E_ISO_EJTAG_SCPU_LOC, + RTD1315E_ISO_DMIC_LOC, + RTD1315E_ISO_VTC_DMIC_LOC, + RTD1315E_ISO_VTC_TDM_LOC, + RTD1315E_ISO_VTC_I2SI_LOC, + RTD1315E_ISO_TDM_AI_LOC, + RTD1315E_ISO_AI_LOC, + RTD1315E_ISO_SPDIF_LOC, + RTD1315E_ISO_HIF_EN_LOC, + RTD1315E_ISO_SCAN_SWITCH, + RTD1315E_ISO_WD_RSET, + RTD1315E_ISO_BOOT_SEL, + RTD1315E_ISO_RESET_N, + RTD1315E_ISO_TESTMODE, +}; + +static const struct pinctrl_pin_desc rtd1315e_iso_pins[] = { + PINCTRL_PIN(RTD1315E_ISO_GPIO_0, "gpio_0"), + PINCTRL_PIN(RTD1315E_ISO_GPIO_1, "gpio_1"), + PINCTRL_PIN(RTD1315E_ISO_EMMC_RST_N, "emmc_rst_n"), + PINCTRL_PIN(RTD1315E_ISO_EMMC_DD_SB, "emmc_dd_sb"), + PINCTRL_PIN(RTD1315E_ISO_EMMC_CLK, "emmc_clk"), + PINCTRL_PIN(RTD1315E_ISO_EMMC_CMD, "emmc_cmd"), + PINCTRL_PIN(RTD1315E_ISO_GPIO_6, "gpio_6"), + PINCTRL_PIN(RTD1315E_ISO_GPIO_7, "gpio_7"), + PINCTRL_PIN(RTD1315E_ISO_GPIO_8, "gpio_8"), + PINCTRL_PIN(RTD1315E_ISO_GPIO_9, "gpio_9"), + PINCTRL_PIN(RTD1315E_ISO_GPIO_10, "gpio_10"), + PINCTRL_PIN(RTD1315E_ISO_GPIO_11, "gpio_11"), + PINCTRL_PIN(RTD1315E_ISO_GPIO_12, "gpio_12"), + PINCTRL_PIN(RTD1315E_ISO_GPIO_13, "gpio_13"), + PINCTRL_PIN(RTD1315E_ISO_GPIO_14, "gpio_14"), + PINCTRL_PIN(RTD1315E_ISO_GPIO_15, "gpio_15"), + PINCTRL_PIN(RTD1315E_ISO_GPIO_16, "gpio_16"), + PINCTRL_PIN(RTD1315E_ISO_GPIO_17, "gpio_17"), + PINCTRL_PIN(RTD1315E_ISO_GPIO_18, "gpio_18"), + PINCTRL_PIN(RTD1315E_ISO_GPIO_19, "gpio_19"), + PINCTRL_PIN(RTD1315E_ISO_GPIO_20, "gpio_20"), + PINCTRL_PIN(RTD1315E_ISO_EMMC_DATA_0, "emmc_data_0"), + PINCTRL_PIN(RTD1315E_ISO_EMMC_DATA_1, "emmc_data_1"), + PINCTRL_PIN(RTD1315E_ISO_EMMC_DATA_2, "emmc_data_2"), + PINCTRL_PIN(RTD1315E_ISO_USB_CC2, "usb_cc2"), + PINCTRL_PIN(RTD1315E_ISO_GPIO_25, "gpio_25"), + PINCTRL_PIN(RTD1315E_ISO_GPIO_26, "gpio_26"), + PINCTRL_PIN(RTD1315E_ISO_GPIO_27, "gpio_27"), + PINCTRL_PIN(RTD1315E_ISO_GPIO_28, "gpio_28"), + PINCTRL_PIN(RTD1315E_ISO_GPIO_29, "gpio_29"), + PINCTRL_PIN(RTD1315E_ISO_GPIO_30, "gpio_30"), + PINCTRL_PIN(RTD1315E_ISO_GPIO_31, "gpio_31"), + PINCTRL_PIN(RTD1315E_ISO_GPIO_32, "gpio_32"), + PINCTRL_PIN(RTD1315E_ISO_GPIO_33, "gpio_33"), + PINCTRL_PIN(RTD1315E_ISO_GPIO_34, "gpio_34"), + PINCTRL_PIN(RTD1315E_ISO_GPIO_35, "gpio_35"), + PINCTRL_PIN(RTD1315E_ISO_HIF_DATA, "hif_data"), + PINCTRL_PIN(RTD1315E_ISO_HIF_EN, "hif_en"), + PINCTRL_PIN(RTD1315E_ISO_HIF_RDY, "hif_rdy"), + PINCTRL_PIN(RTD1315E_ISO_HIF_CLK, "hif_clk"), + PINCTRL_PIN(RTD1315E_ISO_GPIO_DUMMY_40, "gpio_dummy_40"), + PINCTRL_PIN(RTD1315E_ISO_GPIO_DUMMY_41, "gpio_dummy_41"), + PINCTRL_PIN(RTD1315E_ISO_GPIO_DUMMY_42, "gpio_dummy_42"), + PINCTRL_PIN(RTD1315E_ISO_GPIO_DUMMY_43, "gpio_dummy_43"), + PINCTRL_PIN(RTD1315E_ISO_GPIO_DUMMY_44, "gpio_dummy_44"), + PINCTRL_PIN(RTD1315E_ISO_GPIO_DUMMY_45, "gpio_dummy_45"), + PINCTRL_PIN(RTD1315E_ISO_GPIO_46, "gpio_46"), + PINCTRL_PIN(RTD1315E_ISO_GPIO_47, "gpio_47"), + PINCTRL_PIN(RTD1315E_ISO_GPIO_48, "gpio_48"), + PINCTRL_PIN(RTD1315E_ISO_GPIO_49, "gpio_49"), + PINCTRL_PIN(RTD1315E_ISO_GPIO_50, "gpio_50"), + PINCTRL_PIN(RTD1315E_ISO_USB_CC1, "usb_cc1"), + PINCTRL_PIN(RTD1315E_ISO_EMMC_DATA_3, "emmc_data_3"), + PINCTRL_PIN(RTD1315E_ISO_EMMC_DATA_4, "emmc_data_4"), + PINCTRL_PIN(RTD1315E_ISO_IR_RX, "ir_rx"), + PINCTRL_PIN(RTD1315E_ISO_UR0_RX, "ur0_rx"), + PINCTRL_PIN(RTD1315E_ISO_UR0_TX, "ur0_tx"), + PINCTRL_PIN(RTD1315E_ISO_GPIO_57, "gpio_57"), + PINCTRL_PIN(RTD1315E_ISO_GPIO_58, "gpio_58"), + PINCTRL_PIN(RTD1315E_ISO_GPIO_59, "gpio_59"), + PINCTRL_PIN(RTD1315E_ISO_GPIO_60, "gpio_60"), + PINCTRL_PIN(RTD1315E_ISO_GPIO_61, "gpio_61"), + PINCTRL_PIN(RTD1315E_ISO_GPIO_62, "gpio_62"), + PINCTRL_PIN(RTD1315E_ISO_GPIO_DUMMY_63, "gpio_dummy_63"), + PINCTRL_PIN(RTD1315E_ISO_GPIO_DUMMY_64, "gpio_dummy_64"), + PINCTRL_PIN(RTD1315E_ISO_GPIO_DUMMY_65, "gpio_dummy_65"), + PINCTRL_PIN(RTD1315E_ISO_GPIO_66, "gpio_66"), + PINCTRL_PIN(RTD1315E_ISO_GPIO_67, "gpio_67"), + PINCTRL_PIN(RTD1315E_ISO_GPIO_68, "gpio_68"), + PINCTRL_PIN(RTD1315E_ISO_GPIO_69, "gpio_69"), + PINCTRL_PIN(RTD1315E_ISO_GPIO_70, "gpio_70"), + PINCTRL_PIN(RTD1315E_ISO_GPIO_71, "gpio_71"), + PINCTRL_PIN(RTD1315E_ISO_GPIO_72, "gpio_72"), + PINCTRL_PIN(RTD1315E_ISO_GPIO_DUMMY_73, "gpio_dummy_73"), + PINCTRL_PIN(RTD1315E_ISO_EMMC_DATA_5, "emmc_data_5"), + PINCTRL_PIN(RTD1315E_ISO_EMMC_DATA_6, "emmc_data_6"), + PINCTRL_PIN(RTD1315E_ISO_EMMC_DATA_7, "emmc_data_7"), + PINCTRL_PIN(RTD1315E_ISO_GPIO_DUMMY_77, "gpio_dummy_77"), + PINCTRL_PIN(RTD1315E_ISO_GPIO_78, "gpio_78"), + PINCTRL_PIN(RTD1315E_ISO_GPIO_79, "gpio_79"), + PINCTRL_PIN(RTD1315E_ISO_GPIO_80, "gpio_80"), + PINCTRL_PIN(RTD1315E_ISO_GPIO_81, "gpio_81"), + PINCTRL_PIN(RTD1315E_ISO_UR2_LOC, "ur2_loc"), + PINCTRL_PIN(RTD1315E_ISO_GSPI_LOC, "gspi_loc"), + PINCTRL_PIN(RTD1315E_ISO_HI_WIDTH, "hi_width"), + PINCTRL_PIN(RTD1315E_ISO_SF_EN, "sf_en"), + PINCTRL_PIN(RTD1315E_ISO_ARM_TRACE_DBG_EN, "arm_trace_dbg_en"), + PINCTRL_PIN(RTD1315E_ISO_EJTAG_AUCPU_LOC, "ejtag_aucpu_loc"), + PINCTRL_PIN(RTD1315E_ISO_EJTAG_ACPU_LOC, "ejtag_acpu_loc"), + PINCTRL_PIN(RTD1315E_ISO_EJTAG_VCPU_LOC, "ejtag_vcpu_loc"), + PINCTRL_PIN(RTD1315E_ISO_EJTAG_SCPU_LOC, "ejtag_scpu_loc"), + PINCTRL_PIN(RTD1315E_ISO_DMIC_LOC, "dmic_loc"), + PINCTRL_PIN(RTD1315E_ISO_VTC_DMIC_LOC, "vtc_dmic_loc"), + PINCTRL_PIN(RTD1315E_ISO_VTC_TDM_LOC, "vtc_tdm_loc"), + PINCTRL_PIN(RTD1315E_ISO_VTC_I2SI_LOC, "vtc_i2si_loc"), + PINCTRL_PIN(RTD1315E_ISO_TDM_AI_LOC, "tdm_ai_loc"), + PINCTRL_PIN(RTD1315E_ISO_AI_LOC, "ai_loc"), + PINCTRL_PIN(RTD1315E_ISO_SPDIF_LOC, "spdif_loc"), + PINCTRL_PIN(RTD1315E_ISO_HIF_EN_LOC, "hif_en_loc"), + PINCTRL_PIN(RTD1315E_ISO_SCAN_SWITCH, "scan_switch"), + PINCTRL_PIN(RTD1315E_ISO_WD_RSET, "wd_rset"), + PINCTRL_PIN(RTD1315E_ISO_BOOT_SEL, "boot_sel"), + PINCTRL_PIN(RTD1315E_ISO_RESET_N, "reset_n"), + PINCTRL_PIN(RTD1315E_ISO_TESTMODE, "testmode"), +}; + +/* Tagged as __maybe_unused since there are pins we may use in the future */ +#define DECLARE_RTD1315E_PIN(_pin, _name) \ + static const unsigned int rtd1315e_## _name ##_pins[] __maybe_unused = { _pin } + +DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_0, gpio_0); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_1, gpio_1); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_EMMC_RST_N, emmc_rst_n); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_EMMC_DD_SB, emmc_dd_sb); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_EMMC_CLK, emmc_clk); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_EMMC_CMD, emmc_cmd); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_6, gpio_6); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_7, gpio_7); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_8, gpio_8); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_9, gpio_9); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_10, gpio_10); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_11, gpio_11); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_12, gpio_12); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_13, gpio_13); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_14, gpio_14); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_15, gpio_15); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_16, gpio_16); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_17, gpio_17); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_18, gpio_18); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_19, gpio_19); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_20, gpio_20); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_EMMC_DATA_0, emmc_data_0); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_EMMC_DATA_1, emmc_data_1); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_EMMC_DATA_2, emmc_data_2); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_USB_CC2, usb_cc2); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_25, gpio_25); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_26, gpio_26); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_27, gpio_27); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_28, gpio_28); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_29, gpio_29); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_30, gpio_30); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_31, gpio_31); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_32, gpio_32); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_33, gpio_33); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_34, gpio_34); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_35, gpio_35); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_HIF_DATA, hif_data); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_HIF_EN, hif_en); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_HIF_RDY, hif_rdy); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_HIF_CLK, hif_clk); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_DUMMY_40, gpio_dummy_40); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_DUMMY_41, gpio_dummy_41); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_DUMMY_42, gpio_dummy_42); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_DUMMY_43, gpio_dummy_43); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_DUMMY_44, gpio_dummy_44); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_DUMMY_45, gpio_dummy_45); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_46, gpio_46); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_47, gpio_47); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_48, gpio_48); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_49, gpio_49); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_50, gpio_50); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_USB_CC1, usb_cc1); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_EMMC_DATA_3, emmc_data_3); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_EMMC_DATA_4, emmc_data_4); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_IR_RX, ir_rx); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_UR0_RX, ur0_rx); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_UR0_TX, ur0_tx); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_57, gpio_57); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_58, gpio_58); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_59, gpio_59); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_60, gpio_60); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_61, gpio_61); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_62, gpio_62); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_DUMMY_63, gpio_dummy_63); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_DUMMY_64, gpio_dummy_64); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_DUMMY_65, gpio_dummy_65); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_66, gpio_66); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_67, gpio_67); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_68, gpio_68); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_69, gpio_69); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_70, gpio_70); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_71, gpio_71); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_72, gpio_72); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_DUMMY_73, gpio_dummy_73); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_EMMC_DATA_5, emmc_data_5); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_EMMC_DATA_6, emmc_data_6); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_EMMC_DATA_7, emmc_data_7); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_DUMMY_77, gpio_dummy_77); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_78, gpio_78); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_79, gpio_79); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_80, gpio_80); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_81, gpio_81); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_UR2_LOC, ur2_loc); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_GSPI_LOC, gspi_loc); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_HI_WIDTH, hi_width); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_SF_EN, sf_en); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_ARM_TRACE_DBG_EN, arm_trace_dbg_en); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_EJTAG_AUCPU_LOC, ejtag_aucpu_loc); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_EJTAG_ACPU_LOC, ejtag_acpu_loc); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_EJTAG_VCPU_LOC, ejtag_vcpu_loc); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_EJTAG_SCPU_LOC, ejtag_scpu_loc); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_DMIC_LOC, dmic_loc); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_VTC_DMIC_LOC, vtc_dmic_loc); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_VTC_TDM_LOC, vtc_tdm_loc); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_VTC_I2SI_LOC, vtc_i2si_loc); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_TDM_AI_LOC, tdm_ai_loc); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_AI_LOC, ai_loc); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_SPDIF_LOC, spdif_loc); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_HIF_EN_LOC, hif_en_loc); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_SCAN_SWITCH, scan_switch); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_WD_RSET, wd_rset); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_BOOT_SEL, boot_sel); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_RESET_N, reset_n); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_TESTMODE, testmode); + +#define RTD1315E_GROUP(_name) \ + { \ + .name = # _name, \ + .pins = rtd1315e_ ## _name ## _pins, \ + .num_pins = ARRAY_SIZE(rtd1315e_ ## _name ## _pins), \ + } + +static const struct rtd_pin_group_desc rtd1315e_pin_groups[] = { + RTD1315E_GROUP(gpio_0), + RTD1315E_GROUP(gpio_1), + RTD1315E_GROUP(emmc_rst_n), + RTD1315E_GROUP(emmc_dd_sb), + RTD1315E_GROUP(emmc_clk), + RTD1315E_GROUP(emmc_cmd), + RTD1315E_GROUP(gpio_6), + RTD1315E_GROUP(gpio_7), + RTD1315E_GROUP(gpio_8), + RTD1315E_GROUP(gpio_9), + RTD1315E_GROUP(gpio_10), + RTD1315E_GROUP(gpio_11), + RTD1315E_GROUP(gpio_12), + RTD1315E_GROUP(gpio_13), + RTD1315E_GROUP(gpio_14), + RTD1315E_GROUP(gpio_15), + RTD1315E_GROUP(gpio_16), + RTD1315E_GROUP(gpio_17), + RTD1315E_GROUP(gpio_18), + RTD1315E_GROUP(gpio_19), + RTD1315E_GROUP(gpio_20), + RTD1315E_GROUP(emmc_data_0), + RTD1315E_GROUP(emmc_data_1), + RTD1315E_GROUP(emmc_data_2), + RTD1315E_GROUP(usb_cc2), + RTD1315E_GROUP(gpio_25), + RTD1315E_GROUP(gpio_26), + RTD1315E_GROUP(gpio_27), + RTD1315E_GROUP(gpio_28), + RTD1315E_GROUP(gpio_29), + RTD1315E_GROUP(gpio_30), + RTD1315E_GROUP(gpio_31), + RTD1315E_GROUP(gpio_32), + RTD1315E_GROUP(gpio_33), + RTD1315E_GROUP(gpio_34), + RTD1315E_GROUP(gpio_35), + RTD1315E_GROUP(hif_data), + RTD1315E_GROUP(hif_en), + RTD1315E_GROUP(hif_rdy), + RTD1315E_GROUP(hif_clk), + RTD1315E_GROUP(gpio_dummy_40), + RTD1315E_GROUP(gpio_dummy_41), + RTD1315E_GROUP(gpio_dummy_42), + RTD1315E_GROUP(gpio_dummy_43), + RTD1315E_GROUP(gpio_dummy_44), + RTD1315E_GROUP(gpio_dummy_45), + RTD1315E_GROUP(gpio_46), + RTD1315E_GROUP(gpio_47), + RTD1315E_GROUP(gpio_48), + RTD1315E_GROUP(gpio_49), + RTD1315E_GROUP(gpio_50), + RTD1315E_GROUP(usb_cc1), + RTD1315E_GROUP(emmc_data_3), + RTD1315E_GROUP(emmc_data_4), + RTD1315E_GROUP(ir_rx), + RTD1315E_GROUP(ur0_rx), + RTD1315E_GROUP(ur0_tx), + RTD1315E_GROUP(gpio_57), + RTD1315E_GROUP(gpio_58), + RTD1315E_GROUP(gpio_59), + RTD1315E_GROUP(gpio_60), + RTD1315E_GROUP(gpio_61), + RTD1315E_GROUP(gpio_62), + RTD1315E_GROUP(gpio_dummy_63), + RTD1315E_GROUP(gpio_dummy_64), + RTD1315E_GROUP(gpio_dummy_65), + RTD1315E_GROUP(gpio_66), + RTD1315E_GROUP(gpio_67), + RTD1315E_GROUP(gpio_68), + RTD1315E_GROUP(gpio_69), + RTD1315E_GROUP(gpio_70), + RTD1315E_GROUP(gpio_71), + RTD1315E_GROUP(gpio_72), + RTD1315E_GROUP(gpio_dummy_73), + RTD1315E_GROUP(emmc_data_5), + RTD1315E_GROUP(emmc_data_6), + RTD1315E_GROUP(emmc_data_7), + RTD1315E_GROUP(gpio_dummy_77), + RTD1315E_GROUP(gpio_78), + RTD1315E_GROUP(gpio_79), + RTD1315E_GROUP(gpio_80), + RTD1315E_GROUP(gpio_81), + RTD1315E_GROUP(ur2_loc), + RTD1315E_GROUP(gspi_loc), + RTD1315E_GROUP(hi_width), + RTD1315E_GROUP(sf_en), + RTD1315E_GROUP(arm_trace_dbg_en), + RTD1315E_GROUP(ejtag_aucpu_loc), + RTD1315E_GROUP(ejtag_acpu_loc), + RTD1315E_GROUP(ejtag_vcpu_loc), + RTD1315E_GROUP(ejtag_scpu_loc), + RTD1315E_GROUP(dmic_loc), + RTD1315E_GROUP(vtc_dmic_loc), + RTD1315E_GROUP(vtc_tdm_loc), + RTD1315E_GROUP(vtc_i2si_loc), + RTD1315E_GROUP(tdm_ai_loc), + RTD1315E_GROUP(ai_loc), + RTD1315E_GROUP(spdif_loc), + RTD1315E_GROUP(hif_en_loc), + +}; + +static const char * const rtd1315e_gpio_groups[] = { + "gpio_0", "gpio_1", "emmc_rst_n", "emmc_dd_sb", "emmc_clk", + "emmc_cmd", "gpio_6", "gpio_7", "gpio_8", "gpio_9", + "gpio_10", "gpio_11", "gpio_12", "gpio_13", "gpio_14", + "gpio_15", "gpio_16", "gpio_17", "gpio_18", "gpio_19", + "gpio_20", "emmc_data_0", "emmc_data_1", "emmc_data_2", "usb_cc2", + "gpio_25", "gpio_26", "gpio_27", "gpio_28", "gpio_29", + "gpio_30", "gpio_31", "gpio_32", "gpio_33", "gpio_34", + "gpio_35", "hif_data", "hif_en", "hif_rdy", "hif_clk", + "gpio_46", "gpio_47", "gpio_48", "gpio_49", + "gpio_50", "usb_cc1", "emmc_data_3", "emmc_data_4", "ir_rx", + "ur0_rx", "ur0_tx", "gpio_57", "gpio_58", "gpio_59", + "gpio_60", "gpio_61", "gpio_62", "gpio_66", "gpio_67", + "gpio_68", "gpio_69", "gpio_70", "gpio_71", "gpio_72", + "emmc_data_5", "emmc_data_6", "emmc_data_7", + "gpio_78", "gpio_79", "gpio_80", "gpio_81" }; +static const char * const rtd1315e_nf_groups[] = { + "emmc_rst_n", "emmc_clk", "emmc_cmd", "emmc_data_0", + "emmc_data_1", "emmc_data_2", "emmc_data_3", "emmc_data_4", + "emmc_data_5", "emmc_data_6", "emmc_data_7", + "gpio_78", "gpio_79", "gpio_80", "gpio_81" }; +static const char * const rtd1315e_emmc_groups[] = { + "emmc_rst_n", "emmc_dd_sb", "emmc_clk", "emmc_cmd", + "emmc_data_0", "emmc_data_1", "emmc_data_2", "emmc_data_3", + "emmc_data_4", "emmc_data_5", "emmc_data_6", "emmc_data_7" }; + +static const char * const rtd1315e_ao_groups[] = { + "gpio_66", "gpio_67", "gpio_68", "gpio_69", "gpio_70", + "gpio_71", "gpio_72" }; +static const char * const rtd1315e_gspi_loc0_groups[] = { + "gpio_18", "gpio_19", "gpio_20", "gpio_31", "gspi_loc" }; +static const char * const rtd1315e_gspi_loc1_groups[] = { + "gpio_8", "gpio_9", "gpio_10", "gpio_11", "gspi_loc" }; +static const char * const rtd1315e_uart0_groups[] = { "ur0_rx", "ur0_tx"}; +static const char * const rtd1315e_uart1_groups[] = { + "gpio_8", "gpio_9", "gpio_10", "gpio_11" }; +static const char * const rtd1315e_uart2_loc0_groups[] = { + "gpio_18", "gpio_19", "gpio_20", "gpio_31", "ur2_loc" }; +static const char * const rtd1315e_uart2_loc1_groups[] = { + "gpio_25", "gpio_26", "gpio_27", "gpio_28", "ur2_loc" }; +static const char * const rtd1315e_i2c0_groups[] = { "gpio_12", "gpio_13" }; +static const char * const rtd1315e_i2c1_groups[] = { "gpio_16", "gpio_17" }; +static const char * const rtd1315e_i2c4_groups[] = { "gpio_34", "gpio_35" }; +static const char * const rtd1315e_i2c5_groups[] = { "gpio_29", "gpio_46" }; +static const char * const rtd1315e_pcie1_groups[] = { "gpio_25" }; +static const char * const rtd1315e_etn_led_groups[] = { "gpio_14", "gpio_15" }; +static const char * const rtd1315e_etn_phy_groups[] = { "gpio_14", "gpio_15" }; +static const char * const rtd1315e_spi_groups[] = { + "gpio_78", "gpio_79", "gpio_80", "gpio_81" }; +static const char * const rtd1315e_pwm0_loc0_groups[] = { "gpio_26" }; +static const char * const rtd1315e_pwm0_loc1_groups[] = { "gpio_20" }; +static const char * const rtd1315e_pwm1_loc0_groups[] = { "gpio_27" }; +static const char * const rtd1315e_pwm1_loc1_groups[] = { "gpio_29" }; + +static const char * const rtd1315e_pwm2_loc0_groups[] = { "gpio_28" }; +static const char * const rtd1315e_pwm2_loc1_groups[] = { "gpio_30" }; +static const char * const rtd1315e_pwm3_loc0_groups[] = { "gpio_47" }; +static const char * const rtd1315e_pwm3_loc1_groups[] = { "gpio_31" }; +static const char * const rtd1315e_spdif_optical_loc0_groups[] = { "gpio_20", "spdif_loc" }; +static const char * const rtd1315e_spdif_optical_loc1_groups[] = { "gpio_6", "spdif_loc" }; +static const char * const rtd1315e_usb_cc1_groups[] = { "usb_cc1" }; +static const char * const rtd1315e_usb_cc2_groups[] = { "usb_cc2" }; + +static const char * const rtd1315e_sd_groups[] = { + "gpio_32", "gpio_33", "gpio_34", "gpio_35", + "hif_data", "hif_en", "hif_rdy", "hif_clk" }; +static const char * const rtd1315e_dmic_loc0_groups[] = { + "gpio_57", "gpio_58", "gpio_59", "gpio_60", "gpio_61", + "gpio_62", "gpio_1", "gpio_6", "dmic_loc" }; +static const char * const rtd1315e_dmic_loc1_groups[] = { + "gpio_32", "gpio_33", "gpio_34", "gpio_35", + "hif_data", "hif_en", "hif_rdy", "hif_clk", + "dmic_loc" }; +static const char * const rtd1315e_ai_loc0_groups[] = { + "gpio_57", "gpio_58", "gpio_59", "gpio_60", "gpio_61", + "gpio_62", "gpio_1", "ai_loc" }; +static const char * const rtd1315e_ai_loc1_groups[] = { + "gpio_32", "gpio_33", "gpio_34", "hif_data", + "hif_en", "hif_rdy", "hif_clk", "ai_loc" }; +static const char * const rtd1315e_tdm_ai_loc0_groups[] = { + "gpio_57", "gpio_58", "gpio_59", + "gpio_60", "tdm_ai_loc" }; +static const char * const rtd1315e_tdm_ai_loc1_groups[] = { + "hif_data", "hif_en", "hif_rdy", "hif_clk", "tdm_ai_loc" }; +static const char * const rtd1315e_hi_loc0_groups[] = { + "hif_data", "hif_en", "hif_rdy", "hif_clk" }; +static const char * const rtd1315e_hi_m_groups[] = { + "hif_data", "hif_en", "hif_rdy", "hif_clk" }; +static const char * const rtd1315e_vtc_i2so_groups[] = { + "gpio_67", "gpio_68", "gpio_69", "gpio_70"}; +static const char * const rtd1315e_vtc_i2si_loc0_groups[] = { + "gpio_57", "gpio_58", "gpio_59", "gpio_60", "gpio_61", + "vtc_i2si_loc" }; +static const char * const rtd1315e_vtc_i2si_loc1_groups[] = { + "gpio_32", "hif_data", "hif_en", "hif_rdy", "hif_clk", + "vtc_i2si_loc" }; +static const char * const rtd1315e_vtc_dmic_loc0_groups[] = { + "gpio_57", "gpio_58", "gpio_59", "gpio_60", + "vtc_dmic_loc" }; +static const char * const rtd1315e_vtc_dmic_loc1_groups[] = { + "hif_data", "hif_en", "hif_rdy", "hif_clk", + "vtc_dmic_loc" }; +static const char * const rtd1315e_vtc_tdm_loc0_groups[] = { + "gpio_57", "gpio_58", "gpio_59", "gpio_60", + "vtc_tdm_loc" }; +static const char * const rtd1315e_vtc_tdm_loc1_groups[] = { + "hif_data", "hif_en", "hif_rdy", "hif_clk", + "vtc_tdm_loc" }; +static const char * const rtd1315e_dc_fan_groups[] = { "gpio_47" }; +static const char * const rtd1315e_pll_test_loc0_groups[] = { "gpio_0", "gpio_1" }; +static const char * const rtd1315e_pll_test_loc1_groups[] = { "gpio_48", "gpio_49" }; +static const char * const rtd1315e_spdif_groups[] = { "gpio_50" }; +static const char * const rtd1315e_ir_rx_groups[] = { "ir_rx" }; +static const char * const rtd1315e_uart2_disable_groups[] = { "ur2_loc" }; +static const char * const rtd1315e_gspi_disable_groups[] = { "gspi_loc" }; +static const char * const rtd1315e_hi_width_disable_groups[] = { "hi_width" }; +static const char * const rtd1315e_hi_width_1bit_groups[] = { "hi_width" }; +static const char * const rtd1315e_sf_disable_groups[] = { "sf_en" }; +static const char * const rtd1315e_sf_enable_groups[] = { "sf_en" }; +static const char * const rtd1315e_scpu_ejtag_loc0_groups[] = { + "gpio_68", "gpio_69", "gpio_70", "gpio_71", "gpio_72", + "ejtag_scpu_loc" }; +static const char * const rtd1315e_scpu_ejtag_loc1_groups[] = { + "gpio_32", "gpio_33", "hif_data", "hif_en", "hif_clk", + "ejtag_scpu_loc" }; +static const char * const rtd1315e_scpu_ejtag_loc2_groups[] = { + "gpio_57", "gpio_58", "gpio_59", "gpio_60", "gpio_61", + "ejtag_scpu_loc" }; +static const char * const rtd1315e_scpu_ejtag_loc3_groups[] = { + "hif_data" }; +static const char * const rtd1315e_acpu_ejtag_loc0_groups[] = { + "gpio_68", "gpio_69", "gpio_70", "gpio_71", "gpio_72", + "ejtag_acpu_loc" }; +static const char * const rtd1315e_acpu_ejtag_loc1_groups[] = { + "gpio_32", "gpio_33", "hif_data", "hif_en", "hif_clk", + "ejtag_acpu_loc" }; +static const char * const rtd1315e_acpu_ejtag_loc2_groups[] = { + "gpio_57", "gpio_58", "gpio_59", "gpio_60", "gpio_61", + "ejtag_acpu_loc" }; +static const char * const rtd1315e_vcpu_ejtag_loc0_groups[] = { + "gpio_68", "gpio_69", "gpio_70", "gpio_71", "gpio_72", + "ejtag_vcpu_loc" }; +static const char * const rtd1315e_vcpu_ejtag_loc1_groups[] = { + "gpio_32", "gpio_33", "hif_data", "hif_en", "hif_clk", + "ejtag_vcpu_loc" }; +static const char * const rtd1315e_vcpu_ejtag_loc2_groups[] = { + "gpio_57", "gpio_58", "gpio_59", "gpio_60", "gpio_61", + "ejtag_vcpu_loc" }; +static const char * const rtd1315e_aucpu_ejtag_loc0_groups[] = { + "gpio_68", "gpio_69", "gpio_70", "gpio_71", "gpio_72", + "ejtag_aucpu_loc" }; +static const char * const rtd1315e_aucpu_ejtag_loc1_groups[] = { + "gpio_32", "gpio_33", "hif_data", "hif_en", "hif_clk", + "ejtag_aucpu_loc" }; +static const char * const rtd1315e_aucpu_ejtag_loc2_groups[] = { + "gpio_57", "gpio_58", "gpio_59", "gpio_60", "gpio_61", + "ejtag_aucpu_loc" }; +static const char * const rtd1315e_gpu_ejtag_groups[] = { + "gpio_68", "gpio_69", "gpio_70", "gpio_71", "gpio_72" }; + +static const char * const rtd1315e_iso_tristate_groups[] = { + "emmc_rst_n", "emmc_dd_sb", "emmc_clk", "emmc_cmd", + "emmc_data_0", "emmc_data_1", "emmc_data_2", "emmc_data_3", + "emmc_data_4", "emmc_data_5", "emmc_data_6", "emmc_data_7", + "gpio_1", "gpio_7", "gpio_8", "gpio_9", "gpio_10", + "gpio_11", "usb_cc2", "gpio_32", "gpio_33", "hif_data", + "hif_en", "hif_rdy", "hif_clk", "ir_rx", "ur0_rx", + "ur0_tx", "gpio_66", "gpio_67", "gpio_68", "gpio_69", "gpio_70", + "gpio_71", "gpio_72", "gpio_78", "gpio_79", "gpio_80", "gpio_81" }; +static const char * const rtd1315e_dbg_out0_groups[] = { + "gpio_0", "gpio_12", "gpio_13", "gpio_16", "gpio_17", "gpio_26", + "gpio_27", "gpio_28", "gpio_29", "gpio_30", "gpio_34", "gpio_35", + "gpio_46", "gpio_48", "gpio_49", "usb_cc1", "gpio_57", "gpio_58", "gpio_59", "gpio_60" }; +static const char * const rtd1315e_dbg_out1_groups[] = { + "gpio_6", "gpio_14", "gpio_15", "gpio_18", "gpio_19", "gpio_20", + "gpio_25", "gpio_31", "gpio_47", "gpio_50", "gpio_59", "gpio_61", + "gpio_62" }; +static const char * const rtd1315e_standby_dbg_groups[] = { + "gpio_1", "gpio_6", "ir_rx" }; +static const char * const rtd1315e_arm_trace_debug_disable_groups[] = { "arm_trace_dbg_en" }; +static const char * const rtd1315e_arm_trace_debug_enable_groups[] = { "arm_trace_dbg_en" }; +static const char * const rtd1315e_aucpu_ejtag_disable_groups[] = { "ejtag_aucpu_loc" }; +static const char * const rtd1315e_acpu_ejtag_disable_groups[] = { "ejtag_acpu_loc" }; +static const char * const rtd1315e_vcpu_ejtag_disable_groups[] = { "ejtag_vcpu_loc" }; +static const char * const rtd1315e_scpu_ejtag_disable_groups[] = { "ejtag_scpu_loc" }; +static const char * const rtd1315e_vtc_dmic_loc_disable_groups[] = { "vtc_dmic_loc" }; +static const char * const rtd1315e_vtc_tdm_disable_groups[] = { "vtc_tdm_loc" }; +static const char * const rtd1315e_vtc_i2si_disable_groups[] = { "vtc_i2si_loc" }; +static const char * const rtd1315e_tdm_ai_disable_groups[] = { "tdm_ai_loc" }; +static const char * const rtd1315e_ai_disable_groups[] = { "ai_loc" }; +static const char * const rtd1315e_spdif_disable_groups[] = { "spdif_loc" }; +static const char * const rtd1315e_hif_disable_groups[] = { "hif_en_loc" }; +static const char * const rtd1315e_hif_enable_groups[] = { "hif_en_loc" }; +static const char * const rtd1315e_test_loop_groups[] = { "gpio_50" }; +static const char * const rtd1315e_pmic_pwrup_groups[] = { "gpio_78" }; + +#define RTD1315E_FUNC(_name) \ + { \ + .name = # _name, \ + .groups = rtd1315e_ ## _name ## _groups, \ + .num_groups = ARRAY_SIZE(rtd1315e_ ## _name ## _groups), \ + } + +static const struct rtd_pin_func_desc rtd1315e_pin_functions[] = { + RTD1315E_FUNC(gpio), + RTD1315E_FUNC(nf), + RTD1315E_FUNC(emmc), + RTD1315E_FUNC(ao), + RTD1315E_FUNC(gspi_loc0), + RTD1315E_FUNC(gspi_loc1), + RTD1315E_FUNC(uart0), + RTD1315E_FUNC(uart1), + RTD1315E_FUNC(uart2_loc0), + RTD1315E_FUNC(uart2_loc1), + RTD1315E_FUNC(i2c0), + RTD1315E_FUNC(i2c1), + RTD1315E_FUNC(i2c4), + RTD1315E_FUNC(i2c5), + RTD1315E_FUNC(pcie1), + RTD1315E_FUNC(etn_led), + RTD1315E_FUNC(etn_phy), + RTD1315E_FUNC(spi), + RTD1315E_FUNC(pwm0_loc0), + RTD1315E_FUNC(pwm0_loc1), + RTD1315E_FUNC(pwm1_loc0), + RTD1315E_FUNC(pwm1_loc1), + RTD1315E_FUNC(pwm2_loc0), + RTD1315E_FUNC(pwm2_loc1), + RTD1315E_FUNC(pwm3_loc0), + RTD1315E_FUNC(pwm3_loc1), + RTD1315E_FUNC(spdif_optical_loc0), + RTD1315E_FUNC(spdif_optical_loc1), + RTD1315E_FUNC(usb_cc1), + RTD1315E_FUNC(usb_cc2), + RTD1315E_FUNC(sd), + RTD1315E_FUNC(dmic_loc0), + RTD1315E_FUNC(dmic_loc1), + RTD1315E_FUNC(ai_loc0), + RTD1315E_FUNC(ai_loc1), + RTD1315E_FUNC(tdm_ai_loc0), + RTD1315E_FUNC(tdm_ai_loc1), + RTD1315E_FUNC(hi_loc0), + RTD1315E_FUNC(hi_m), + RTD1315E_FUNC(vtc_i2so), + RTD1315E_FUNC(vtc_i2si_loc0), + RTD1315E_FUNC(vtc_i2si_loc1), + RTD1315E_FUNC(vtc_dmic_loc0), + RTD1315E_FUNC(vtc_dmic_loc1), + RTD1315E_FUNC(vtc_tdm_loc0), + RTD1315E_FUNC(vtc_tdm_loc1), + RTD1315E_FUNC(dc_fan), + RTD1315E_FUNC(pll_test_loc0), + RTD1315E_FUNC(pll_test_loc1), + RTD1315E_FUNC(ir_rx), + RTD1315E_FUNC(uart2_disable), + RTD1315E_FUNC(gspi_disable), + RTD1315E_FUNC(hi_width_disable), + RTD1315E_FUNC(hi_width_1bit), + RTD1315E_FUNC(sf_disable), + RTD1315E_FUNC(sf_enable), + RTD1315E_FUNC(scpu_ejtag_loc0), + RTD1315E_FUNC(scpu_ejtag_loc1), + RTD1315E_FUNC(scpu_ejtag_loc2), + RTD1315E_FUNC(scpu_ejtag_loc3), + RTD1315E_FUNC(acpu_ejtag_loc0), + RTD1315E_FUNC(acpu_ejtag_loc1), + RTD1315E_FUNC(acpu_ejtag_loc2), + RTD1315E_FUNC(vcpu_ejtag_loc0), + RTD1315E_FUNC(vcpu_ejtag_loc1), + RTD1315E_FUNC(vcpu_ejtag_loc2), + RTD1315E_FUNC(aucpu_ejtag_loc0), + RTD1315E_FUNC(aucpu_ejtag_loc1), + RTD1315E_FUNC(aucpu_ejtag_loc2), + RTD1315E_FUNC(gpu_ejtag), + RTD1315E_FUNC(iso_tristate), + RTD1315E_FUNC(dbg_out0), + RTD1315E_FUNC(dbg_out1), + RTD1315E_FUNC(standby_dbg), + RTD1315E_FUNC(spdif), + RTD1315E_FUNC(arm_trace_debug_disable), + RTD1315E_FUNC(arm_trace_debug_enable), + RTD1315E_FUNC(aucpu_ejtag_disable), + RTD1315E_FUNC(acpu_ejtag_disable), + RTD1315E_FUNC(vcpu_ejtag_disable), + RTD1315E_FUNC(scpu_ejtag_disable), + RTD1315E_FUNC(vtc_dmic_loc_disable), + RTD1315E_FUNC(vtc_tdm_disable), + RTD1315E_FUNC(vtc_i2si_disable), + RTD1315E_FUNC(tdm_ai_disable), + RTD1315E_FUNC(ai_disable), + RTD1315E_FUNC(spdif_disable), + RTD1315E_FUNC(hif_disable), + RTD1315E_FUNC(hif_enable), + RTD1315E_FUNC(test_loop), + RTD1315E_FUNC(pmic_pwrup), +}; + +#undef RTD1315E_FUNC + +static const struct rtd_pin_desc rtd1315e_iso_muxes[ARRAY_SIZE(rtd1315e_iso_pins)] = { + [RTD1315E_ISO_EMMC_RST_N] = RTK_PIN_MUX(emmc_rst_n, 0x0, GENMASK(3, 0), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "nf"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 0), "emmc"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 0), "iso_tristate")), + [RTD1315E_ISO_EMMC_DD_SB] = RTK_PIN_MUX(emmc_dd_sb, 0x0, GENMASK(7, 4), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 4), "emmc"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 4), "iso_tristate")), + [RTD1315E_ISO_EMMC_CLK] = RTK_PIN_MUX(emmc_clk, 0x0, GENMASK(11, 8), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 8), "nf"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 8), "emmc"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 8), "iso_tristate")), + [RTD1315E_ISO_EMMC_CMD] = RTK_PIN_MUX(emmc_cmd, 0x0, GENMASK(15, 12), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 12), "nf"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 12), "emmc"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 12), "iso_tristate")), + [RTD1315E_ISO_EMMC_DATA_0] = RTK_PIN_MUX(emmc_data_0, 0x0, GENMASK(19, 16), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 16), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 16), "nf"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 16), "emmc"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 16), "iso_tristate")), + [RTD1315E_ISO_EMMC_DATA_1] = RTK_PIN_MUX(emmc_data_1, 0x0, GENMASK(23, 20), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 20), "nf"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 20), "emmc"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 20), "iso_tristate")), + [RTD1315E_ISO_EMMC_DATA_2] = RTK_PIN_MUX(emmc_data_2, 0x0, GENMASK(27, 24), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 24), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 24), "nf"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 24), "emmc"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 24), "iso_tristate")), + [RTD1315E_ISO_EMMC_DATA_3] = RTK_PIN_MUX(emmc_data_3, 0x0, GENMASK(31, 28), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 28), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 28), "nf"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 28), "emmc"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 28), "iso_tristate")), + + [RTD1315E_ISO_EMMC_DATA_4] = RTK_PIN_MUX(emmc_data_4, 0x4, GENMASK(3, 0), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "nf"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 0), "emmc"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 0), "iso_tristate")), + [RTD1315E_ISO_EMMC_DATA_5] = RTK_PIN_MUX(emmc_data_5, 0x4, GENMASK(7, 4), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 4), "nf"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 4), "emmc"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 4), "iso_tristate")), + [RTD1315E_ISO_EMMC_DATA_6] = RTK_PIN_MUX(emmc_data_6, 0x4, GENMASK(11, 8), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 8), "nf"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 8), "emmc"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 8), "iso_tristate")), + [RTD1315E_ISO_EMMC_DATA_7] = RTK_PIN_MUX(emmc_data_7, 0x4, GENMASK(15, 12), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 12), "nf"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 12), "emmc"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 12), "iso_tristate")), + [RTD1315E_ISO_GPIO_0] = RTK_PIN_MUX(gpio_0, 0x4, GENMASK(19, 16), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 16), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 16), "pll_test_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 16), "dbg_out0")), + [RTD1315E_ISO_GPIO_1] = RTK_PIN_MUX(gpio_1, 0x4, GENMASK(23, 20), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 20), "standby_dbg"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 20), "pll_test_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 20), "dmic_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 20), "ai_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 20), "iso_tristate")), + [RTD1315E_ISO_GPIO_6] = RTK_PIN_MUX(gpio_6, 0x4, GENMASK(27, 24), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 24), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 24), "standby_dbg"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 24), "dmic_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 24), "spdif_optical_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 24), "dbg_out1")), + [RTD1315E_ISO_GPIO_7] = RTK_PIN_MUX(gpio_7, 0x4, GENMASK(31, 28), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 28), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 28), "iso_tristate")), + + [RTD1315E_ISO_GPIO_8] = RTK_PIN_MUX(gpio_8, 0x8, GENMASK(3, 0), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "uart1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 0), "gspi_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 0), "iso_tristate")), + [RTD1315E_ISO_GPIO_9] = RTK_PIN_MUX(gpio_9, 0x8, GENMASK(7, 4), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 4), "uart1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 4), "gspi_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 4), "iso_tristate")), + [RTD1315E_ISO_GPIO_10] = RTK_PIN_MUX(gpio_10, 0x8, GENMASK(11, 8), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 8), "uart1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 8), "gspi_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 8), "iso_tristate")), + [RTD1315E_ISO_GPIO_11] = RTK_PIN_MUX(gpio_11, 0x8, GENMASK(15, 12), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 12), "uart1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 12), "gspi_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 12), "iso_tristate")), + [RTD1315E_ISO_GPIO_12] = RTK_PIN_MUX(gpio_12, 0x8, GENMASK(19, 16), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 16), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 16), "i2c0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 16), "dbg_out0")), + [RTD1315E_ISO_GPIO_13] = RTK_PIN_MUX(gpio_13, 0x8, GENMASK(23, 20), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 20), "i2c0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 20), "dbg_out0")), + [RTD1315E_ISO_GPIO_14] = RTK_PIN_MUX(gpio_14, 0x8, GENMASK(27, 24), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 24), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 24), "etn_led"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 24), "etn_phy"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 24), "dbg_out1")), + [RTD1315E_ISO_GPIO_15] = RTK_PIN_MUX(gpio_15, 0x8, GENMASK(31, 28), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 28), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 28), "etn_led"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 28), "etn_phy"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 28), "dbg_out1")), + + [RTD1315E_ISO_GPIO_16] = RTK_PIN_MUX(gpio_16, 0xc, GENMASK(3, 0), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "i2c1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 0), "dbg_out0")), + [RTD1315E_ISO_GPIO_17] = RTK_PIN_MUX(gpio_17, 0xc, GENMASK(7, 4), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 4), "i2c1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 4), "dbg_out0")), + [RTD1315E_ISO_GPIO_18] = RTK_PIN_MUX(gpio_18, 0xc, GENMASK(11, 8), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 8), "uart2_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 8), "gspi_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 8), "dbg_out1")), + [RTD1315E_ISO_GPIO_19] = RTK_PIN_MUX(gpio_19, 0xc, GENMASK(15, 12), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 12), "uart2_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 12), "gspi_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 12), "dbg_out1")), + [RTD1315E_ISO_GPIO_20] = RTK_PIN_MUX(gpio_20, 0xc, GENMASK(19, 16), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 16), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 16), "uart2_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 16), "pwm0_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 16), "gspi_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x6, 16), "spdif_optical_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 16), "dbg_out1")), + [RTD1315E_ISO_USB_CC2] = RTK_PIN_MUX(usb_cc2, 0xc, GENMASK(23, 20), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 20), "usb_cc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 20), "iso_tristate")), + [RTD1315E_ISO_GPIO_25] = RTK_PIN_MUX(gpio_25, 0xc, GENMASK(27, 24), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 24), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 24), "uart2_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 24), "pcie1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 24), "dbg_out1")), + [RTD1315E_ISO_GPIO_26] = RTK_PIN_MUX(gpio_26, 0xc, GENMASK(31, 28), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 28), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 28), "uart2_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 28), "pwm0_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 28), "dbg_out0")), + + [RTD1315E_ISO_GPIO_27] = RTK_PIN_MUX(gpio_27, 0x10, GENMASK(3, 0), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "uart2_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 0), "pwm1_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 0), "dbg_out0")), + [RTD1315E_ISO_GPIO_28] = RTK_PIN_MUX(gpio_28, 0x10, GENMASK(7, 4), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 4), "uart2_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 4), "pwm2_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 4), "dbg_out0")), + [RTD1315E_ISO_GPIO_29] = RTK_PIN_MUX(gpio_29, 0x10, GENMASK(11, 8), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 8), "i2c5"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 8), "pwm1_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 8), "dbg_out0")), + [RTD1315E_ISO_GPIO_30] = RTK_PIN_MUX(gpio_30, 0x10, GENMASK(15, 12), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 12), "pwm2_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 12), "dbg_out0")), + [RTD1315E_ISO_GPIO_31] = RTK_PIN_MUX(gpio_31, 0x10, GENMASK(19, 16), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 16), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 16), "uart2_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 16), "pwm3_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 16), "gspi_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 16), "dbg_out1")), + [RTD1315E_ISO_GPIO_32] = RTK_PIN_MUX(gpio_32, 0x10, GENMASK(23, 20), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 20), "sd"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 20), "aucpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 20), "dmic_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 20), "scpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x6, 20), "acpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x7, 20), "vcpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x8, 20), "ai_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xb, 20), "vtc_i2si_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 20), "iso_tristate")), + [RTD1315E_ISO_GPIO_33] = RTK_PIN_MUX(gpio_33, 0x10, GENMASK(27, 24), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 24), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 24), "sd"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 24), "aucpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 24), "dmic_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 24), "scpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x6, 24), "acpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x7, 24), "vcpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x8, 24), "ai_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 24), "iso_tristate")), + [RTD1315E_ISO_GPIO_34] = RTK_PIN_MUX(gpio_34, 0x10, GENMASK(31, 28), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 28), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 28), "sd"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 28), "dmic_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 28), "i2c4"), + RTK_PIN_FUNC(SHIFT_LEFT(0x8, 28), "ai_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 28), "dbg_out0")), + + [RTD1315E_ISO_GPIO_35] = RTK_PIN_MUX(gpio_35, 0x14, GENMASK(3, 0), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "sd"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 0), "dmic_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 0), "i2c4"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 0), "dbg_out0")), + [RTD1315E_ISO_HIF_DATA] = RTK_PIN_MUX(hif_data, 0x14, GENMASK(7, 4), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 4), "sd"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 4), "aucpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 4), "dmic_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 4), "tdm_ai_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 4), "scpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x6, 4), "acpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x7, 4), "vcpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x8, 4), "ai_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x9, 4), "hi_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xa, 4), "hi_m"), + RTK_PIN_FUNC(SHIFT_LEFT(0xb, 4), "vtc_i2si_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xc, 4), "vtc_tdm_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xd, 4), "vtc_dmic_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xe, 4), "scpu_ejtag_loc3"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 4), "iso_tristate")), + [RTD1315E_ISO_HIF_EN] = RTK_PIN_MUX(hif_en, 0x14, GENMASK(11, 8), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 8), "sd"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 8), "aucpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 8), "dmic_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 8), "tdm_ai_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 8), "scpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x6, 8), "acpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x7, 8), "vcpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x8, 8), "ai_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x9, 8), "hi_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xa, 8), "hi_m"), + RTK_PIN_FUNC(SHIFT_LEFT(0xb, 8), "vtc_i2si_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xc, 8), "vtc_tdm_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xd, 8), "vtc_dmic_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 8), "iso_tristate")), + [RTD1315E_ISO_HIF_RDY] = RTK_PIN_MUX(hif_rdy, 0x14, GENMASK(15, 12), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 12), "sd"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 12), "dmic_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 12), "tdm_ai_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x8, 12), "ai_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x9, 12), "hi_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xa, 12), "hi_m"), + RTK_PIN_FUNC(SHIFT_LEFT(0xb, 12), "vtc_i2si_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xc, 12), "vtc_tdm_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xd, 12), "vtc_dmic_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 12), "iso_tristate")), + [RTD1315E_ISO_HIF_CLK] = RTK_PIN_MUX(hif_clk, 0x14, GENMASK(19, 16), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 16), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 16), "sd"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 16), "aucpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 16), "dmic_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 16), "tdm_ai_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 16), "scpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x6, 16), "acpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x7, 16), "vcpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x8, 16), "ai_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x9, 16), "hi_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xa, 16), "hi_m"), + RTK_PIN_FUNC(SHIFT_LEFT(0xb, 16), "vtc_i2si_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xc, 16), "vtc_tdm_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xd, 16), "vtc_dmic_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 16), "iso_tristate")), + [RTD1315E_ISO_GPIO_46] = RTK_PIN_MUX(gpio_46, 0x14, GENMASK(23, 20), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 20), "i2c5"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 20), "dbg_out0")), + [RTD1315E_ISO_GPIO_47] = RTK_PIN_MUX(gpio_47, 0x14, GENMASK(27, 24), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 24), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 24), "dc_fan"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 24), "pwm3_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 24), "dbg_out1")), + [RTD1315E_ISO_GPIO_48] = RTK_PIN_MUX(gpio_48, 0x14, GENMASK(31, 28), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 28), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 28), "pll_test_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 28), "dbg_out0")), + + [RTD1315E_ISO_GPIO_49] = RTK_PIN_MUX(gpio_49, 0x18, GENMASK(3, 0), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "pll_test_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 0), "dbg_out0")), + [RTD1315E_ISO_GPIO_50] = RTK_PIN_MUX(gpio_50, 0x18, GENMASK(7, 4), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 4), "spdif"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 4), "test_loop"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 4), "dbg_out1")), + [RTD1315E_ISO_USB_CC1] = RTK_PIN_MUX(usb_cc1, 0x18, GENMASK(11, 8), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 8), "usb_cc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 8), "dbg_out0")), + [RTD1315E_ISO_IR_RX] = RTK_PIN_MUX(ir_rx, 0x18, GENMASK(15, 12), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 12), "ir_rx"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 12), "standby_dbg"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 12), "iso_tristate")), + [RTD1315E_ISO_UR0_RX] = RTK_PIN_MUX(ur0_rx, 0x18, GENMASK(19, 16), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 16), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 16), "uart0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 16), "iso_tristate")), + [RTD1315E_ISO_UR0_TX] = RTK_PIN_MUX(ur0_tx, 0x18, GENMASK(23, 20), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 20), "uart0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 20), "iso_tristate")), + [RTD1315E_ISO_GPIO_57] = RTK_PIN_MUX(gpio_57, 0x18, GENMASK(27, 24), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 24), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 24), "tdm_ai_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 24), "ai_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 24), "dmic_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x6, 24), "acpu_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0x7, 24), "vcpu_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0x9, 24), "aucpu_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0xb, 24), "vtc_i2si_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xc, 24), "vtc_tdm_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xd, 24), "vtc_dmic_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xe, 24), "scpu_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 24), "dbg_out0")), + [RTD1315E_ISO_GPIO_58] = RTK_PIN_MUX(gpio_58, 0x18, GENMASK(31, 28), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 28), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 28), "tdm_ai_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 28), "ai_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 28), "dmic_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x6, 28), "acpu_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0x7, 28), "vcpu_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0x9, 28), "aucpu_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0xb, 28), "vtc_i2si_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xc, 28), "vtc_tdm_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xd, 28), "vtc_dmic_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xe, 28), "scpu_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 28), "dbg_out0")), + + [RTD1315E_ISO_GPIO_59] = RTK_PIN_MUX(gpio_59, 0x1c, GENMASK(3, 0), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "tdm_ai_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 0), "ai_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 0), "dmic_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x6, 0), "acpu_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0x7, 0), "vcpu_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0x9, 0), "aucpu_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0xb, 0), "vtc_i2si_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xc, 0), "vtc_tdm_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xd, 0), "vtc_dmic_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xe, 0), "scpu_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 0), "dbg_out1")), + [RTD1315E_ISO_GPIO_60] = RTK_PIN_MUX(gpio_60, 0x1c, GENMASK(7, 4), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 4), "tdm_ai_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 4), "ai_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 4), "dmic_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x6, 4), "acpu_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0x7, 4), "vcpu_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0x9, 4), "aucpu_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0xb, 4), "vtc_i2si_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xc, 4), "vtc_tdm_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xd, 4), "vtc_dmic_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xe, 4), "scpu_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 4), "dbg_out0")), + [RTD1315E_ISO_GPIO_61] = RTK_PIN_MUX(gpio_61, 0x1c, GENMASK(11, 8), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 8), "ai_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 8), "dmic_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x6, 8), "acpu_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0x7, 8), "vcpu_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0x9, 8), "aucpu_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0xb, 8), "vtc_i2si_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xe, 8), "scpu_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 8), "dbg_out1")), + [RTD1315E_ISO_GPIO_62] = RTK_PIN_MUX(gpio_62, 0x1c, GENMASK(15, 12), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 12), "ai_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 12), "dmic_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 12), "dbg_out1")), + [RTD1315E_ISO_GPIO_66] = RTK_PIN_MUX(gpio_66, 0x1c, GENMASK(19, 16), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 16), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0xc, 16), "ao"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 16), "iso_tristate")), + [RTD1315E_ISO_GPIO_67] = RTK_PIN_MUX(gpio_67, 0x1c, GENMASK(23, 20), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0xb, 20), "vtc_i2so"), + RTK_PIN_FUNC(SHIFT_LEFT(0xc, 20), "ao"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 20), "iso_tristate")), + [RTD1315E_ISO_GPIO_68] = RTK_PIN_MUX(gpio_68, 0x1c, GENMASK(27, 24), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 24), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 24), "aucpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 24), "gpu_ejtag"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 24), "scpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x6, 24), "acpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x7, 24), "vcpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xb, 24), "vtc_i2so"), + RTK_PIN_FUNC(SHIFT_LEFT(0xc, 24), "ao"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 24), "iso_tristate")), + [RTD1315E_ISO_GPIO_69] = RTK_PIN_MUX(gpio_69, 0x1c, GENMASK(31, 28), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 28), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 28), "aucpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 28), "gpu_ejtag"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 28), "scpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x6, 28), "acpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x7, 28), "vcpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xb, 28), "vtc_i2so"), + RTK_PIN_FUNC(SHIFT_LEFT(0xc, 28), "ao"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 28), "iso_tristate")), + + [RTD1315E_ISO_GPIO_70] = RTK_PIN_MUX(gpio_70, 0x20, GENMASK(3, 0), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 0), "aucpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 0), "gpu_ejtag"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 0), "scpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x6, 0), "acpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x7, 0), "vcpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xb, 0), "vtc_i2so"), + RTK_PIN_FUNC(SHIFT_LEFT(0xc, 0), "ao"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 0), "iso_tristate")), + [RTD1315E_ISO_GPIO_71] = RTK_PIN_MUX(gpio_71, 0x20, GENMASK(7, 4), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 4), "aucpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 4), "gpu_ejtag"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 4), "scpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x6, 4), "acpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x7, 4), "vcpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xc, 4), "ao"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 4), "iso_tristate")), + [RTD1315E_ISO_GPIO_72] = RTK_PIN_MUX(gpio_72, 0x20, GENMASK(11, 8), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 8), "aucpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 8), "gpu_ejtag"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 8), "scpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x6, 8), "acpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x7, 8), "vcpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xc, 8), "ao"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 8), "iso_tristate")), + [RTD1315E_ISO_GPIO_78] = RTK_PIN_MUX(gpio_78, 0x20, GENMASK(15, 12), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 12), "nf"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 12), "pmic_pwrup"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 12), "spi"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 12), "iso_tristate")), + [RTD1315E_ISO_GPIO_79] = RTK_PIN_MUX(gpio_79, 0x20, GENMASK(19, 16), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 16), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 16), "nf"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 16), "spi"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 16), "iso_tristate")), + [RTD1315E_ISO_GPIO_80] = RTK_PIN_MUX(gpio_80, 0x20, GENMASK(23, 20), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 20), "nf"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 20), "spi"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 20), "iso_tristate")), + [RTD1315E_ISO_GPIO_81] = RTK_PIN_MUX(gpio_81, 0x20, GENMASK(27, 24), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 24), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 24), "nf"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 24), "spi"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 24), "iso_tristate")), + + [RTD1315E_ISO_UR2_LOC] = RTK_PIN_MUX(ur2_loc, 0x120, GENMASK(1, 0), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "uart2_disable"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "uart2_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 0), "uart2_loc1")), + [RTD1315E_ISO_GSPI_LOC] = RTK_PIN_MUX(gspi_loc, 0x120, GENMASK(3, 2), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 2), "gspi_disable"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 2), "gspi_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 2), "gspi_loc1")), + [RTD1315E_ISO_HI_WIDTH] = RTK_PIN_MUX(hi_width, 0x120, GENMASK(9, 8), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "hi_width_disable"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 8), "hi_width_1bit")), + [RTD1315E_ISO_SF_EN] = RTK_PIN_MUX(sf_en, 0x120, GENMASK(11, 11), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 11), "sf_disable"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 11), "sf_enable")), + [RTD1315E_ISO_ARM_TRACE_DBG_EN] = RTK_PIN_MUX(arm_trace_dbg_en, 0x120, GENMASK(12, 12), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "arm_trace_debug_disable"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 12), "arm_trace_debug_enable")), + [RTD1315E_ISO_EJTAG_AUCPU_LOC] = RTK_PIN_MUX(ejtag_aucpu_loc, 0x120, GENMASK(16, 14), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 14), "aucpu_ejtag_disable"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 14), "aucpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 14), "aucpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 14), "aucpu_ejtag_loc2")), + [RTD1315E_ISO_EJTAG_ACPU_LOC] = RTK_PIN_MUX(ejtag_acpu_loc, 0x120, GENMASK(19, 17), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 17), "acpu_ejtag_disable"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 17), "acpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 17), "acpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 17), "acpu_ejtag_loc2")), + [RTD1315E_ISO_EJTAG_VCPU_LOC] = RTK_PIN_MUX(ejtag_vcpu_loc, 0x120, GENMASK(22, 20), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "vcpu_ejtag_disable"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 20), "vcpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 20), "vcpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 20), "vcpu_ejtag_loc2")), + [RTD1315E_ISO_EJTAG_SCPU_LOC] = RTK_PIN_MUX(ejtag_scpu_loc, 0x120, GENMASK(25, 23), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 23), "scpu_ejtag_disable"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 23), "scpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 23), "scpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 23), "scpu_ejtag_loc2")), + [RTD1315E_ISO_DMIC_LOC] = RTK_PIN_MUX(dmic_loc, 0x120, GENMASK(27, 26), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 26), "dmic_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 26), "dmic_loc1")), + + [RTD1315E_ISO_VTC_DMIC_LOC] = RTK_PIN_MUX(vtc_dmic_loc, 0x128, GENMASK(1, 0), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "vtc_dmic_loc_disable"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "vtc_dmic_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 0), "vtc_dmic_loc1")), + [RTD1315E_ISO_VTC_TDM_LOC] = RTK_PIN_MUX(vtc_tdm_loc, 0x128, GENMASK(3, 2), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 2), "vtc_tdm_disable"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 2), "vtc_tdm_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 2), "vtc_tdm_loc1")), + [RTD1315E_ISO_VTC_I2SI_LOC] = RTK_PIN_MUX(vtc_i2si_loc, 0x128, GENMASK(5, 4), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "vtc_i2si_disable"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 4), "vtc_i2si_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 4), "vtc_i2si_loc1")), + [RTD1315E_ISO_TDM_AI_LOC] = RTK_PIN_MUX(tdm_ai_loc, 0x128, GENMASK(7, 6), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 6), "tdm_ai_disable"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 6), "tdm_ai_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 6), "tdm_ai_loc1")), + [RTD1315E_ISO_AI_LOC] = RTK_PIN_MUX(ai_loc, 0x128, GENMASK(9, 8), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "ai_disable"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 8), "ai_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 8), "ai_loc1")), + [RTD1315E_ISO_SPDIF_LOC] = RTK_PIN_MUX(spdif_loc, 0x128, GENMASK(11, 10), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 10), "spdif_disable"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 10), "spdif_optical_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 10), "spdif_optical_loc1")), + + [RTD1315E_ISO_HIF_EN_LOC] = RTK_PIN_MUX(hif_en_loc, 0x12c, GENMASK(2, 0), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 0), "hif_disable"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 0), "hif_enable")), +}; + +static const struct rtd_pin_config_desc rtd1315e_iso_configs[ARRAY_SIZE(rtd1315e_iso_pins)] = { + [RTD1315E_ISO_BOOT_SEL] = RTK_PIN_CONFIG(boot_sel, 0x24, 0, 0, 1, NA, 2, 3, NA), + [RTD1315E_ISO_EMMC_CLK] = RTK_PIN_CONFIG(emmc_clk, 0x24, 4, 0, 1, NA, 2, 12, NA), + [RTD1315E_ISO_EMMC_CMD] = RTK_PIN_CONFIG(emmc_cmd, 0x24, 17, 0, 1, NA, 2, 13, NA), + [RTD1315E_ISO_EMMC_DATA_0] = RTK_PIN_CONFIG(emmc_data_0, 0x28, 0, 0, 1, NA, 2, 12, NA), + [RTD1315E_ISO_EMMC_DATA_1] = RTK_PIN_CONFIG(emmc_data_1, 0x28, 13, 0, 1, NA, 2, 12, NA), + [RTD1315E_ISO_EMMC_DATA_2] = RTK_PIN_CONFIG(emmc_data_2, 0x2c, 0, 0, 1, NA, 2, 12, NA), + [RTD1315E_ISO_EMMC_DATA_3] = RTK_PIN_CONFIG(emmc_data_3, 0x2c, 13, 0, 1, NA, 2, 12, NA), + [RTD1315E_ISO_EMMC_DATA_4] = RTK_PIN_CONFIG(emmc_data_4, 0x30, 0, 0, 1, NA, 2, 12, NA), + [RTD1315E_ISO_EMMC_DATA_5] = RTK_PIN_CONFIG(emmc_data_5, 0x30, 13, 0, 1, NA, 2, 12, NA), + [RTD1315E_ISO_EMMC_DATA_6] = RTK_PIN_CONFIG(emmc_data_6, 0x34, 0, 0, 1, NA, 2, 12, NA), + [RTD1315E_ISO_EMMC_DATA_7] = RTK_PIN_CONFIG(emmc_data_7, 0x34, 13, 0, 1, NA, 2, 12, NA), + [RTD1315E_ISO_EMMC_DD_SB] = RTK_PIN_CONFIG(emmc_dd_sb, 0x38, 0, 0, 1, NA, 2, 12, NA), + [RTD1315E_ISO_EMMC_RST_N] = RTK_PIN_CONFIG(emmc_rst_n, 0x38, 13, 0, 1, NA, 2, 12, NA), + [RTD1315E_ISO_GPIO_1] = RTK_PIN_CONFIG(gpio_1, 0x3c, 0, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1315E_ISO_GPIO_6] = RTK_PIN_CONFIG(gpio_6, 0x3c, 5, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1315E_ISO_GPIO_7] = RTK_PIN_CONFIG(gpio_7, 0x3c, 10, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1315E_ISO_GPIO_8] = RTK_PIN_CONFIG(gpio_8, 0x3c, 15, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1315E_ISO_GPIO_9] = RTK_PIN_CONFIG(gpio_9, 0x3c, 20, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1315E_ISO_GPIO_10] = RTK_PIN_CONFIG(gpio_10, 0x3c, 25, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1315E_ISO_GPIO_11] = RTK_PIN_CONFIG(gpio_11, 0x40, 0, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1315E_ISO_GPIO_12] = RTK_PIN_CONFIG(gpio_12, 0x40, 5, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1315E_ISO_GPIO_13] = RTK_PIN_CONFIG(gpio_13, 0x40, 10, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1315E_ISO_GPIO_14] = RTK_PIN_CONFIG(gpio_14, 0x40, 15, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1315E_ISO_GPIO_15] = RTK_PIN_CONFIG(gpio_15, 0x40, 20, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1315E_ISO_GPIO_16] = RTK_PIN_CONFIG(gpio_16, 0x40, 25, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1315E_ISO_GPIO_17] = RTK_PIN_CONFIG(gpio_17, 0x44, 0, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1315E_ISO_GPIO_18] = RTK_PIN_CONFIG(gpio_18, 0x44, 5, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1315E_ISO_GPIO_19] = RTK_PIN_CONFIG(gpio_19, 0x44, 10, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1315E_ISO_GPIO_20] = RTK_PIN_CONFIG(gpio_20, 0x44, 15, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1315E_ISO_GPIO_25] = RTK_PIN_CONFIG(gpio_25, 0x44, 20, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1315E_ISO_GPIO_26] = RTK_PIN_CONFIG(gpio_26, 0x44, 25, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1315E_ISO_GPIO_27] = RTK_PIN_CONFIG(gpio_27, 0x48, 0, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1315E_ISO_GPIO_28] = RTK_PIN_CONFIG(gpio_28, 0x48, 6, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1315E_ISO_GPIO_29] = RTK_PIN_CONFIG(gpio_29, 0x48, 12, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1315E_ISO_GPIO_30] = RTK_PIN_CONFIG(gpio_30, 0x48, 17, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1315E_ISO_GPIO_31] = RTK_PIN_CONFIG(gpio_31, 0x4c, 0, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1315E_ISO_GPIO_32] = RTK_PIN_CONFIG(gpio_32, 0x4c, 5, 0, 1, NA, 2, 12, NA), + [RTD1315E_ISO_GPIO_33] = RTK_PIN_CONFIG(gpio_33, 0x4c, 18, 0, 1, NA, 2, 12, NA), + [RTD1315E_ISO_GPIO_34] = RTK_PIN_CONFIG(gpio_34, 0x50, 0, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1315E_ISO_GPIO_35] = RTK_PIN_CONFIG(gpio_35, 0x50, 5, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1315E_ISO_GPIO_46] = RTK_PIN_CONFIG(gpio_46, 0x50, 10, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1315E_ISO_GPIO_47] = RTK_PIN_CONFIG(gpio_47, 0x50, 15, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1315E_ISO_GPIO_48] = RTK_PIN_CONFIG(gpio_48, 0x50, 20, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1315E_ISO_GPIO_49] = RTK_PIN_CONFIG(gpio_49, 0x50, 25, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1315E_ISO_GPIO_50] = RTK_PIN_CONFIG(gpio_50, 0x54, 0, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1315E_ISO_GPIO_57] = RTK_PIN_CONFIG(gpio_57, 0x54, 5, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1315E_ISO_GPIO_58] = RTK_PIN_CONFIG(gpio_58, 0x54, 10, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1315E_ISO_GPIO_59] = RTK_PIN_CONFIG(gpio_59, 0x54, 15, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1315E_ISO_GPIO_60] = RTK_PIN_CONFIG(gpio_60, 0x54, 20, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1315E_ISO_GPIO_61] = RTK_PIN_CONFIG(gpio_61, 0x54, 25, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1315E_ISO_GPIO_62] = RTK_PIN_CONFIG(gpio_62, 0x58, 0, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1315E_ISO_GPIO_66] = RTK_PIN_CONFIG(gpio_66, 0x58, 5, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1315E_ISO_GPIO_67] = RTK_PIN_CONFIG(gpio_67, 0x58, 10, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1315E_ISO_GPIO_68] = RTK_PIN_CONFIG(gpio_68, 0x58, 15, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1315E_ISO_GPIO_69] = RTK_PIN_CONFIG(gpio_69, 0x58, 20, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1315E_ISO_GPIO_70] = RTK_PIN_CONFIG(gpio_70, 0x58, 25, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1315E_ISO_GPIO_71] = RTK_PIN_CONFIG(gpio_71, 0x5c, 0, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1315E_ISO_GPIO_72] = RTK_PIN_CONFIG(gpio_72, 0x5c, 5, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1315E_ISO_GPIO_78] = RTK_PIN_CONFIG(gpio_78, 0x5c, 10, 0, 1, NA, 2, 12, NA), + [RTD1315E_ISO_GPIO_79] = RTK_PIN_CONFIG(gpio_79, 0x60, 0, 0, 1, NA, 2, 12, NA), + [RTD1315E_ISO_GPIO_80] = RTK_PIN_CONFIG(gpio_80, 0x60, 13, 0, 1, NA, 2, 12, NA), + [RTD1315E_ISO_GPIO_81] = RTK_PIN_CONFIG(gpio_81, 0x64, 0, 0, 1, NA, 2, 12, NA), + [RTD1315E_ISO_HIF_CLK] = RTK_PIN_CONFIG(hif_clk, 0x64, 13, 0, 1, NA, 2, 12, NA), + [RTD1315E_ISO_HIF_DATA] = RTK_PIN_CONFIG(hif_data, 0x68, 0, 0, 1, NA, 2, 12, NA), + [RTD1315E_ISO_HIF_EN] = RTK_PIN_CONFIG(hif_en, 0x68, 13, 0, 1, NA, 2, 12, NA), + [RTD1315E_ISO_HIF_RDY] = RTK_PIN_CONFIG(hif_rdy, 0x68, 26, 0, 1, NA, 2, 12, NA), + [RTD1315E_ISO_IR_RX] = RTK_PIN_CONFIG(ir_rx, 0x6c, 7, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1315E_ISO_RESET_N] = RTK_PIN_CONFIG(reset_n, 0x6c, 12, 0, 1, NA, 2, 3, PADDRI_4_8), + [RTD1315E_ISO_SCAN_SWITCH] = RTK_PIN_CONFIG(scan_switch, 0x6c, 16, NA, NA, 0, 1, 2, PADDRI_4_8), + [RTD1315E_ISO_TESTMODE] = RTK_PIN_CONFIG(testmode, 0x6c, 19, 0, 1, NA, 2, 3, PADDRI_4_8), + [RTD1315E_ISO_UR0_RX] = RTK_PIN_CONFIG(ur0_rx, 0x6c, 23, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1315E_ISO_UR0_TX] = RTK_PIN_CONFIG(ur0_tx, 0x6c, 28, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1315E_ISO_USB_CC1] = RTK_PIN_CONFIG(usb_cc1, 0x70, 1, NA, NA, 0, 1, 2, PADDRI_4_8), + [RTD1315E_ISO_USB_CC2] = RTK_PIN_CONFIG(usb_cc2, 0x70, 4, NA, NA, 0, 1, 2, PADDRI_4_8), + [RTD1315E_ISO_WD_RSET] = RTK_PIN_CONFIG(wd_rset, 0x70, 7, 1, 2, 0, 3, 4, PADDRI_4_8), +}; + +static const struct rtd_pin_sconfig_desc rtd1315e_iso_sconfigs[] = { + RTK_PIN_SCONFIG(emmc_clk, 0x24, 7, 3, 10, 3, 13, 3), + RTK_PIN_SCONFIG(emmc_cmd, 0x24, 20, 3, 23, 3, 26, 3), + RTK_PIN_SCONFIG(emmc_data_0, 0x28, 3, 3, 6, 3, 9, 3), + RTK_PIN_SCONFIG(emmc_data_1, 0x28, 16, 3, 19, 3, 22, 3), + RTK_PIN_SCONFIG(emmc_data_2, 0x2c, 3, 3, 6, 3, 9, 3), + RTK_PIN_SCONFIG(emmc_data_3, 0x2c, 16, 3, 19, 3, 22, 3), + RTK_PIN_SCONFIG(emmc_data_4, 0x30, 3, 3, 6, 3, 9, 3), + RTK_PIN_SCONFIG(emmc_data_5, 0x30, 16, 3, 19, 3, 22, 3), + RTK_PIN_SCONFIG(emmc_data_6, 0x34, 3, 3, 6, 3, 9, 3), + RTK_PIN_SCONFIG(emmc_data_7, 0x34, 16, 3, 19, 3, 22, 3), + RTK_PIN_SCONFIG(emmc_dd_sb, 0x38, 3, 3, 6, 3, 9, 3), + RTK_PIN_SCONFIG(emmc_rst_n, 0x38, 16, 3, 19, 3, 22, 3), + RTK_PIN_SCONFIG(gpio_32, 0x4c, 8, 3, 11, 3, 14, 3), + RTK_PIN_SCONFIG(gpio_33, 0x4c, 21, 3, 24, 3, 27, 3), + RTK_PIN_SCONFIG(gpio_78, 0x5c, 13, 3, 16, 3, 19, 3), + RTK_PIN_SCONFIG(gpio_79, 0x60, 3, 3, 6, 3, 9, 3), + RTK_PIN_SCONFIG(gpio_80, 0x60, 16, 3, 19, 3, 22, 3), + RTK_PIN_SCONFIG(gpio_81, 0x64, 3, 3, 6, 3, 9, 3), + RTK_PIN_SCONFIG(hif_clk, 0x64, 16, 3, 19, 3, 22, 3), + RTK_PIN_SCONFIG(hif_data, 0x68, 3, 3, 6, 3, 9, 3), + RTK_PIN_SCONFIG(hif_en, 0x68, 16, 3, 19, 3, 22, 3), + RTK_PIN_SCONFIG(hif_rdy, 0x68, 29, 3, 32, 3, 35, 3), + +}; + +static const struct rtd_pinctrl_desc rtd1315e_iso_pinctrl_desc = { + .pins = rtd1315e_iso_pins, + .num_pins = ARRAY_SIZE(rtd1315e_iso_pins), + .groups = rtd1315e_pin_groups, + .num_groups = ARRAY_SIZE(rtd1315e_pin_groups), + .functions = rtd1315e_pin_functions, + .num_functions = ARRAY_SIZE(rtd1315e_pin_functions), + .muxes = rtd1315e_iso_muxes, + .num_muxes = ARRAY_SIZE(rtd1315e_iso_muxes), + .configs = rtd1315e_iso_configs, + .num_configs = ARRAY_SIZE(rtd1315e_iso_configs), + .sconfigs = rtd1315e_iso_sconfigs, + .num_sconfigs = ARRAY_SIZE(rtd1315e_iso_sconfigs), +}; + +static int rtd1315e_pinctrl_probe(struct platform_device *pdev) +{ + return rtd_pinctrl_probe(pdev, &rtd1315e_iso_pinctrl_desc); +} + +static const struct of_device_id rtd1315e_pinctrl_of_match[] = { + { .compatible = "realtek,rtd1315e-pinctrl", }, + {}, +}; + +static struct platform_driver rtd1315e_pinctrl_driver = { + .driver = { + .name = "rtd1315e-pinctrl", + .of_match_table = rtd1315e_pinctrl_of_match, + }, + .probe = rtd1315e_pinctrl_probe, +}; + +static int __init rtd1315e_pinctrl_init(void) +{ + return platform_driver_register(&rtd1315e_pinctrl_driver); +} +arch_initcall(rtd1315e_pinctrl_init); + +static void __exit rtd1315e_pinctrl_exit(void) +{ + platform_driver_unregister(&rtd1315e_pinctrl_driver); +} +module_exit(rtd1315e_pinctrl_exit); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Realtek Semiconductor Corporation"); +MODULE_DESCRIPTION("Realtek DHC SoC RTD1315E pinctrl driver"); diff --git a/drivers/pinctrl/realtek/pinctrl-rtd1319d.c b/drivers/pinctrl/realtek/pinctrl-rtd1319d.c new file mode 100644 index 000000000000..b1a654ac30dc --- /dev/null +++ b/drivers/pinctrl/realtek/pinctrl-rtd1319d.c @@ -0,0 +1,1610 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Realtek DHC 1319D pin controller driver + * + * Copyright (c) 2023 Realtek Semiconductor Corp. + * + */ + +#include <linux/module.h> +#include <linux/of.h> +#include <linux/platform_device.h> +#include <linux/pinctrl/pinctrl.h> + +#include "pinctrl-rtd.h" + +enum rtd13xxd_iso_pins { + RTD1319D_ISO_GPIO_0 = 0, + RTD1319D_ISO_GPIO_1, + RTD1319D_ISO_GPIO_2, + RTD1319D_ISO_GPIO_3, + RTD1319D_ISO_GPIO_4, + RTD1319D_ISO_GPIO_5, + RTD1319D_ISO_GPIO_6, + RTD1319D_ISO_GPIO_7, + RTD1319D_ISO_GPIO_8, + RTD1319D_ISO_GPIO_9, + RTD1319D_ISO_GPIO_10, + RTD1319D_ISO_GPIO_11, + RTD1319D_ISO_GPIO_12, + RTD1319D_ISO_GPIO_13, + RTD1319D_ISO_GPIO_14, + RTD1319D_ISO_GPIO_15, + RTD1319D_ISO_GPIO_16, + RTD1319D_ISO_GPIO_17, + RTD1319D_ISO_GPIO_18, + RTD1319D_ISO_GPIO_19, + RTD1319D_ISO_GPIO_20, + RTD1319D_ISO_GPIO_21, + RTD1319D_ISO_GPIO_22, + RTD1319D_ISO_GPIO_23, + RTD1319D_ISO_USB_CC2, + RTD1319D_ISO_GPIO_25, + RTD1319D_ISO_GPIO_26, + RTD1319D_ISO_GPIO_27, + RTD1319D_ISO_GPIO_28, + RTD1319D_ISO_GPIO_29, + RTD1319D_ISO_GPIO_30, + RTD1319D_ISO_GPIO_31, + RTD1319D_ISO_GPIO_32, + RTD1319D_ISO_GPIO_33, + RTD1319D_ISO_GPIO_34, + RTD1319D_ISO_GPIO_35, + RTD1319D_ISO_HIF_DATA, + RTD1319D_ISO_HIF_EN, + RTD1319D_ISO_HIF_RDY, + RTD1319D_ISO_HIF_CLK, + RTD1319D_ISO_GPIO_40, + RTD1319D_ISO_GPIO_41, + RTD1319D_ISO_GPIO_42, + RTD1319D_ISO_GPIO_43, + RTD1319D_ISO_GPIO_44, + RTD1319D_ISO_GPIO_45, + RTD1319D_ISO_GPIO_46, + RTD1319D_ISO_GPIO_47, + RTD1319D_ISO_GPIO_48, + RTD1319D_ISO_GPIO_49, + RTD1319D_ISO_GPIO_50, + RTD1319D_ISO_USB_CC1, + RTD1319D_ISO_GPIO_52, + RTD1319D_ISO_GPIO_53, + RTD1319D_ISO_IR_RX, + RTD1319D_ISO_UR0_RX, + RTD1319D_ISO_UR0_TX, + RTD1319D_ISO_GPIO_57, + RTD1319D_ISO_GPIO_58, + RTD1319D_ISO_GPIO_59, + RTD1319D_ISO_GPIO_60, + RTD1319D_ISO_GPIO_61, + RTD1319D_ISO_GPIO_62, + RTD1319D_ISO_GPIO_63, + RTD1319D_ISO_GPIO_64, + RTD1319D_ISO_EMMC_RST_N, + RTD1319D_ISO_EMMC_DD_SB, + RTD1319D_ISO_EMMC_CLK, + RTD1319D_ISO_EMMC_CMD, + RTD1319D_ISO_EMMC_DATA_0, + RTD1319D_ISO_EMMC_DATA_1, + RTD1319D_ISO_EMMC_DATA_2, + RTD1319D_ISO_EMMC_DATA_3, + RTD1319D_ISO_EMMC_DATA_4, + RTD1319D_ISO_EMMC_DATA_5, + RTD1319D_ISO_EMMC_DATA_6, + RTD1319D_ISO_EMMC_DATA_7, + RTD1319D_ISO_GPIO_DUMMY_77, + RTD1319D_ISO_GPIO_78, + RTD1319D_ISO_GPIO_79, + RTD1319D_ISO_GPIO_80, + RTD1319D_ISO_GPIO_81, + RTD1319D_ISO_UR2_LOC, + RTD1319D_ISO_GSPI_LOC, + RTD1319D_ISO_HI_WIDTH, + RTD1319D_ISO_SF_EN, + RTD1319D_ISO_ARM_TRACE_DBG_EN, + RTD1319D_ISO_EJTAG_AUCPU_LOC, + RTD1319D_ISO_EJTAG_ACPU_LOC, + RTD1319D_ISO_EJTAG_VCPU_LOC, + RTD1319D_ISO_EJTAG_SCPU_LOC, + RTD1319D_ISO_DMIC_LOC, + RTD1319D_ISO_EJTAG_SECPU_LOC, + RTD1319D_ISO_VTC_DMIC_LOC, + RTD1319D_ISO_VTC_TDM_LOC, + RTD1319D_ISO_VTC_I2SI_LOC, + RTD1319D_ISO_TDM_AI_LOC, + RTD1319D_ISO_AI_LOC, + RTD1319D_ISO_SPDIF_LOC, + RTD1319D_ISO_HIF_EN_LOC, + RTD1319D_ISO_SC0_LOC, + RTD1319D_ISO_SC1_LOC, + RTD1319D_ISO_SCAN_SWITCH, + RTD1319D_ISO_WD_RSET, + RTD1319D_ISO_BOOT_SEL, + RTD1319D_ISO_RESET_N, + RTD1319D_ISO_TESTMODE, +}; + +static const struct pinctrl_pin_desc rtd1319d_iso_pins[] = { + PINCTRL_PIN(RTD1319D_ISO_GPIO_0, "gpio_0"), + PINCTRL_PIN(RTD1319D_ISO_GPIO_1, "gpio_1"), + PINCTRL_PIN(RTD1319D_ISO_GPIO_2, "gpio_2"), + PINCTRL_PIN(RTD1319D_ISO_GPIO_3, "gpio_3"), + PINCTRL_PIN(RTD1319D_ISO_GPIO_4, "gpio_4"), + PINCTRL_PIN(RTD1319D_ISO_GPIO_5, "gpio_5"), + PINCTRL_PIN(RTD1319D_ISO_GPIO_6, "gpio_6"), + PINCTRL_PIN(RTD1319D_ISO_GPIO_7, "gpio_7"), + PINCTRL_PIN(RTD1319D_ISO_GPIO_8, "gpio_8"), + PINCTRL_PIN(RTD1319D_ISO_GPIO_9, "gpio_9"), + PINCTRL_PIN(RTD1319D_ISO_GPIO_10, "gpio_10"), + PINCTRL_PIN(RTD1319D_ISO_GPIO_11, "gpio_11"), + PINCTRL_PIN(RTD1319D_ISO_GPIO_12, "gpio_12"), + PINCTRL_PIN(RTD1319D_ISO_GPIO_13, "gpio_13"), + PINCTRL_PIN(RTD1319D_ISO_GPIO_14, "gpio_14"), + PINCTRL_PIN(RTD1319D_ISO_GPIO_15, "gpio_15"), + PINCTRL_PIN(RTD1319D_ISO_GPIO_16, "gpio_16"), + PINCTRL_PIN(RTD1319D_ISO_GPIO_17, "gpio_17"), + PINCTRL_PIN(RTD1319D_ISO_GPIO_18, "gpio_18"), + PINCTRL_PIN(RTD1319D_ISO_GPIO_19, "gpio_19"), + PINCTRL_PIN(RTD1319D_ISO_GPIO_20, "gpio_20"), + PINCTRL_PIN(RTD1319D_ISO_GPIO_21, "gpio_21"), + PINCTRL_PIN(RTD1319D_ISO_GPIO_22, "gpio_22"), + PINCTRL_PIN(RTD1319D_ISO_GPIO_23, "gpio_23"), + PINCTRL_PIN(RTD1319D_ISO_USB_CC2, "usb_cc2"), + PINCTRL_PIN(RTD1319D_ISO_GPIO_25, "gpio_25"), + PINCTRL_PIN(RTD1319D_ISO_GPIO_26, "gpio_26"), + PINCTRL_PIN(RTD1319D_ISO_GPIO_27, "gpio_27"), + PINCTRL_PIN(RTD1319D_ISO_GPIO_28, "gpio_28"), + PINCTRL_PIN(RTD1319D_ISO_GPIO_29, "gpio_29"), + PINCTRL_PIN(RTD1319D_ISO_GPIO_30, "gpio_30"), + PINCTRL_PIN(RTD1319D_ISO_GPIO_31, "gpio_31"), + PINCTRL_PIN(RTD1319D_ISO_GPIO_32, "gpio_32"), + PINCTRL_PIN(RTD1319D_ISO_GPIO_33, "gpio_33"), + PINCTRL_PIN(RTD1319D_ISO_GPIO_34, "gpio_34"), + PINCTRL_PIN(RTD1319D_ISO_GPIO_35, "gpio_35"), + PINCTRL_PIN(RTD1319D_ISO_HIF_DATA, "hif_data"), + PINCTRL_PIN(RTD1319D_ISO_HIF_EN, "hif_en"), + PINCTRL_PIN(RTD1319D_ISO_HIF_RDY, "hif_rdy"), + PINCTRL_PIN(RTD1319D_ISO_HIF_CLK, "hif_clk"), + PINCTRL_PIN(RTD1319D_ISO_GPIO_40, "gpio_40"), + PINCTRL_PIN(RTD1319D_ISO_GPIO_41, "gpio_41"), + PINCTRL_PIN(RTD1319D_ISO_GPIO_42, "gpio_42"), + PINCTRL_PIN(RTD1319D_ISO_GPIO_43, "gpio_43"), + PINCTRL_PIN(RTD1319D_ISO_GPIO_44, "gpio_44"), + PINCTRL_PIN(RTD1319D_ISO_GPIO_45, "gpio_45"), + PINCTRL_PIN(RTD1319D_ISO_GPIO_46, "gpio_46"), + PINCTRL_PIN(RTD1319D_ISO_GPIO_47, "gpio_47"), + PINCTRL_PIN(RTD1319D_ISO_GPIO_48, "gpio_48"), + PINCTRL_PIN(RTD1319D_ISO_GPIO_49, "gpio_49"), + PINCTRL_PIN(RTD1319D_ISO_GPIO_50, "gpio_50"), + PINCTRL_PIN(RTD1319D_ISO_USB_CC1, "usb_cc1"), + PINCTRL_PIN(RTD1319D_ISO_GPIO_52, "gpio_52"), + PINCTRL_PIN(RTD1319D_ISO_GPIO_53, "gpio_53"), + PINCTRL_PIN(RTD1319D_ISO_IR_RX, "ir_rx"), + PINCTRL_PIN(RTD1319D_ISO_UR0_RX, "ur0_rx"), + PINCTRL_PIN(RTD1319D_ISO_UR0_TX, "ur0_tx"), + PINCTRL_PIN(RTD1319D_ISO_GPIO_57, "gpio_57"), + PINCTRL_PIN(RTD1319D_ISO_GPIO_58, "gpio_58"), + PINCTRL_PIN(RTD1319D_ISO_GPIO_59, "gpio_59"), + PINCTRL_PIN(RTD1319D_ISO_GPIO_60, "gpio_60"), + PINCTRL_PIN(RTD1319D_ISO_GPIO_61, "gpio_61"), + PINCTRL_PIN(RTD1319D_ISO_GPIO_62, "gpio_62"), + PINCTRL_PIN(RTD1319D_ISO_GPIO_63, "gpio_63"), + PINCTRL_PIN(RTD1319D_ISO_GPIO_64, "gpio_64"), + PINCTRL_PIN(RTD1319D_ISO_EMMC_RST_N, "emmc_rst_n"), + PINCTRL_PIN(RTD1319D_ISO_EMMC_DD_SB, "emmc_dd_sb"), + PINCTRL_PIN(RTD1319D_ISO_EMMC_CLK, "emmc_clk"), + PINCTRL_PIN(RTD1319D_ISO_EMMC_CMD, "emmc_cmd"), + PINCTRL_PIN(RTD1319D_ISO_EMMC_DATA_0, "emmc_data_0"), + PINCTRL_PIN(RTD1319D_ISO_EMMC_DATA_1, "emmc_data_1"), + PINCTRL_PIN(RTD1319D_ISO_EMMC_DATA_2, "emmc_data_2"), + PINCTRL_PIN(RTD1319D_ISO_EMMC_DATA_3, "emmc_data_3"), + PINCTRL_PIN(RTD1319D_ISO_EMMC_DATA_4, "emmc_data_4"), + PINCTRL_PIN(RTD1319D_ISO_EMMC_DATA_5, "emmc_data_5"), + PINCTRL_PIN(RTD1319D_ISO_EMMC_DATA_6, "emmc_data_6"), + PINCTRL_PIN(RTD1319D_ISO_EMMC_DATA_7, "emmc_data_7"), + PINCTRL_PIN(RTD1319D_ISO_GPIO_DUMMY_77, "dummy"), + PINCTRL_PIN(RTD1319D_ISO_GPIO_78, "gpio_78"), + PINCTRL_PIN(RTD1319D_ISO_GPIO_79, "gpio_79"), + PINCTRL_PIN(RTD1319D_ISO_GPIO_80, "gpio_80"), + PINCTRL_PIN(RTD1319D_ISO_GPIO_81, "gpio_81"), + PINCTRL_PIN(RTD1319D_ISO_UR2_LOC, "ur2_loc"), + PINCTRL_PIN(RTD1319D_ISO_GSPI_LOC, "gspi_loc"), + PINCTRL_PIN(RTD1319D_ISO_HI_WIDTH, "hi_width"), + PINCTRL_PIN(RTD1319D_ISO_SF_EN, "sf_en"), + PINCTRL_PIN(RTD1319D_ISO_ARM_TRACE_DBG_EN, "arm_trace_dbg_en"), + PINCTRL_PIN(RTD1319D_ISO_EJTAG_AUCPU_LOC, "ejtag_aucpu_loc"), + PINCTRL_PIN(RTD1319D_ISO_EJTAG_ACPU_LOC, "ejtag_acpu_loc"), + PINCTRL_PIN(RTD1319D_ISO_EJTAG_VCPU_LOC, "ejtag_vcpu_loc"), + PINCTRL_PIN(RTD1319D_ISO_EJTAG_SCPU_LOC, "ejtag_scpu_loc"), + PINCTRL_PIN(RTD1319D_ISO_DMIC_LOC, "dmic_loc"), + PINCTRL_PIN(RTD1319D_ISO_EJTAG_SECPU_LOC, "ejtag_secpu_loc"), + PINCTRL_PIN(RTD1319D_ISO_VTC_DMIC_LOC, "vtc_dmic_loc"), + PINCTRL_PIN(RTD1319D_ISO_VTC_TDM_LOC, "vtc_tdm_loc"), + PINCTRL_PIN(RTD1319D_ISO_VTC_I2SI_LOC, "vtc_i2si_loc"), + PINCTRL_PIN(RTD1319D_ISO_TDM_AI_LOC, "tdm_ai_loc"), + PINCTRL_PIN(RTD1319D_ISO_AI_LOC, "ai_loc"), + PINCTRL_PIN(RTD1319D_ISO_SPDIF_LOC, "spdif_loc"), + PINCTRL_PIN(RTD1319D_ISO_HIF_EN_LOC, "hif_en_loc"), + PINCTRL_PIN(RTD1319D_ISO_SC0_LOC, "sc0_loc"), + PINCTRL_PIN(RTD1319D_ISO_SC1_LOC, "sc1_loc"), + PINCTRL_PIN(RTD1319D_ISO_SCAN_SWITCH, "scan_switch"), + PINCTRL_PIN(RTD1319D_ISO_WD_RSET, "wd_rset"), + PINCTRL_PIN(RTD1319D_ISO_BOOT_SEL, "boot_sel"), + PINCTRL_PIN(RTD1319D_ISO_RESET_N, "reset_n"), + PINCTRL_PIN(RTD1319D_ISO_TESTMODE, "testmode"), +}; + +/* Tagged as __maybe_unused since there are pins we may use in the future */ +#define DECLARE_RTD1319D_PIN(_pin, _name) \ + static const unsigned int rtd1319d_## _name ##_pins[] __maybe_unused = { _pin } + +DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_0, gpio_0); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_1, gpio_1); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_2, gpio_2); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_3, gpio_3); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_4, gpio_4); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_5, gpio_5); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_6, gpio_6); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_7, gpio_7); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_8, gpio_8); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_9, gpio_9); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_10, gpio_10); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_11, gpio_11); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_12, gpio_12); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_13, gpio_13); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_14, gpio_14); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_15, gpio_15); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_16, gpio_16); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_17, gpio_17); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_18, gpio_18); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_19, gpio_19); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_20, gpio_20); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_21, gpio_21); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_22, gpio_22); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_23, gpio_23); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_USB_CC2, usb_cc2); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_25, gpio_25); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_26, gpio_26); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_27, gpio_27); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_28, gpio_28); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_29, gpio_29); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_30, gpio_30); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_31, gpio_31); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_32, gpio_32); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_33, gpio_33); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_34, gpio_34); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_35, gpio_35); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_HIF_DATA, hif_data); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_HIF_EN, hif_en); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_HIF_RDY, hif_rdy); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_HIF_CLK, hif_clk); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_40, gpio_40); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_41, gpio_41); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_42, gpio_42); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_43, gpio_43); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_44, gpio_44); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_45, gpio_45); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_46, gpio_46); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_47, gpio_47); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_48, gpio_48); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_49, gpio_49); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_50, gpio_50); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_USB_CC1, usb_cc1); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_52, gpio_52); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_53, gpio_53); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_IR_RX, ir_rx); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_UR0_RX, ur0_rx); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_UR0_TX, ur0_tx); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_57, gpio_57); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_58, gpio_58); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_59, gpio_59); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_60, gpio_60); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_61, gpio_61); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_62, gpio_62); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_63, gpio_63); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_64, gpio_64); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_EMMC_RST_N, emmc_rst_n); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_EMMC_DD_SB, emmc_dd_sb); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_EMMC_CLK, emmc_clk); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_EMMC_CMD, emmc_cmd); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_EMMC_DATA_0, emmc_data_0); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_EMMC_DATA_1, emmc_data_1); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_EMMC_DATA_2, emmc_data_2); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_EMMC_DATA_3, emmc_data_3); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_EMMC_DATA_4, emmc_data_4); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_EMMC_DATA_5, emmc_data_5); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_EMMC_DATA_6, emmc_data_6); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_EMMC_DATA_7, emmc_data_7); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_78, gpio_78); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_79, gpio_79); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_80, gpio_80); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_81, gpio_81); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_UR2_LOC, ur2_loc); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_GSPI_LOC, gspi_loc); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_HI_WIDTH, hi_width); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_SF_EN, sf_en); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_ARM_TRACE_DBG_EN, arm_trace_dbg_en); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_EJTAG_AUCPU_LOC, ejtag_aucpu_loc); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_EJTAG_ACPU_LOC, ejtag_acpu_loc); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_EJTAG_VCPU_LOC, ejtag_vcpu_loc); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_EJTAG_SCPU_LOC, ejtag_scpu_loc); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_DMIC_LOC, dmic_loc); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_EJTAG_SECPU_LOC, ejtag_secpu_loc); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_VTC_DMIC_LOC, vtc_dmic_loc); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_VTC_TDM_LOC, vtc_tdm_loc); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_VTC_I2SI_LOC, vtc_i2si_loc); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_TDM_AI_LOC, tdm_ai_loc); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_AI_LOC, ai_loc); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_SPDIF_LOC, spdif_loc); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_HIF_EN_LOC, hif_en_loc); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_SC0_LOC, sc0_loc); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_SC1_LOC, sc1_loc); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_SCAN_SWITCH, scan_switch); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_WD_RSET, wd_rset); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_BOOT_SEL, boot_sel); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_RESET_N, reset_n); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_TESTMODE, testmode); + +#define RTD1319D_GROUP(_name) \ + { \ + .name = # _name, \ + .pins = rtd1319d_ ## _name ## _pins, \ + .num_pins = ARRAY_SIZE(rtd1319d_ ## _name ## _pins), \ + } + +static const struct rtd_pin_group_desc rtd1319d_pin_groups[] = { + RTD1319D_GROUP(gpio_0), + RTD1319D_GROUP(gpio_1), + RTD1319D_GROUP(gpio_2), + RTD1319D_GROUP(gpio_3), + RTD1319D_GROUP(gpio_4), + RTD1319D_GROUP(gpio_5), + RTD1319D_GROUP(gpio_6), + RTD1319D_GROUP(gpio_7), + RTD1319D_GROUP(gpio_8), + RTD1319D_GROUP(gpio_9), + RTD1319D_GROUP(gpio_10), + RTD1319D_GROUP(gpio_11), + RTD1319D_GROUP(gpio_12), + RTD1319D_GROUP(gpio_13), + RTD1319D_GROUP(gpio_14), + RTD1319D_GROUP(gpio_15), + RTD1319D_GROUP(gpio_16), + RTD1319D_GROUP(gpio_17), + RTD1319D_GROUP(gpio_18), + RTD1319D_GROUP(gpio_19), + RTD1319D_GROUP(gpio_20), + RTD1319D_GROUP(gpio_21), + RTD1319D_GROUP(gpio_22), + RTD1319D_GROUP(gpio_23), + RTD1319D_GROUP(usb_cc2), + RTD1319D_GROUP(gpio_25), + RTD1319D_GROUP(gpio_26), + RTD1319D_GROUP(gpio_27), + RTD1319D_GROUP(gpio_28), + RTD1319D_GROUP(gpio_29), + RTD1319D_GROUP(gpio_30), + RTD1319D_GROUP(gpio_31), + RTD1319D_GROUP(gpio_32), + RTD1319D_GROUP(gpio_33), + RTD1319D_GROUP(gpio_34), + RTD1319D_GROUP(gpio_35), + RTD1319D_GROUP(hif_data), + RTD1319D_GROUP(hif_en), + RTD1319D_GROUP(hif_rdy), + RTD1319D_GROUP(hif_clk), + RTD1319D_GROUP(gpio_40), + RTD1319D_GROUP(gpio_41), + RTD1319D_GROUP(gpio_42), + RTD1319D_GROUP(gpio_43), + RTD1319D_GROUP(gpio_44), + RTD1319D_GROUP(gpio_45), + RTD1319D_GROUP(gpio_46), + RTD1319D_GROUP(gpio_47), + RTD1319D_GROUP(gpio_48), + RTD1319D_GROUP(gpio_49), + RTD1319D_GROUP(gpio_50), + RTD1319D_GROUP(usb_cc1), + RTD1319D_GROUP(gpio_52), + RTD1319D_GROUP(gpio_53), + RTD1319D_GROUP(ir_rx), + RTD1319D_GROUP(ur0_rx), + RTD1319D_GROUP(ur0_tx), + RTD1319D_GROUP(gpio_57), + RTD1319D_GROUP(gpio_58), + RTD1319D_GROUP(gpio_59), + RTD1319D_GROUP(gpio_60), + RTD1319D_GROUP(gpio_61), + RTD1319D_GROUP(gpio_62), + RTD1319D_GROUP(gpio_63), + RTD1319D_GROUP(gpio_64), + RTD1319D_GROUP(emmc_rst_n), + RTD1319D_GROUP(emmc_dd_sb), + RTD1319D_GROUP(emmc_clk), + RTD1319D_GROUP(emmc_cmd), + RTD1319D_GROUP(emmc_data_0), + RTD1319D_GROUP(emmc_data_1), + RTD1319D_GROUP(emmc_data_2), + RTD1319D_GROUP(emmc_data_3), + RTD1319D_GROUP(emmc_data_4), + RTD1319D_GROUP(emmc_data_5), + RTD1319D_GROUP(emmc_data_6), + RTD1319D_GROUP(emmc_data_7), + RTD1319D_GROUP(gpio_78), + RTD1319D_GROUP(gpio_79), + RTD1319D_GROUP(gpio_80), + RTD1319D_GROUP(gpio_81), + RTD1319D_GROUP(ur2_loc), + RTD1319D_GROUP(gspi_loc), + RTD1319D_GROUP(hi_width), + RTD1319D_GROUP(sf_en), + RTD1319D_GROUP(arm_trace_dbg_en), + RTD1319D_GROUP(ejtag_aucpu_loc), + RTD1319D_GROUP(ejtag_acpu_loc), + RTD1319D_GROUP(ejtag_vcpu_loc), + RTD1319D_GROUP(ejtag_scpu_loc), + RTD1319D_GROUP(dmic_loc), + RTD1319D_GROUP(ejtag_secpu_loc), + RTD1319D_GROUP(vtc_dmic_loc), + RTD1319D_GROUP(vtc_tdm_loc), + RTD1319D_GROUP(vtc_i2si_loc), + RTD1319D_GROUP(tdm_ai_loc), + RTD1319D_GROUP(ai_loc), + RTD1319D_GROUP(spdif_loc), + RTD1319D_GROUP(hif_en_loc), + RTD1319D_GROUP(sc0_loc), + RTD1319D_GROUP(sc1_loc), +}; + +static const char * const rtd1319d_gpio_groups[] = { + "gpio_0", "gpio_1", "gpio_2", "gpio_3", "gpio_4", + "gpio_5", "gpio_6", "gpio_7", "gpio_8", "gpio_9", + "gpio_10", "gpio_11", "gpio_12", "gpio_13", "gpio_14", + "gpio_15", "gpio_16", "gpio_17", "gpio_18", "gpio_19", + "gpio_20", "gpio_21", "gpio_22", "gpio_23", "usb_cc2", + "gpio_25", "gpio_26", "gpio_27", "gpio_28", "gpio_29", + "gpio_30", "gpio_31", "gpio_32", "gpio_33", "gpio_34", + "gpio_35", "hif_data", "hif_en", "hif_rdy", "hif_clk", + "gpio_40", "gpio_41", "gpio_42", "gpio_43", "gpio_44", + "gpio_45", "gpio_46", "gpio_47", "gpio_48", "gpio_49", + "gpio_50", "usb_cc1", "gpio_52", "gpio_53", "ir_rx", + "ur0_rx", "ur0_tx", "gpio_57", "gpio_58", "gpio_59", + "gpio_60", "gpio_61", "gpio_62", "gpio_63", "gpio_64", + "emmc_rst_n", "emmc_dd_sb", "emmc_clk", "emmc_cmd", + "emmc_data_0", "emmc_data_1", "emmc_data_2", "emmc_data_3", + "emmc_data_4", "emmc_data_5", "emmc_data_6", "emmc_data_7", + "gpio_78", "gpio_79", "gpio_80", "gpio_81" }; +static const char * const rtd1319d_nf_groups[] = { + "emmc_rst_n", "emmc_clk", "emmc_cmd", "emmc_data_0", + "emmc_data_1", "emmc_data_2", "emmc_data_3", "emmc_data_4", + "emmc_data_5", "emmc_data_6", "emmc_data_7", + "gpio_78", "gpio_79", "gpio_80", "gpio_81" }; +static const char * const rtd1319d_emmc_groups[] = { + "emmc_rst_n", "emmc_dd_sb", "emmc_clk", "emmc_cmd", + "emmc_data_0", "emmc_data_1", "emmc_data_2", "emmc_data_3", + "emmc_data_4", "emmc_data_5", "emmc_data_6", "emmc_data_7" }; +static const char * const rtd1319d_tp0_groups[] = { + "gpio_2", "gpio_3", "gpio_4", "gpio_57", "gpio_58", + "gpio_59", "gpio_60", "gpio_61", "gpio_62", "gpio_63", + "gpio_64" }; +static const char * const rtd1319d_tp1_groups[] = { + "gpio_61", "gpio_62", "gpio_63", "gpio_64" }; +static const char * const rtd1319d_sc0_groups[] = { + "gpio_18", "gpio_19", "gpio_31" }; +static const char * const rtd1319d_sc0_data0_groups[] = { "gpio_20", "sc0_loc" }; +static const char * const rtd1319d_sc0_data1_groups[] = { "gpio_30", "sc0_loc" }; +static const char * const rtd1319d_sc0_data2_groups[] = { "gpio_47", "sc0_loc" }; +static const char * const rtd1319d_sc1_groups[] = { + "gpio_2", "gpio_3", "gpio_5" }; +static const char * const rtd1319d_sc1_data0_groups[] = { "gpio_52", "sc1_loc" }; +static const char * const rtd1319d_sc1_data1_groups[] = { "gpio_34", "sc1_loc" }; +static const char * const rtd1319d_sc1_data2_groups[] = { "gpio_35", "sc1_loc" }; +static const char * const rtd1319d_ao_groups[] = { + "gpio_2", "gpio_3", "gpio_4", "gpio_61", "gpio_62", + "gpio_63", "gpio_64" }; +static const char * const rtd1319d_gspi_loc0_groups[] = { + "gpio_18", "gpio_19", "gpio_20", "gpio_31", "gspi_loc" }; +static const char * const rtd1319d_gspi_loc1_groups[] = { + "gpio_8", "gpio_9", "gpio_10", "gpio_11", "gspi_loc" }; +static const char * const rtd1319d_uart0_groups[] = { "ur0_rx", "ur0_tx"}; +static const char * const rtd1319d_uart1_groups[] = { + "gpio_8", "gpio_9", "gpio_10", "gpio_11" }; +static const char * const rtd1319d_uart2_loc0_groups[] = { + "gpio_18", "gpio_19", "gpio_20", "gpio_31", "ur2_loc" }; +static const char * const rtd1319d_uart2_loc1_groups[] = { + "gpio_25", "gpio_26", "gpio_27", "gpio_28", "ur2_loc" }; +static const char * const rtd1319d_i2c0_groups[] = { "gpio_12", "gpio_13" }; +static const char * const rtd1319d_i2c1_groups[] = { "gpio_16", "gpio_17" }; +static const char * const rtd1319d_i2c3_groups[] = { "gpio_26", "gpio_27" }; +static const char * const rtd1319d_i2c4_groups[] = { "gpio_34", "gpio_35" }; +static const char * const rtd1319d_i2c5_groups[] = { "gpio_29", "gpio_46" }; +static const char * const rtd1319d_pcie1_groups[] = { "gpio_22" }; +static const char * const rtd1319d_sdio_groups[] = { + "gpio_40", "gpio_41", "gpio_42", "gpio_43", "gpio_44", + "gpio_45" }; +static const char * const rtd1319d_etn_led_groups[] = { "gpio_14", "gpio_15" }; +static const char * const rtd1319d_etn_phy_groups[] = { "gpio_14", "gpio_15" }; +static const char * const rtd1319d_spi_groups[] = { + "gpio_18", "gpio_19", "gpio_20", "gpio_31" }; +static const char * const rtd1319d_pwm0_loc0_groups[] = { "gpio_26" }; +static const char * const rtd1319d_pwm0_loc1_groups[] = { "gpio_20" }; +static const char * const rtd1319d_pwm1_loc0_groups[] = { "gpio_27" }; +static const char * const rtd1319d_pwm1_loc1_groups[] = { "gpio_21" }; + +static const char * const rtd1319d_pwm2_loc0_groups[] = { "gpio_28" }; +static const char * const rtd1319d_pwm2_loc1_groups[] = { "gpio_22" }; +static const char * const rtd1319d_pwm3_loc0_groups[] = { "gpio_47" }; +static const char * const rtd1319d_pwm3_loc1_groups[] = { "gpio_23" }; +static const char * const rtd1319d_qam_agc_if0_groups[] = { "gpio_21" }; +static const char * const rtd1319d_qam_agc_if1_groups[] = { "gpio_23" }; +static const char * const rtd1319d_spdif_optical_loc0_groups[] = { "gpio_21", "spdif_loc" }; +static const char * const rtd1319d_spdif_optical_loc1_groups[] = { "gpio_6", "spdif_loc" }; +static const char * const rtd1319d_usb_cc1_groups[] = { "usb_cc1" }; +static const char * const rtd1319d_usb_cc2_groups[] = { "usb_cc2" }; +static const char * const rtd1319d_vfd_groups[] = { + "gpio_26", "gpio_27", "gpio_28" }; +static const char * const rtd1319d_sd_groups[] = { + "gpio_32", "gpio_33", "gpio_34", "gpio_35", + "hif_data", "hif_en", "hif_rdy", "hif_clk" }; +static const char * const rtd1319d_dmic_loc0_groups[] = { + "gpio_57", "gpio_58", "gpio_59", "gpio_60", "gpio_61", + "gpio_62", "gpio_63", "gpio_64", "dmic_loc" }; +static const char * const rtd1319d_dmic_loc1_groups[] = { + "gpio_32", "gpio_33", "gpio_34", "gpio_35", + "hif_data", "hif_en", "hif_rdy", "hif_clk", + "dmic_loc" }; +static const char * const rtd1319d_ai_loc0_groups[] = { + "gpio_57", "gpio_58", "gpio_59", "gpio_60", "gpio_61", + "gpio_62", "gpio_63", "ai_loc" }; +static const char * const rtd1319d_ai_loc1_groups[] = { + "gpio_32", "gpio_33", "gpio_34", "hif_data", + "hif_en", "hif_rdy", "hif_clk", "ai_loc" }; +static const char * const rtd1319d_tdm_ai_loc0_groups[] = { + "gpio_57", "gpio_58", "gpio_59", + "gpio_60", "tdm_ai_loc" }; +static const char * const rtd1319d_tdm_ai_loc1_groups[] = { + "hif_data", "hif_en", "hif_rdy", "hif_clk", "tdm_ai_loc" }; +static const char * const rtd1319d_hi_loc0_groups[] = { + "hif_data", "hif_en", "hif_rdy", "hif_clk" }; +static const char * const rtd1319d_hi_m_groups[] = { + "hif_data", "hif_en", "hif_rdy", "hif_clk" }; +static const char * const rtd1319d_vtc_i2so_groups[] = { + "gpio_2", "gpio_3", "gpio_4", "gpio_64"}; +static const char * const rtd1319d_vtc_i2si_loc0_groups[] = { + "gpio_57", "gpio_58", "gpio_59", "gpio_60", "gpio_61", + "vtc_i2si_loc" }; +static const char * const rtd1319d_vtc_i2si_loc1_groups[] = { + "gpio_32", "hif_data", "hif_en", "hif_rdy", "hif_clk", + "vtc_i2si_loc" }; +static const char * const rtd1319d_vtc_dmic_loc0_groups[] = { + "gpio_57", "gpio_58", "gpio_59", "gpio_60", + "vtc_dmic_loc" }; +static const char * const rtd1319d_vtc_dmic_loc1_groups[] = { + "hif_data", "hif_en", "hif_rdy", "hif_clk", + "vtc_dmic_loc" }; +static const char * const rtd1319d_vtc_tdm_loc0_groups[] = { + "gpio_57", "gpio_58", "gpio_59", "gpio_60", + "vtc_tdm_loc" }; +static const char * const rtd1319d_vtc_tdm_loc1_groups[] = { + "hif_data", "hif_en", "hif_rdy", "hif_clk", + "vtc_tdm_loc" }; +static const char * const rtd1319d_dc_fan_groups[] = { "gpio_47" }; +static const char * const rtd1319d_pll_test_loc0_groups[] = { "gpio_52", "gpio_53" }; +static const char * const rtd1319d_pll_test_loc1_groups[] = { "gpio_48", "gpio_49" }; +static const char * const rtd1319d_spdif_groups[] = { "gpio_50" }; +static const char * const rtd1319d_ir_rx_groups[] = { "ir_rx" }; +static const char * const rtd1319d_uart2_disable_groups[] = { "ur2_loc" }; +static const char * const rtd1319d_gspi_disable_groups[] = { "gspi_loc" }; +static const char * const rtd1319d_hi_width_disable_groups[] = { "hi_width" }; +static const char * const rtd1319d_hi_width_1bit_groups[] = { "hi_width" }; +static const char * const rtd1319d_sf_disable_groups[] = { "sf_en" }; +static const char * const rtd1319d_sf_enable_groups[] = { "sf_en" }; +static const char * const rtd1319d_scpu_ejtag_loc0_groups[] = { + "gpio_2", "gpio_3", "gpio_4", "gpio_5", "gpio_6", + "ejtag_scpu_loc" }; +static const char * const rtd1319d_scpu_ejtag_loc1_groups[] = { + "gpio_32", "gpio_33", "hif_data", "hif_en", "hif_clk", + "ejtag_scpu_loc" }; +static const char * const rtd1319d_scpu_ejtag_loc2_groups[] = { + "gpio_57", "gpio_58", "gpio_59", "gpio_60", "gpio_61", + "ejtag_scpu_loc" }; +static const char * const rtd1319d_acpu_ejtag_loc0_groups[] = { + "gpio_2", "gpio_3", "gpio_4", "gpio_5", "gpio_6", + "ejtag_acpu_loc" }; +static const char * const rtd1319d_acpu_ejtag_loc1_groups[] = { + "gpio_32", "gpio_33", "hif_data", "hif_en", "hif_clk", + "ejtag_acpu_loc" }; +static const char * const rtd1319d_acpu_ejtag_loc2_groups[] = { + "gpio_57", "gpio_58", "gpio_59", "gpio_60", "gpio_61", + "ejtag_acpu_loc" }; +static const char * const rtd1319d_vcpu_ejtag_loc0_groups[] = { + "gpio_2", "gpio_3", "gpio_4", "gpio_5", "gpio_6", + "ejtag_vcpu_loc" }; +static const char * const rtd1319d_vcpu_ejtag_loc1_groups[] = { + "gpio_32", "gpio_33", "hif_data", "hif_en", "hif_clk", + "ejtag_vcpu_loc" }; +static const char * const rtd1319d_vcpu_ejtag_loc2_groups[] = { + "gpio_57", "gpio_58", "gpio_59", "gpio_60", "gpio_61", + "ejtag_vcpu_loc" }; +static const char * const rtd1319d_secpu_ejtag_loc0_groups[] = { + "gpio_2", "gpio_3", "gpio_4", "gpio_5", "gpio_6", + "ejtag_secpu_loc" }; +static const char * const rtd1319d_secpu_ejtag_loc1_groups[] = { + "gpio_32", "gpio_33", "hif_data", "hif_en", "hif_clk", + "ejtag_secpu_loc" }; +static const char * const rtd1319d_secpu_ejtag_loc2_groups[] = { + "gpio_57", "gpio_58", "gpio_59", "gpio_60", "gpio_61", + "ejtag_secpu_loc" }; +static const char * const rtd1319d_aucpu_ejtag_loc0_groups[] = { + "gpio_2", "gpio_3", "gpio_4", "gpio_5", "gpio_6", + "ejtag_aucpu_loc" }; +static const char * const rtd1319d_aucpu_ejtag_loc1_groups[] = { + "gpio_32", "gpio_33", "hif_data", "hif_en", "hif_clk", + "ejtag_aucpu_loc" }; +static const char * const rtd1319d_aucpu_ejtag_loc2_groups[] = { + "gpio_57", "gpio_58", "gpio_59", "gpio_60", "gpio_61", + "ejtag_aucpu_loc" }; +static const char * const rtd1319d_iso_tristate_groups[] = { + "emmc_rst_n", "emmc_dd_sb", "emmc_clk", "emmc_cmd", + "emmc_data_0", "emmc_data_1", "emmc_data_2", "emmc_data_3", + "emmc_data_4", "emmc_data_5", "emmc_data_6", "emmc_data_7", + "gpio_78", "gpio_79", "gpio_80", "gpio_81", "gpio_1", + "gpio_8", "gpio_9", "gpio_10", "gpio_11", "gpio_22", + "gpio_23", "usb_cc2", "gpio_25", "gpio_28", "gpio_29", + "gpio_30", "gpio_32", "gpio_33", "hif_data", "hif_en", + "hif_rdy", "hif_clk", "gpio_40", "gpio_41", "gpio_42", + "gpio_43", "gpio_44", "gpio_45", "gpio_46", "usb_cc1", + "ir_rx", "ur0_rx", "ur0_tx", "gpio_62", "gpio_63", "gpio_64" }; +static const char * const rtd1319d_dbg_out0_groups[] = { + "gpio_12", "gpio_13", "gpio_16", "gpio_17", "gpio_26", "gpio_27", + "gpio_34", "gpio_35", "gpio_48", "gpio_49", "gpio_57", "gpio_58", + "gpio_59", "gpio_60", "gpio_61" }; +static const char * const rtd1319d_dbg_out1_groups[] = { + "gpio_0", "gpio_2", "gpio_3", "gpio_4", "gpio_5", "gpio_6", + "gpio_7", "gpio_14", "gpio_15", "gpio_18", "gpio_19", "gpio_20", + "gpio_21", "gpio_31", "gpio_47", "gpio_50", "gpio_52", "gpio_53" }; +static const char * const rtd1319d_standby_dbg_groups[] = { + "gpio_2", "gpio_3", "ir_rx" }; +static const char * const rtd1319d_arm_trace_debug_disable_groups[] = { "arm_trace_dbg_en" }; +static const char * const rtd1319d_arm_trace_debug_enable_groups[] = { "arm_trace_dbg_en" }; +static const char * const rtd1319d_aucpu_ejtag_disable_groups[] = { "ejtag_aucpu_loc" }; +static const char * const rtd1319d_acpu_ejtag_disable_groups[] = { "ejtag_acpu_loc" }; +static const char * const rtd1319d_vcpu_ejtag_disable_groups[] = { "ejtag_vcpu_loc" }; +static const char * const rtd1319d_scpu_ejtag_disable_groups[] = { "ejtag_scpu_loc" }; +static const char * const rtd1319d_secpu_ejtag_disable_groups[] = { "ejtag_secpu_loc" }; +static const char * const rtd1319d_vtc_dmic_loc_disable_groups[] = { "vtc_dmic_loc" }; +static const char * const rtd1319d_vtc_tdm_disable_groups[] = { "vtc_tdm_loc" }; +static const char * const rtd1319d_vtc_i2si_disable_groups[] = { "vtc_i2si_loc" }; +static const char * const rtd1319d_tdm_ai_disable_groups[] = { "tdm_ai_loc" }; +static const char * const rtd1319d_ai_disable_groups[] = { "ai_loc" }; +static const char * const rtd1319d_spdif_disable_groups[] = { "spdif_loc" }; +static const char * const rtd1319d_hif_disable_groups[] = { "hif_en_loc" }; +static const char * const rtd1319d_hif_enable_groups[] = { "hif_en_loc" }; +static const char * const rtd1319d_test_loop_groups[] = { "gpio_27" }; +static const char * const rtd1319d_pmic_pwrup_groups[] = { "gpio_78" }; + +#define RTD1319D_FUNC(_name) \ + { \ + .name = # _name, \ + .groups = rtd1319d_ ## _name ## _groups, \ + .num_groups = ARRAY_SIZE(rtd1319d_ ## _name ## _groups), \ + } + +static const struct rtd_pin_func_desc rtd1319d_pin_functions[] = { + RTD1319D_FUNC(gpio), + RTD1319D_FUNC(nf), + RTD1319D_FUNC(emmc), + RTD1319D_FUNC(tp0), + RTD1319D_FUNC(tp1), + RTD1319D_FUNC(sc0), + RTD1319D_FUNC(sc0_data0), + RTD1319D_FUNC(sc0_data1), + RTD1319D_FUNC(sc0_data2), + RTD1319D_FUNC(sc1), + RTD1319D_FUNC(sc1_data0), + RTD1319D_FUNC(sc1_data1), + RTD1319D_FUNC(sc1_data2), + RTD1319D_FUNC(ao), + RTD1319D_FUNC(gspi_loc0), + RTD1319D_FUNC(gspi_loc1), + RTD1319D_FUNC(uart0), + RTD1319D_FUNC(uart1), + RTD1319D_FUNC(uart2_loc0), + RTD1319D_FUNC(uart2_loc1), + RTD1319D_FUNC(i2c0), + RTD1319D_FUNC(i2c1), + RTD1319D_FUNC(i2c3), + RTD1319D_FUNC(i2c4), + RTD1319D_FUNC(i2c5), + RTD1319D_FUNC(pcie1), + RTD1319D_FUNC(sdio), + RTD1319D_FUNC(etn_led), + RTD1319D_FUNC(etn_phy), + RTD1319D_FUNC(spi), + RTD1319D_FUNC(pwm0_loc0), + RTD1319D_FUNC(pwm0_loc1), + RTD1319D_FUNC(pwm1_loc0), + RTD1319D_FUNC(pwm1_loc1), + RTD1319D_FUNC(pwm2_loc0), + RTD1319D_FUNC(pwm2_loc1), + RTD1319D_FUNC(pwm3_loc0), + RTD1319D_FUNC(pwm3_loc1), + RTD1319D_FUNC(qam_agc_if0), + RTD1319D_FUNC(qam_agc_if1), + RTD1319D_FUNC(spdif_optical_loc0), + RTD1319D_FUNC(spdif_optical_loc1), + RTD1319D_FUNC(usb_cc1), + RTD1319D_FUNC(usb_cc2), + RTD1319D_FUNC(vfd), + RTD1319D_FUNC(sd), + RTD1319D_FUNC(dmic_loc0), + RTD1319D_FUNC(dmic_loc1), + RTD1319D_FUNC(ai_loc0), + RTD1319D_FUNC(ai_loc1), + RTD1319D_FUNC(tdm_ai_loc0), + RTD1319D_FUNC(tdm_ai_loc1), + RTD1319D_FUNC(hi_loc0), + RTD1319D_FUNC(hi_m), + RTD1319D_FUNC(vtc_i2so), + RTD1319D_FUNC(vtc_i2si_loc0), + RTD1319D_FUNC(vtc_i2si_loc1), + RTD1319D_FUNC(vtc_dmic_loc0), + RTD1319D_FUNC(vtc_dmic_loc1), + RTD1319D_FUNC(vtc_tdm_loc0), + RTD1319D_FUNC(vtc_tdm_loc1), + RTD1319D_FUNC(dc_fan), + RTD1319D_FUNC(pll_test_loc0), + RTD1319D_FUNC(pll_test_loc1), + RTD1319D_FUNC(ir_rx), + RTD1319D_FUNC(uart2_disable), + RTD1319D_FUNC(gspi_disable), + RTD1319D_FUNC(hi_width_disable), + RTD1319D_FUNC(hi_width_1bit), + RTD1319D_FUNC(sf_disable), + RTD1319D_FUNC(sf_enable), + RTD1319D_FUNC(scpu_ejtag_loc0), + RTD1319D_FUNC(scpu_ejtag_loc1), + RTD1319D_FUNC(scpu_ejtag_loc2), + RTD1319D_FUNC(acpu_ejtag_loc0), + RTD1319D_FUNC(acpu_ejtag_loc1), + RTD1319D_FUNC(acpu_ejtag_loc2), + RTD1319D_FUNC(vcpu_ejtag_loc0), + RTD1319D_FUNC(vcpu_ejtag_loc1), + RTD1319D_FUNC(vcpu_ejtag_loc2), + RTD1319D_FUNC(secpu_ejtag_loc0), + RTD1319D_FUNC(secpu_ejtag_loc1), + RTD1319D_FUNC(secpu_ejtag_loc2), + RTD1319D_FUNC(aucpu_ejtag_loc0), + RTD1319D_FUNC(aucpu_ejtag_loc1), + RTD1319D_FUNC(aucpu_ejtag_loc2), + RTD1319D_FUNC(iso_tristate), + RTD1319D_FUNC(dbg_out0), + RTD1319D_FUNC(dbg_out1), + RTD1319D_FUNC(standby_dbg), + RTD1319D_FUNC(spdif), + RTD1319D_FUNC(arm_trace_debug_disable), + RTD1319D_FUNC(arm_trace_debug_enable), + RTD1319D_FUNC(aucpu_ejtag_disable), + RTD1319D_FUNC(acpu_ejtag_disable), + RTD1319D_FUNC(vcpu_ejtag_disable), + RTD1319D_FUNC(scpu_ejtag_disable), + RTD1319D_FUNC(secpu_ejtag_disable), + RTD1319D_FUNC(vtc_dmic_loc_disable), + RTD1319D_FUNC(vtc_tdm_disable), + RTD1319D_FUNC(vtc_i2si_disable), + RTD1319D_FUNC(tdm_ai_disable), + RTD1319D_FUNC(ai_disable), + RTD1319D_FUNC(spdif_disable), + RTD1319D_FUNC(hif_disable), + RTD1319D_FUNC(hif_enable), + RTD1319D_FUNC(test_loop), + RTD1319D_FUNC(pmic_pwrup), +}; + +#undef RTD1319D_FUNC + +static const struct rtd_pin_desc rtd1319d_iso_muxes[] = { + [RTD1319D_ISO_EMMC_RST_N] = RTK_PIN_MUX(emmc_rst_n, 0x0, GENMASK(3, 0), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "nf"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 0), "emmc"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 0), "iso_tristate")), + [RTD1319D_ISO_EMMC_DD_SB] = RTK_PIN_MUX(emmc_dd_sb, 0x0, GENMASK(7, 4), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 4), "emmc"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 4), "iso_tristate")), + [RTD1319D_ISO_EMMC_CLK] = RTK_PIN_MUX(emmc_clk, 0x0, GENMASK(11, 8), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 8), "nf"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 8), "emmc"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 8), "iso_tristate")), + [RTD1319D_ISO_EMMC_CMD] = RTK_PIN_MUX(emmc_cmd, 0x0, GENMASK(15, 12), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 12), "nf"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 12), "emmc"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 12), "iso_tristate")), + [RTD1319D_ISO_EMMC_DATA_0] = RTK_PIN_MUX(emmc_data_0, 0x0, GENMASK(19, 16), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 16), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 16), "nf"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 16), "emmc"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 16), "iso_tristate")), + [RTD1319D_ISO_EMMC_DATA_1] = RTK_PIN_MUX(emmc_data_1, 0x0, GENMASK(23, 20), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 20), "nf"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 20), "emmc"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 20), "iso_tristate")), + [RTD1319D_ISO_EMMC_DATA_2] = RTK_PIN_MUX(emmc_data_2, 0x0, GENMASK(27, 24), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 24), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 24), "nf"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 24), "emmc"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 24), "iso_tristate")), + [RTD1319D_ISO_EMMC_DATA_3] = RTK_PIN_MUX(emmc_data_3, 0x0, GENMASK(31, 28), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 28), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 28), "nf"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 28), "emmc"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 28), "iso_tristate")), + + [RTD1319D_ISO_EMMC_DATA_4] = RTK_PIN_MUX(emmc_data_4, 0x4, GENMASK(3, 0), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "nf"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 0), "emmc"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 0), "iso_tristate")), + [RTD1319D_ISO_EMMC_DATA_5] = RTK_PIN_MUX(emmc_data_5, 0x4, GENMASK(7, 4), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 4), "nf"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 4), "emmc"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 4), "iso_tristate")), + [RTD1319D_ISO_EMMC_DATA_6] = RTK_PIN_MUX(emmc_data_6, 0x4, GENMASK(11, 8), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 8), "nf"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 8), "emmc"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 8), "iso_tristate")), + [RTD1319D_ISO_EMMC_DATA_7] = RTK_PIN_MUX(emmc_data_7, 0x4, GENMASK(15, 12), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 12), "nf"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 12), "emmc"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 12), "iso_tristate")), + [RTD1319D_ISO_GPIO_78] = RTK_PIN_MUX(gpio_78, 0x4, GENMASK(19, 16), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 16), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 16), "nf"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 16), "pmic_pwrup"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 16), "iso_tristate")), + [RTD1319D_ISO_GPIO_79] = RTK_PIN_MUX(gpio_79, 0x4, GENMASK(23, 20), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 20), "nf"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 20), "iso_tristate")), + [RTD1319D_ISO_GPIO_80] = RTK_PIN_MUX(gpio_80, 0x4, GENMASK(27, 24), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 24), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 24), "nf"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 24), "iso_tristate")), + [RTD1319D_ISO_GPIO_81] = RTK_PIN_MUX(gpio_81, 0x4, GENMASK(31, 28), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 28), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 28), "nf"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 28), "iso_tristate")), + + [RTD1319D_ISO_GPIO_0] = RTK_PIN_MUX(gpio_0, 0x8, GENMASK(3, 0), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 0), "dbg_out1")), + [RTD1319D_ISO_GPIO_1] = RTK_PIN_MUX(gpio_1, 0x8, GENMASK(7, 4), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 4), "iso_tristate")), + [RTD1319D_ISO_GPIO_2] = RTK_PIN_MUX(gpio_2, 0x8, GENMASK(11, 8), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 8), "standby_dbg"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 8), "tp0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 8), "aucpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 8), "sc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 8), "scpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x6, 8), "acpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x7, 8), "vcpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x8, 8), "secpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xb, 8), "vtc_i2so"), + RTK_PIN_FUNC(SHIFT_LEFT(0xc, 8), "ao"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 8), "dbg_out1")), + [RTD1319D_ISO_GPIO_3] = RTK_PIN_MUX(gpio_3, 0x8, GENMASK(15, 12), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 12), "standby_dbg"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 12), "tp0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 12), "aucpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 12), "sc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 12), "scpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x6, 12), "acpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x7, 12), "vcpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x8, 12), "secpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xb, 12), "vtc_i2so"), + RTK_PIN_FUNC(SHIFT_LEFT(0xc, 12), "ao"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 12), "dbg_out1")), + [RTD1319D_ISO_GPIO_4] = RTK_PIN_MUX(gpio_4, 0x8, GENMASK(19, 16), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 16), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 16), "tp0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 16), "aucpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 16), "scpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x6, 16), "acpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x7, 16), "vcpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x8, 16), "secpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xb, 16), "vtc_i2so"), + RTK_PIN_FUNC(SHIFT_LEFT(0xc, 16), "ao"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 16), "dbg_out1")), + [RTD1319D_ISO_GPIO_5] = RTK_PIN_MUX(gpio_5, 0x8, GENMASK(23, 20), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 20), "aucpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 20), "sc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 20), "scpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x6, 20), "acpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x7, 20), "vcpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x8, 20), "secpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 20), "dbg_out1")), + [RTD1319D_ISO_GPIO_6] = RTK_PIN_MUX(gpio_6, 0x8, GENMASK(27, 24), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 24), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 24), "aucpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 24), "spdif_optical_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 24), "scpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x6, 24), "acpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x7, 24), "vcpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x8, 24), "secpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 24), "dbg_out1")), + [RTD1319D_ISO_GPIO_7] = RTK_PIN_MUX(gpio_7, 0x8, GENMASK(31, 28), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 28), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 28), "dbg_out1")), + + [RTD1319D_ISO_GPIO_8] = RTK_PIN_MUX(gpio_8, 0xc, GENMASK(3, 0), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "uart1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 0), "gspi_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 0), "iso_tristate")), + [RTD1319D_ISO_GPIO_9] = RTK_PIN_MUX(gpio_9, 0xc, GENMASK(7, 4), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 4), "uart1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 4), "gspi_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 4), "iso_tristate")), + [RTD1319D_ISO_GPIO_10] = RTK_PIN_MUX(gpio_10, 0xc, GENMASK(11, 8), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 8), "uart1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 8), "gspi_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 8), "iso_tristate")), + [RTD1319D_ISO_GPIO_11] = RTK_PIN_MUX(gpio_11, 0xc, GENMASK(15, 12), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 12), "uart1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 12), "gspi_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 12), "iso_tristate")), + [RTD1319D_ISO_GPIO_12] = RTK_PIN_MUX(gpio_12, 0xc, GENMASK(19, 16), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 16), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 16), "i2c0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 16), "dbg_out0")), + [RTD1319D_ISO_GPIO_13] = RTK_PIN_MUX(gpio_13, 0xc, GENMASK(23, 20), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 20), "i2c0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 20), "dbg_out0")), + [RTD1319D_ISO_GPIO_14] = RTK_PIN_MUX(gpio_14, 0xc, GENMASK(27, 24), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 24), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 24), "etn_led"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 24), "etn_phy"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 24), "dbg_out1")), + [RTD1319D_ISO_GPIO_15] = RTK_PIN_MUX(gpio_15, 0xc, GENMASK(31, 28), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 28), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 28), "etn_led"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 28), "etn_phy"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 28), "dbg_out1")), + + [RTD1319D_ISO_GPIO_16] = RTK_PIN_MUX(gpio_16, 0x10, GENMASK(3, 0), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "i2c1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 0), "dbg_out0")), + [RTD1319D_ISO_GPIO_17] = RTK_PIN_MUX(gpio_17, 0x10, GENMASK(7, 4), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 4), "i2c1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 4), "dbg_out0")), + [RTD1319D_ISO_GPIO_18] = RTK_PIN_MUX(gpio_18, 0x10, GENMASK(11, 8), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 8), "uart2_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 8), "sc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 8), "gspi_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 8), "spi"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 8), "dbg_out1")), + [RTD1319D_ISO_GPIO_19] = RTK_PIN_MUX(gpio_19, 0x10, GENMASK(15, 12), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 12), "uart2_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 12), "sc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 12), "gspi_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 12), "spi"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 12), "dbg_out1")), + [RTD1319D_ISO_GPIO_20] = RTK_PIN_MUX(gpio_20, 0x10, GENMASK(19, 16), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 16), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 16), "uart2_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 16), "pwm0_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 16), "gspi_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 16), "sc0_data0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 16), "spi"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 16), "dbg_out1")), + [RTD1319D_ISO_GPIO_21] = RTK_PIN_MUX(gpio_21, 0x10, GENMASK(23, 20), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 20), "pwm1_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 20), "qam_agc_if0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x6, 20), "spdif_optical_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 20), "dbg_out1")), + [RTD1319D_ISO_GPIO_22] = RTK_PIN_MUX(gpio_22, 0x10, GENMASK(27, 24), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 24), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 24), "pwm2_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 24), "pcie1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 24), "iso_tristate")), + [RTD1319D_ISO_GPIO_23] = RTK_PIN_MUX(gpio_23, 0x10, GENMASK(31, 28), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 28), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 28), "pwm3_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 28), "qam_agc_if1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 28), "iso_tristate")), + + [RTD1319D_ISO_USB_CC2] = RTK_PIN_MUX(usb_cc2, 0x14, GENMASK(3, 0), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "usb_cc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 0), "iso_tristate")), + [RTD1319D_ISO_GPIO_25] = RTK_PIN_MUX(gpio_25, 0x14, GENMASK(7, 4), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 4), "uart2_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 4), "iso_tristate")), + [RTD1319D_ISO_GPIO_26] = RTK_PIN_MUX(gpio_26, 0x14, GENMASK(11, 8), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 8), "uart2_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 8), "vfd"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 8), "pwm0_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 8), "i2c3"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 8), "dbg_out0")), + [RTD1319D_ISO_GPIO_27] = RTK_PIN_MUX(gpio_27, 0x14, GENMASK(15, 12), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 12), "uart2_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 12), "vfd"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 12), "pwm1_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 12), "i2c3"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 12), "test_loop"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 12), "dbg_out0")), + [RTD1319D_ISO_GPIO_28] = RTK_PIN_MUX(gpio_28, 0x14, GENMASK(19, 16), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 16), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 16), "uart2_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 16), "vfd"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 16), "pwm2_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 16), "iso_tristate")), + [RTD1319D_ISO_GPIO_29] = RTK_PIN_MUX(gpio_29, 0x14, GENMASK(23, 20), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 20), "i2c5"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 20), "iso_tristate")), + [RTD1319D_ISO_GPIO_30] = RTK_PIN_MUX(gpio_30, 0x14, GENMASK(27, 24), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 24), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 24), "sc0_data1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 24), "iso_tristate")), + [RTD1319D_ISO_GPIO_31] = RTK_PIN_MUX(gpio_31, 0x14, GENMASK(31, 28), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 28), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 28), "uart2_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 28), "sc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 28), "gspi_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 28), "spi"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 28), "dbg_out1")), + + [RTD1319D_ISO_GPIO_32] = RTK_PIN_MUX(gpio_32, 0x18, GENMASK(3, 0), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "sd"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 0), "aucpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 0), "dmic_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 0), "ai_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 0), "scpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x6, 0), "acpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x7, 0), "vcpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xb, 0), "vtc_i2si_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xe, 0), "secpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 0), "iso_tristate")), + [RTD1319D_ISO_GPIO_33] = RTK_PIN_MUX(gpio_33, 0x18, GENMASK(7, 4), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 4), "sd"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 4), "aucpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 4), "dmic_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 4), "ai_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 4), "scpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x6, 4), "acpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x7, 4), "vcpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xe, 4), "secpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 4), "iso_tristate")), + [RTD1319D_ISO_GPIO_34] = RTK_PIN_MUX(gpio_34, 0x18, GENMASK(11, 8), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 8), "sd"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 8), "dmic_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 8), "ai_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 8), "i2c4"), + RTK_PIN_FUNC(SHIFT_LEFT(0x6, 8), "sc1_data1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 8), "dbg_out0")), + [RTD1319D_ISO_GPIO_35] = RTK_PIN_MUX(gpio_35, 0x18, GENMASK(15, 12), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 12), "sd"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 12), "dmic_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 12), "i2c4"), + RTK_PIN_FUNC(SHIFT_LEFT(0x6, 12), "sc1_data2"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 12), "dbg_out0")), + [RTD1319D_ISO_HIF_DATA] = RTK_PIN_MUX(hif_data, 0x18, GENMASK(19, 16), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 16), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 16), "sd"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 16), "aucpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 16), "dmic_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 16), "tdm_ai_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 16), "scpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x6, 16), "acpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x7, 16), "vcpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x8, 16), "ai_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x9, 16), "hi_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xa, 16), "hi_m"), + RTK_PIN_FUNC(SHIFT_LEFT(0xb, 16), "vtc_i2si_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xc, 16), "vtc_tdm_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xd, 16), "vtc_dmic_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xe, 16), "secpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 16), "iso_tristate")), + [RTD1319D_ISO_HIF_EN] = RTK_PIN_MUX(hif_en, 0x18, GENMASK(23, 20), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 20), "sd"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 20), "aucpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 20), "dmic_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 20), "tdm_ai_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 20), "scpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x6, 20), "acpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x7, 20), "vcpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x8, 20), "ai_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x9, 20), "hi_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xa, 20), "hi_m"), + RTK_PIN_FUNC(SHIFT_LEFT(0xb, 20), "vtc_i2si_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xc, 20), "vtc_tdm_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xd, 20), "vtc_dmic_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xe, 20), "secpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 20), "iso_tristate")), + [RTD1319D_ISO_HIF_RDY] = RTK_PIN_MUX(hif_rdy, 0x18, GENMASK(27, 24), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 24), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 24), "sd"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 24), "dmic_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 24), "tdm_ai_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x8, 24), "ai_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x9, 24), "hi_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xa, 24), "hi_m"), + RTK_PIN_FUNC(SHIFT_LEFT(0xb, 24), "vtc_i2si_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xc, 24), "vtc_tdm_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xd, 24), "vtc_dmic_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 24), "iso_tristate")), + [RTD1319D_ISO_HIF_CLK] = RTK_PIN_MUX(hif_clk, 0x18, GENMASK(31, 28), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 28), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 28), "sd"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 28), "aucpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 28), "dmic_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 28), "tdm_ai_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 28), "scpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x6, 28), "acpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x7, 28), "vcpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x8, 28), "ai_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x9, 28), "hi_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xa, 28), "hi_m"), + RTK_PIN_FUNC(SHIFT_LEFT(0xb, 28), "vtc_i2si_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xc, 28), "vtc_tdm_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xd, 28), "vtc_dmic_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xe, 28), "secpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 28), "iso_tristate")), + + [RTD1319D_ISO_GPIO_40] = RTK_PIN_MUX(gpio_40, 0x1c, GENMASK(3, 0), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 0), "sdio"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 0), "iso_tristate")), + [RTD1319D_ISO_GPIO_41] = RTK_PIN_MUX(gpio_41, 0x1c, GENMASK(7, 4), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 4), "sdio"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 4), "iso_tristate")), + [RTD1319D_ISO_GPIO_42] = RTK_PIN_MUX(gpio_42, 0x1c, GENMASK(11, 8), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 8), "sdio"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 8), "iso_tristate")), + [RTD1319D_ISO_GPIO_43] = RTK_PIN_MUX(gpio_43, 0x1c, GENMASK(15, 12), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 12), "sdio"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 12), "iso_tristate")), + [RTD1319D_ISO_GPIO_44] = RTK_PIN_MUX(gpio_44, 0x1c, GENMASK(19, 16), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 16), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 16), "sdio"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 16), "iso_tristate")), + [RTD1319D_ISO_GPIO_45] = RTK_PIN_MUX(gpio_45, 0x1c, GENMASK(23, 20), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 20), "sdio"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 20), "iso_tristate")), + [RTD1319D_ISO_GPIO_46] = RTK_PIN_MUX(gpio_46, 0x1c, GENMASK(27, 24), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 24), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 24), "i2c5"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 24), "iso_tristate")), + [RTD1319D_ISO_GPIO_47] = RTK_PIN_MUX(gpio_47, 0x1c, GENMASK(31, 28), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 28), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 28), "dc_fan"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 28), "pwm3_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 28), "sc0_data2"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 28), "dbg_out1")), + + [RTD1319D_ISO_GPIO_48] = RTK_PIN_MUX(gpio_48, 0x20, GENMASK(3, 0), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "pll_test_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 0), "dbg_out0")), + [RTD1319D_ISO_GPIO_49] = RTK_PIN_MUX(gpio_49, 0x20, GENMASK(7, 4), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 4), "pll_test_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 4), "dbg_out0")), + [RTD1319D_ISO_GPIO_50] = RTK_PIN_MUX(gpio_50, 0x20, GENMASK(11, 8), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 8), "spdif"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 8), "dbg_out1")), + [RTD1319D_ISO_USB_CC1] = RTK_PIN_MUX(usb_cc1, 0x20, GENMASK(15, 12), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 12), "usb_cc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 12), "iso_tristate")), + [RTD1319D_ISO_GPIO_52] = RTK_PIN_MUX(gpio_52, 0x20, GENMASK(19, 16), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 16), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 16), "pll_test_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 16), "sc1_data0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 16), "dbg_out1")), + [RTD1319D_ISO_GPIO_53] = RTK_PIN_MUX(gpio_53, 0x20, GENMASK(23, 20), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 20), "pll_test_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 20), "dbg_out1")), + [RTD1319D_ISO_IR_RX] = RTK_PIN_MUX(ir_rx, 0x20, GENMASK(27, 24), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 24), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 24), "ir_rx"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 24), "standby_dbg"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 24), "iso_tristate")), + [RTD1319D_ISO_UR0_RX] = RTK_PIN_MUX(ur0_rx, 0x20, GENMASK(31, 28), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 28), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 28), "uart0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 28), "iso_tristate")), + + [RTD1319D_ISO_UR0_TX] = RTK_PIN_MUX(ur0_tx, 0x24, GENMASK(3, 0), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "uart0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 0), "iso_tristate")), + [RTD1319D_ISO_GPIO_57] = RTK_PIN_MUX(gpio_57, 0x24, GENMASK(7, 4), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 4), "tdm_ai_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 4), "ai_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 4), "dmic_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 4), "tp0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x6, 4), "acpu_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0x7, 4), "vcpu_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0x8, 4), "secpu_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0x9, 4), "aucpu_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0xb, 4), "vtc_i2si_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xc, 4), "vtc_tdm_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xd, 4), "vtc_dmic_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xe, 4), "scpu_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 4), "dbg_out0")), + [RTD1319D_ISO_GPIO_58] = RTK_PIN_MUX(gpio_58, 0x24, GENMASK(11, 8), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 8), "tdm_ai_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 8), "ai_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 8), "dmic_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 8), "tp0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x6, 8), "acpu_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0x7, 8), "vcpu_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0x8, 8), "secpu_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0x9, 8), "aucpu_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0xb, 8), "vtc_i2si_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xc, 8), "vtc_tdm_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xd, 8), "vtc_dmic_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xe, 8), "scpu_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 8), "dbg_out0")), + [RTD1319D_ISO_GPIO_59] = RTK_PIN_MUX(gpio_59, 0x24, GENMASK(15, 12), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 12), "tdm_ai_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 12), "ai_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 12), "dmic_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 12), "tp0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x6, 12), "acpu_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0x7, 12), "vcpu_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0x8, 12), "secpu_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0x9, 12), "aucpu_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0xb, 12), "vtc_i2si_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xc, 12), "vtc_tdm_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xd, 12), "vtc_dmic_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xe, 12), "scpu_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 12), "dbg_out0")), + [RTD1319D_ISO_GPIO_60] = RTK_PIN_MUX(gpio_60, 0x24, GENMASK(19, 16), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 16), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 16), "tdm_ai_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 16), "ai_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 16), "dmic_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 16), "tp0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x6, 16), "acpu_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0x7, 16), "vcpu_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0x8, 16), "secpu_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0x9, 16), "aucpu_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0xb, 16), "vtc_i2si_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xc, 16), "vtc_tdm_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xd, 16), "vtc_dmic_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xe, 16), "scpu_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 16), "dbg_out0")), + [RTD1319D_ISO_GPIO_61] = RTK_PIN_MUX(gpio_61, 0x24, GENMASK(23, 20), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 20), "ai_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 20), "ao"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 20), "dmic_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 20), "tp0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 20), "tp1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x6, 20), "acpu_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0x7, 20), "vcpu_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0x8, 20), "secpu_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0x9, 20), "aucpu_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0xb, 20), "vtc_i2si_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xe, 20), "scpu_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 20), "dbg_out0")), + [RTD1319D_ISO_GPIO_62] = RTK_PIN_MUX(gpio_62, 0x24, GENMASK(27, 24), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 24), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 24), "ai_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 24), "ao"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 24), "dmic_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 24), "tp0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 24), "tp1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 24), "iso_tristate")), + [RTD1319D_ISO_GPIO_63] = RTK_PIN_MUX(gpio_63, 0x24, GENMASK(31, 28), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 28), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 28), "ai_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 28), "ao"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 28), "dmic_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 28), "tp0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 28), "tp1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 28), "iso_tristate")), + + [RTD1319D_ISO_GPIO_64] = RTK_PIN_MUX(gpio_64, 0x28, GENMASK(3, 0), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 0), "ao"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 0), "dmic_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 0), "tp0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 0), "tp1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xb, 0), "vtc_i2so"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 0), "iso_tristate")), + + [RTD1319D_ISO_UR2_LOC] = RTK_PIN_MUX(ur2_loc, 0x120, GENMASK(1, 0), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "uart2_disable"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "uart2_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 0), "uart2_loc1")), + [RTD1319D_ISO_GSPI_LOC] = RTK_PIN_MUX(gspi_loc, 0x120, GENMASK(3, 2), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 2), "gspi_disable"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 2), "gspi_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 2), "gspi_loc1")), + [RTD1319D_ISO_HI_WIDTH] = RTK_PIN_MUX(hi_width, 0x120, GENMASK(9, 8), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "hi_width_disable"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 8), "hi_width_1bit")), + [RTD1319D_ISO_SF_EN] = RTK_PIN_MUX(sf_en, 0x120, GENMASK(11, 11), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 11), "sf_disable"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 11), "sf_enable")), + [RTD1319D_ISO_ARM_TRACE_DBG_EN] = RTK_PIN_MUX(arm_trace_dbg_en, 0x120, GENMASK(12, 12), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "arm_trace_debug_disable"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 12), "arm_trace_debug_enable")), + [RTD1319D_ISO_EJTAG_AUCPU_LOC] = RTK_PIN_MUX(ejtag_aucpu_loc, 0x120, GENMASK(16, 14), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 14), "aucpu_ejtag_disable"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 14), "aucpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 14), "aucpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 14), "aucpu_ejtag_loc2")), + [RTD1319D_ISO_EJTAG_ACPU_LOC] = RTK_PIN_MUX(ejtag_acpu_loc, 0x120, GENMASK(19, 17), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 17), "acpu_ejtag_disable"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 17), "acpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 17), "acpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 17), "acpu_ejtag_loc2")), + [RTD1319D_ISO_EJTAG_VCPU_LOC] = RTK_PIN_MUX(ejtag_vcpu_loc, 0x120, GENMASK(22, 20), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "vcpu_ejtag_disable"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 20), "vcpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 20), "vcpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 20), "vcpu_ejtag_loc2")), + [RTD1319D_ISO_EJTAG_SCPU_LOC] = RTK_PIN_MUX(ejtag_scpu_loc, 0x120, GENMASK(25, 23), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 23), "scpu_ejtag_disable"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 23), "scpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 23), "scpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 23), "scpu_ejtag_loc2")), + [RTD1319D_ISO_DMIC_LOC] = RTK_PIN_MUX(dmic_loc, 0x120, GENMASK(27, 26), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 26), "dmic_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 26), "dmic_loc1")), + + [RTD1319D_ISO_EJTAG_SECPU_LOC] = RTK_PIN_MUX(ejtag_secpu_loc, 0x124, GENMASK(20, 18), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 18), "secpu_ejtag_disable"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 18), "secpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 18), "secpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 18), "secpu_ejtag_loc2")), + + [RTD1319D_ISO_VTC_DMIC_LOC] = RTK_PIN_MUX(vtc_dmic_loc, 0x128, GENMASK(1, 0), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "vtc_dmic_loc_disable"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "vtc_dmic_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 0), "vtc_dmic_loc1")), + [RTD1319D_ISO_VTC_TDM_LOC] = RTK_PIN_MUX(vtc_tdm_loc, 0x128, GENMASK(3, 2), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 2), "vtc_tdm_disable"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 2), "vtc_tdm_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 2), "vtc_tdm_loc1")), + [RTD1319D_ISO_VTC_I2SI_LOC] = RTK_PIN_MUX(vtc_i2si_loc, 0x128, GENMASK(5, 4), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "vtc_i2si_disable"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 4), "vtc_i2si_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 4), "vtc_i2si_loc1")), + [RTD1319D_ISO_TDM_AI_LOC] = RTK_PIN_MUX(tdm_ai_loc, 0x128, GENMASK(7, 6), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 6), "tdm_ai_disable"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 6), "tdm_ai_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 6), "tdm_ai_loc1")), + [RTD1319D_ISO_AI_LOC] = RTK_PIN_MUX(ai_loc, 0x128, GENMASK(9, 8), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "ai_disable"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 8), "ai_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 8), "ai_loc1")), + [RTD1319D_ISO_SPDIF_LOC] = RTK_PIN_MUX(spdif_loc, 0x128, GENMASK(11, 10), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 10), "spdif_disable"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 10), "spdif_optical_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 10), "spdif_optical_loc1")), + + [RTD1319D_ISO_HIF_EN_LOC] = RTK_PIN_MUX(hif_en_loc, 0x12c, GENMASK(2, 0), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 0), "hif_disable"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 0), "hif_enable")), + [RTD1319D_ISO_SC0_LOC] = RTK_PIN_MUX(sc0_loc, 0x188, GENMASK(9, 8), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "sc0_data0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 8), "sc0_data1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 8), "sc0_data2")), + [RTD1319D_ISO_SC1_LOC] = RTK_PIN_MUX(sc1_loc, 0x188, GENMASK(11, 10), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 10), "sc1_data0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 10), "sc1_data1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 10), "sc1_data2")), + + [RTD1319D_ISO_TESTMODE] = {0}, +}; + +static const struct rtd_pin_config_desc rtd1319d_iso_configs[] = { + [RTD1319D_ISO_SCAN_SWITCH] = RTK_PIN_CONFIG(scan_switch, 0x2c, 0, NA, NA, 0, 1, 2, PADDRI_4_8), + [RTD1319D_ISO_GPIO_18] = RTK_PIN_CONFIG(gpio_18, 0x2c, 3, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1319D_ISO_GPIO_19] = RTK_PIN_CONFIG(gpio_19, 0x2c, 8, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1319D_ISO_GPIO_20] = RTK_PIN_CONFIG(gpio_20, 0x2c, 13, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1319D_ISO_GPIO_31] = RTK_PIN_CONFIG(gpio_31, 0x2c, 18, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1319D_ISO_GPIO_8] = RTK_PIN_CONFIG(gpio_8, 0x2c, 23, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1319D_ISO_GPIO_9] = RTK_PIN_CONFIG(gpio_9, 0x30, 0, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1319D_ISO_GPIO_10] = RTK_PIN_CONFIG(gpio_10, 0x30, 5, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1319D_ISO_GPIO_11] = RTK_PIN_CONFIG(gpio_11, 0x30, 10, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1319D_ISO_GPIO_0] = RTK_PIN_CONFIG(gpio_0, 0x30, 15, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1319D_ISO_GPIO_1] = RTK_PIN_CONFIG(gpio_1, 0x30, 20, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1319D_ISO_GPIO_5] = RTK_PIN_CONFIG(gpio_5, 0x30, 25, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1319D_ISO_GPIO_6] = RTK_PIN_CONFIG(gpio_6, 0x34, 0, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1319D_ISO_GPIO_12] = RTK_PIN_CONFIG(gpio_12, 0x34, 5, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1319D_ISO_GPIO_13] = RTK_PIN_CONFIG(gpio_13, 0x34, 10, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1319D_ISO_GPIO_22] = RTK_PIN_CONFIG(gpio_22, 0x34, 15, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1319D_ISO_USB_CC2] = RTK_PIN_CONFIG(usb_cc2, 0x34, 20, NA, NA, 0, 1, 2, PADDRI_4_8), + [RTD1319D_ISO_GPIO_29] = RTK_PIN_CONFIG(gpio_29, 0x34, 23, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1319D_ISO_GPIO_46] = RTK_PIN_CONFIG(gpio_46, 0x38, 0, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1319D_ISO_GPIO_47] = RTK_PIN_CONFIG(gpio_47, 0x38, 5, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1319D_ISO_USB_CC1] = RTK_PIN_CONFIG(usb_cc1, 0x38, 10, NA, NA, 0, 1, 2, PADDRI_4_8), + [RTD1319D_ISO_WD_RSET] = RTK_PIN_CONFIG(wd_rset, 0x38, 13, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1319D_ISO_IR_RX] = RTK_PIN_CONFIG(ir_rx, 0x38, 18, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1319D_ISO_BOOT_SEL] = RTK_PIN_CONFIG(boot_sel, 0x38, 23, 0, 1, NA, 2, 3, PADDRI_4_8), + [RTD1319D_ISO_RESET_N] = RTK_PIN_CONFIG(reset_n, 0x38, 27, 0, 1, NA, 2, 3, PADDRI_4_8), + [RTD1319D_ISO_TESTMODE] = RTK_PIN_CONFIG(testmode, 0x3c, 0, 0, 1, NA, 2, 3, PADDRI_4_8), + [RTD1319D_ISO_GPIO_40] = RTK_PIN_CONFIG(gpio_40, 0x3c, 4, 0, 1, NA, 2, 12, NA), + [RTD1319D_ISO_GPIO_41] = RTK_PIN_CONFIG(gpio_41, 0x3c, 17, 0, 1, NA, 2, 12, NA), + [RTD1319D_ISO_GPIO_42] = RTK_PIN_CONFIG(gpio_42, 0x40, 0, 0, 1, NA, 2, 12, NA), + [RTD1319D_ISO_GPIO_43] = RTK_PIN_CONFIG(gpio_43, 0x40, 13, 0, 1, NA, 2, 12, NA), + [RTD1319D_ISO_GPIO_44] = RTK_PIN_CONFIG(gpio_44, 0x44, 0, 0, 1, NA, 2, 12, NA), + [RTD1319D_ISO_GPIO_45] = RTK_PIN_CONFIG(gpio_45, 0x44, 13, 0, 1, NA, 2, 12, NA), + [RTD1319D_ISO_EMMC_DATA_0] = RTK_PIN_CONFIG(emmc_data_0, 0x48, 0, 0, 1, NA, 2, 12, NA), + [RTD1319D_ISO_EMMC_DATA_1] = RTK_PIN_CONFIG(emmc_data_1, 0x48, 13, 0, 1, NA, 2, 12, NA), + [RTD1319D_ISO_EMMC_DATA_2] = RTK_PIN_CONFIG(emmc_data_2, 0x4c, 0, 0, 1, NA, 2, 12, NA), + [RTD1319D_ISO_EMMC_DATA_3] = RTK_PIN_CONFIG(emmc_data_3, 0x4c, 13, 0, 1, NA, 2, 12, NA), + [RTD1319D_ISO_EMMC_DATA_4] = RTK_PIN_CONFIG(emmc_data_4, 0x50, 0, 0, 1, NA, 2, 12, NA), + [RTD1319D_ISO_EMMC_DATA_5] = RTK_PIN_CONFIG(emmc_data_5, 0x50, 13, 0, 1, NA, 2, 12, NA), + [RTD1319D_ISO_EMMC_DATA_6] = RTK_PIN_CONFIG(emmc_data_6, 0x54, 0, 0, 1, NA, 2, 12, NA), + [RTD1319D_ISO_EMMC_DATA_7] = RTK_PIN_CONFIG(emmc_data_7, 0x54, 13, 0, 1, NA, 2, 12, NA), + [RTD1319D_ISO_EMMC_DD_SB] = RTK_PIN_CONFIG(emmc_dd_sb, 0x58, 0, 0, 1, NA, 2, 12, NA), + [RTD1319D_ISO_EMMC_RST_N] = RTK_PIN_CONFIG(emmc_rst_n, 0x58, 13, 0, 1, NA, 2, 12, NA), + [RTD1319D_ISO_EMMC_CMD] = RTK_PIN_CONFIG(emmc_cmd, 0x5c, 0, 0, 1, NA, 2, 13, NA), + [RTD1319D_ISO_EMMC_CLK] = RTK_PIN_CONFIG(emmc_clk, 0x5c, 14, 0, 1, NA, 2, 12, NA), + [RTD1319D_ISO_GPIO_80] = RTK_PIN_CONFIG(gpio_80, 0x60, 0, 0, 1, NA, 2, 12, NA), + [RTD1319D_ISO_GPIO_78] = RTK_PIN_CONFIG(gpio_78, 0x60, 13, 0, 1, NA, 2, 12, NA), + [RTD1319D_ISO_GPIO_79] = RTK_PIN_CONFIG(gpio_79, 0x64, 0, 0, 1, NA, 2, 12, NA), + [RTD1319D_ISO_GPIO_81] = RTK_PIN_CONFIG(gpio_81, 0x64, 13, 0, 1, NA, 2, 12, NA), + [RTD1319D_ISO_GPIO_2] = RTK_PIN_CONFIG(gpio_2, 0x64, 26, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1319D_ISO_GPIO_3] = RTK_PIN_CONFIG(gpio_3, 0x68, 0, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1319D_ISO_GPIO_4] = RTK_PIN_CONFIG(gpio_4, 0x68, 5, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1319D_ISO_GPIO_57] = RTK_PIN_CONFIG(gpio_57, 0x68, 10, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1319D_ISO_GPIO_58] = RTK_PIN_CONFIG(gpio_58, 0x68, 15, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1319D_ISO_GPIO_59] = RTK_PIN_CONFIG(gpio_59, 0x68, 20, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1319D_ISO_GPIO_60] = RTK_PIN_CONFIG(gpio_60, 0x68, 25, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1319D_ISO_GPIO_61] = RTK_PIN_CONFIG(gpio_61, 0x6c, 0, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1319D_ISO_GPIO_62] = RTK_PIN_CONFIG(gpio_62, 0x6c, 5, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1319D_ISO_GPIO_63] = RTK_PIN_CONFIG(gpio_63, 0x6c, 10, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1319D_ISO_GPIO_64] = RTK_PIN_CONFIG(gpio_64, 0x6c, 15, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1319D_ISO_GPIO_7] = RTK_PIN_CONFIG(gpio_7, 0x6c, 20, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1319D_ISO_GPIO_16] = RTK_PIN_CONFIG(gpio_16, 0x6c, 25, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1319D_ISO_GPIO_17] = RTK_PIN_CONFIG(gpio_17, 0x70, 0, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1319D_ISO_GPIO_21] = RTK_PIN_CONFIG(gpio_21, 0x70, 5, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1319D_ISO_GPIO_23] = RTK_PIN_CONFIG(gpio_23, 0x70, 10, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1319D_ISO_GPIO_50] = RTK_PIN_CONFIG(gpio_50, 0x70, 15, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1319D_ISO_HIF_EN] = RTK_PIN_CONFIG(hif_en, 0x74, 0, 0, 1, NA, 2, 12, NA), + [RTD1319D_ISO_HIF_DATA] = RTK_PIN_CONFIG(hif_data, 0x74, 13, 0, 1, NA, 2, 12, NA), + [RTD1319D_ISO_GPIO_33] = RTK_PIN_CONFIG(gpio_33, 0x78, 0, 0, 1, NA, 2, 12, NA), + [RTD1319D_ISO_GPIO_32] = RTK_PIN_CONFIG(gpio_32, 0x78, 13, 0, 1, NA, 2, 12, NA), + [RTD1319D_ISO_HIF_CLK] = RTK_PIN_CONFIG(hif_clk, 0x7c, 0, 0, 1, NA, 2, 12, NA), + [RTD1319D_ISO_HIF_RDY] = RTK_PIN_CONFIG(hif_rdy, 0x7c, 13, 0, 1, NA, 2, 12, NA), + [RTD1319D_ISO_GPIO_14] = RTK_PIN_CONFIG(gpio_14, 0x7c, 26, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1319D_ISO_GPIO_15] = RTK_PIN_CONFIG(gpio_15, 0x80, 0, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1319D_ISO_GPIO_25] = RTK_PIN_CONFIG(gpio_25, 0x80, 5, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1319D_ISO_GPIO_26] = RTK_PIN_CONFIG(gpio_26, 0x80, 10, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1319D_ISO_GPIO_27] = RTK_PIN_CONFIG(gpio_27, 0x80, 16, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1319D_ISO_GPIO_28] = RTK_PIN_CONFIG(gpio_28, 0x80, 22, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1319D_ISO_GPIO_30] = RTK_PIN_CONFIG(gpio_30, 0x84, 0, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1319D_ISO_GPIO_34] = RTK_PIN_CONFIG(gpio_34, 0x84, 5, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1319D_ISO_GPIO_35] = RTK_PIN_CONFIG(gpio_35, 0x84, 10, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1319D_ISO_UR0_TX] = RTK_PIN_CONFIG(ur0_tx, 0x84, 15, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1319D_ISO_UR0_RX] = RTK_PIN_CONFIG(ur0_rx, 0x84, 20, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1319D_ISO_GPIO_48] = RTK_PIN_CONFIG(gpio_48, 0x84, 25, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1319D_ISO_GPIO_49] = RTK_PIN_CONFIG(gpio_49, 0x88, 0, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1319D_ISO_GPIO_52] = RTK_PIN_CONFIG(gpio_52, 0x88, 5, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1319D_ISO_GPIO_53] = RTK_PIN_CONFIG(gpio_53, 0x88, 10, 1, 2, 0, 3, 4, PADDRI_4_8), +}; + +static const struct rtd_pin_sconfig_desc rtd1319d_iso_sconfigs[] = { + RTK_PIN_SCONFIG(gpio_40, 0x3c, 7, 3, 10, 3, 13, 3), + RTK_PIN_SCONFIG(gpio_41, 0x3c, 20, 3, 23, 3, 26, 3), + RTK_PIN_SCONFIG(gpio_42, 0x40, 3, 3, 6, 3, 9, 3), + RTK_PIN_SCONFIG(gpio_43, 0x40, 16, 3, 19, 3, 22, 3), + RTK_PIN_SCONFIG(gpio_44, 0x44, 3, 3, 6, 3, 9, 3), + RTK_PIN_SCONFIG(gpio_45, 0x44, 16, 3, 19, 3, 22, 3), + RTK_PIN_SCONFIG(emmc_data_0, 0x48, 3, 3, 6, 3, 9, 3), + RTK_PIN_SCONFIG(emmc_data_1, 0x48, 16, 3, 19, 3, 22, 3), + RTK_PIN_SCONFIG(emmc_data_2, 0x4c, 3, 3, 6, 3, 9, 3), + RTK_PIN_SCONFIG(emmc_data_3, 0x4c, 16, 3, 19, 3, 22, 3), + RTK_PIN_SCONFIG(emmc_data_4, 0x50, 3, 3, 6, 3, 9, 3), + RTK_PIN_SCONFIG(emmc_data_5, 0x50, 16, 3, 19, 3, 22, 3), + RTK_PIN_SCONFIG(emmc_data_6, 0x54, 3, 3, 6, 3, 9, 3), + RTK_PIN_SCONFIG(emmc_data_7, 0x54, 16, 3, 19, 3, 22, 3), + RTK_PIN_SCONFIG(emmc_dd_sb, 0x58, 3, 3, 6, 3, 9, 3), + RTK_PIN_SCONFIG(emmc_rst_n, 0x58, 16, 3, 19, 3, 22, 3), + RTK_PIN_SCONFIG(emmc_cmd, 0x5c, 3, 3, 6, 3, 9, 3), + RTK_PIN_SCONFIG(emmc_clk, 0x5c, 17, 3, 20, 3, 23, 3), + RTK_PIN_SCONFIG(gpio_80, 0x60, 3, 3, 6, 3, 9, 3), + RTK_PIN_SCONFIG(gpio_78, 0x60, 16, 3, 19, 3, 22, 3), + RTK_PIN_SCONFIG(gpio_79, 0x64, 3, 3, 6, 3, 9, 3), + RTK_PIN_SCONFIG(gpio_81, 0x64, 16, 3, 19, 3, 22, 3), + RTK_PIN_SCONFIG(hif_en, 0x74, 3, 3, 6, 3, 9, 3), + RTK_PIN_SCONFIG(hif_data, 0x74, 16, 3, 19, 3, 22, 3), + RTK_PIN_SCONFIG(gpio_33, 0x78, 3, 3, 6, 3, 9, 3), + RTK_PIN_SCONFIG(gpio_32, 0x78, 16, 3, 19, 3, 22, 3), + RTK_PIN_SCONFIG(hif_clk, 0x7c, 3, 3, 6, 3, 9, 3), + RTK_PIN_SCONFIG(hif_rdy, 0x7c, 16, 3, 19, 3, 22, 3), +}; + +static const struct rtd_pinctrl_desc rtd1319d_iso_pinctrl_desc = { + .pins = rtd1319d_iso_pins, + .num_pins = ARRAY_SIZE(rtd1319d_iso_pins), + .groups = rtd1319d_pin_groups, + .num_groups = ARRAY_SIZE(rtd1319d_pin_groups), + .functions = rtd1319d_pin_functions, + .num_functions = ARRAY_SIZE(rtd1319d_pin_functions), + .muxes = rtd1319d_iso_muxes, + .num_muxes = ARRAY_SIZE(rtd1319d_iso_muxes), + .configs = rtd1319d_iso_configs, + .num_configs = ARRAY_SIZE(rtd1319d_iso_configs), + .sconfigs = rtd1319d_iso_sconfigs, + .num_sconfigs = ARRAY_SIZE(rtd1319d_iso_sconfigs), +}; + +static int rtd1319d_pinctrl_probe(struct platform_device *pdev) +{ + return rtd_pinctrl_probe(pdev, &rtd1319d_iso_pinctrl_desc); +} + +static const struct of_device_id rtd1319d_pinctrl_of_match[] = { + { .compatible = "realtek,rtd1319d-pinctrl", }, + {}, +}; + +static struct platform_driver rtd1319d_pinctrl_driver = { + .driver = { + .name = "rtd1319d-pinctrl", + .of_match_table = rtd1319d_pinctrl_of_match, + }, + .probe = rtd1319d_pinctrl_probe, +}; + +static int __init rtd1319d_pinctrl_init(void) +{ + return platform_driver_register(&rtd1319d_pinctrl_driver); +} +arch_initcall(rtd1319d_pinctrl_init); + +static void __exit rtd1319d_pinctrl_exit(void) +{ + platform_driver_unregister(&rtd1319d_pinctrl_driver); +} +module_exit(rtd1319d_pinctrl_exit); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Realtek Semiconductor Corporation"); +MODULE_DESCRIPTION("Realtek DHC SoC RTD1319D pinctrl driver"); diff --git a/drivers/pinctrl/realtek/pinctrl-rtd1619b.c b/drivers/pinctrl/realtek/pinctrl-rtd1619b.c new file mode 100644 index 000000000000..b07e50d6356d --- /dev/null +++ b/drivers/pinctrl/realtek/pinctrl-rtd1619b.c @@ -0,0 +1,1601 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Realtek DHC 1619B pin controller driver + * + * Copyright (c) 2023 Realtek Semiconductor Corp. + * + */ + +#include <linux/module.h> +#include <linux/of.h> +#include <linux/platform_device.h> +#include <linux/pinctrl/pinctrl.h> + +#include "pinctrl-rtd.h" + +enum rtd16xxb_iso_pins { + RTD1619B_ISO_GPIO_0 = 0, + RTD1619B_ISO_GPIO_1, + RTD1619B_ISO_GPIO_2, + RTD1619B_ISO_GPIO_3, + RTD1619B_ISO_GPIO_4, + RTD1619B_ISO_GPIO_5, + RTD1619B_ISO_GPIO_6, + RTD1619B_ISO_GPIO_7, + RTD1619B_ISO_GPIO_8, + RTD1619B_ISO_GPIO_9, + RTD1619B_ISO_GPIO_10, + RTD1619B_ISO_GPIO_11, + RTD1619B_ISO_GPIO_12, + RTD1619B_ISO_GPIO_13, + RTD1619B_ISO_GPIO_14, + RTD1619B_ISO_GPIO_15, + RTD1619B_ISO_GPIO_16, + RTD1619B_ISO_GPIO_17, + RTD1619B_ISO_GPIO_18, + RTD1619B_ISO_GPIO_19, + RTD1619B_ISO_GPIO_20, + RTD1619B_ISO_GPIO_21, + RTD1619B_ISO_GPIO_22, + RTD1619B_ISO_GPIO_23, + RTD1619B_ISO_USB_CC2, + RTD1619B_ISO_GPIO_25, + RTD1619B_ISO_GPIO_26, + RTD1619B_ISO_GPIO_27, + RTD1619B_ISO_GPIO_28, + RTD1619B_ISO_GPIO_29, + RTD1619B_ISO_GPIO_30, + RTD1619B_ISO_GPIO_31, + RTD1619B_ISO_GPIO_32, + RTD1619B_ISO_GPIO_33, + RTD1619B_ISO_GPIO_34, + RTD1619B_ISO_GPIO_35, + RTD1619B_ISO_HIF_DATA, + RTD1619B_ISO_HIF_EN, + RTD1619B_ISO_HIF_RDY, + RTD1619B_ISO_HIF_CLK, + RTD1619B_ISO_GPIO_40, + RTD1619B_ISO_GPIO_41, + RTD1619B_ISO_GPIO_42, + RTD1619B_ISO_GPIO_43, + RTD1619B_ISO_GPIO_44, + RTD1619B_ISO_GPIO_45, + RTD1619B_ISO_GPIO_46, + RTD1619B_ISO_GPIO_47, + RTD1619B_ISO_GPIO_48, + RTD1619B_ISO_GPIO_49, + RTD1619B_ISO_GPIO_50, + RTD1619B_ISO_USB_CC1, + RTD1619B_ISO_GPIO_52, + RTD1619B_ISO_GPIO_53, + RTD1619B_ISO_IR_RX, + RTD1619B_ISO_UR0_RX, + RTD1619B_ISO_UR0_TX, + RTD1619B_ISO_GPIO_57, + RTD1619B_ISO_GPIO_58, + RTD1619B_ISO_GPIO_59, + RTD1619B_ISO_GPIO_60, + RTD1619B_ISO_GPIO_61, + RTD1619B_ISO_GPIO_62, + RTD1619B_ISO_GPIO_63, + RTD1619B_ISO_GPIO_64, + RTD1619B_ISO_GPIO_65, + RTD1619B_ISO_GPIO_66, + RTD1619B_ISO_GPIO_67, + RTD1619B_ISO_GPIO_68, + RTD1619B_ISO_GPIO_69, + RTD1619B_ISO_GPIO_70, + RTD1619B_ISO_GPIO_71, + RTD1619B_ISO_GPIO_72, + RTD1619B_ISO_GPIO_73, + RTD1619B_ISO_GPIO_74, + RTD1619B_ISO_GPIO_75, + RTD1619B_ISO_GPIO_76, + RTD1619B_ISO_EMMC_CMD, + RTD1619B_ISO_SPI_CE_N, + RTD1619B_ISO_SPI_SCK, + RTD1619B_ISO_SPI_SO, + RTD1619B_ISO_SPI_SI, + RTD1619B_ISO_EMMC_RST_N, + RTD1619B_ISO_EMMC_DD_SB, + RTD1619B_ISO_EMMC_CLK, + RTD1619B_ISO_EMMC_DATA_0, + RTD1619B_ISO_EMMC_DATA_1, + RTD1619B_ISO_EMMC_DATA_2, + RTD1619B_ISO_EMMC_DATA_3, + RTD1619B_ISO_EMMC_DATA_4, + RTD1619B_ISO_EMMC_DATA_5, + RTD1619B_ISO_EMMC_DATA_6, + RTD1619B_ISO_EMMC_DATA_7, + RTD1619B_ISO_UR2_LOC, + RTD1619B_ISO_GSPI_LOC, + RTD1619B_ISO_SDIO_LOC, + RTD1619B_ISO_HI_LOC, + RTD1619B_ISO_HI_WIDTH, + RTD1619B_ISO_SF_EN, + RTD1619B_ISO_ARM_TRACE_DBG_EN, + RTD1619B_ISO_PWM_01_OPEN_DRAIN_EN_LOC0, + RTD1619B_ISO_PWM_23_OPEN_DRAIN_EN_LOC0, + RTD1619B_ISO_PWM_01_OPEN_DRAIN_EN_LOC1, + RTD1619B_ISO_PWM_23_OPEN_DRAIN_EN_LOC1, + RTD1619B_ISO_EJTAG_ACPU_LOC, + RTD1619B_ISO_EJTAG_VCPU_LOC, + RTD1619B_ISO_EJTAG_SCPU_LOC, + RTD1619B_ISO_DMIC_LOC, + RTD1619B_ISO_ISO_GSPI_LOC, + RTD1619B_ISO_EJTAG_VE3_LOC, + RTD1619B_ISO_EJTAG_AUCPU0_LOC, + RTD1619B_ISO_EJTAG_AUCPU1_LOC, +}; + +static const struct pinctrl_pin_desc rtd1619b_iso_pins[] = { + PINCTRL_PIN(RTD1619B_ISO_GPIO_0, "gpio_0"), + PINCTRL_PIN(RTD1619B_ISO_GPIO_1, "gpio_1"), + PINCTRL_PIN(RTD1619B_ISO_GPIO_2, "gpio_2"), + PINCTRL_PIN(RTD1619B_ISO_GPIO_3, "gpio_3"), + PINCTRL_PIN(RTD1619B_ISO_GPIO_4, "gpio_4"), + PINCTRL_PIN(RTD1619B_ISO_GPIO_5, "gpio_5"), + PINCTRL_PIN(RTD1619B_ISO_GPIO_6, "gpio_6"), + PINCTRL_PIN(RTD1619B_ISO_GPIO_7, "gpio_7"), + PINCTRL_PIN(RTD1619B_ISO_GPIO_8, "gpio_8"), + PINCTRL_PIN(RTD1619B_ISO_GPIO_9, "gpio_9"), + PINCTRL_PIN(RTD1619B_ISO_GPIO_10, "gpio_10"), + PINCTRL_PIN(RTD1619B_ISO_GPIO_11, "gpio_11"), + PINCTRL_PIN(RTD1619B_ISO_GPIO_12, "gpio_12"), + PINCTRL_PIN(RTD1619B_ISO_GPIO_13, "gpio_13"), + PINCTRL_PIN(RTD1619B_ISO_GPIO_14, "gpio_14"), + PINCTRL_PIN(RTD1619B_ISO_GPIO_15, "gpio_15"), + PINCTRL_PIN(RTD1619B_ISO_GPIO_16, "gpio_16"), + PINCTRL_PIN(RTD1619B_ISO_GPIO_17, "gpio_17"), + PINCTRL_PIN(RTD1619B_ISO_GPIO_18, "gpio_18"), + PINCTRL_PIN(RTD1619B_ISO_GPIO_19, "gpio_19"), + PINCTRL_PIN(RTD1619B_ISO_GPIO_20, "gpio_20"), + PINCTRL_PIN(RTD1619B_ISO_GPIO_21, "gpio_21"), + PINCTRL_PIN(RTD1619B_ISO_GPIO_22, "gpio_22"), + PINCTRL_PIN(RTD1619B_ISO_GPIO_23, "gpio_23"), + PINCTRL_PIN(RTD1619B_ISO_USB_CC2, "usb_cc2"), + PINCTRL_PIN(RTD1619B_ISO_GPIO_25, "gpio_25"), + PINCTRL_PIN(RTD1619B_ISO_GPIO_26, "gpio_26"), + PINCTRL_PIN(RTD1619B_ISO_GPIO_27, "gpio_27"), + PINCTRL_PIN(RTD1619B_ISO_GPIO_28, "gpio_28"), + PINCTRL_PIN(RTD1619B_ISO_GPIO_29, "gpio_29"), + PINCTRL_PIN(RTD1619B_ISO_GPIO_30, "gpio_30"), + PINCTRL_PIN(RTD1619B_ISO_GPIO_31, "gpio_31"), + PINCTRL_PIN(RTD1619B_ISO_GPIO_32, "gpio_32"), + PINCTRL_PIN(RTD1619B_ISO_GPIO_33, "gpio_33"), + PINCTRL_PIN(RTD1619B_ISO_GPIO_34, "gpio_34"), + PINCTRL_PIN(RTD1619B_ISO_GPIO_35, "gpio_35"), + PINCTRL_PIN(RTD1619B_ISO_HIF_DATA, "hif_data"), + PINCTRL_PIN(RTD1619B_ISO_HIF_EN, "hif_en"), + PINCTRL_PIN(RTD1619B_ISO_HIF_RDY, "hif_rdy"), + PINCTRL_PIN(RTD1619B_ISO_HIF_CLK, "hif_clk"), + PINCTRL_PIN(RTD1619B_ISO_GPIO_40, "gpio_40"), + PINCTRL_PIN(RTD1619B_ISO_GPIO_41, "gpio_41"), + PINCTRL_PIN(RTD1619B_ISO_GPIO_42, "gpio_42"), + PINCTRL_PIN(RTD1619B_ISO_GPIO_43, "gpio_43"), + PINCTRL_PIN(RTD1619B_ISO_GPIO_44, "gpio_44"), + PINCTRL_PIN(RTD1619B_ISO_GPIO_45, "gpio_45"), + PINCTRL_PIN(RTD1619B_ISO_GPIO_46, "gpio_46"), + PINCTRL_PIN(RTD1619B_ISO_GPIO_47, "gpio_47"), + PINCTRL_PIN(RTD1619B_ISO_GPIO_48, "gpio_48"), + PINCTRL_PIN(RTD1619B_ISO_GPIO_49, "gpio_49"), + PINCTRL_PIN(RTD1619B_ISO_GPIO_50, "gpio_50"), + PINCTRL_PIN(RTD1619B_ISO_USB_CC1, "usb_cc1"), + PINCTRL_PIN(RTD1619B_ISO_GPIO_52, "gpio_52"), + PINCTRL_PIN(RTD1619B_ISO_GPIO_53, "gpio_53"), + PINCTRL_PIN(RTD1619B_ISO_IR_RX, "ir_rx"), + PINCTRL_PIN(RTD1619B_ISO_UR0_RX, "ur0_rx"), + PINCTRL_PIN(RTD1619B_ISO_UR0_TX, "ur0_tx"), + PINCTRL_PIN(RTD1619B_ISO_GPIO_57, "gpio_57"), + PINCTRL_PIN(RTD1619B_ISO_GPIO_58, "gpio_58"), + PINCTRL_PIN(RTD1619B_ISO_GPIO_59, "gpio_59"), + PINCTRL_PIN(RTD1619B_ISO_GPIO_60, "gpio_60"), + PINCTRL_PIN(RTD1619B_ISO_GPIO_61, "gpio_61"), + PINCTRL_PIN(RTD1619B_ISO_GPIO_62, "gpio_62"), + PINCTRL_PIN(RTD1619B_ISO_GPIO_63, "gpio_63"), + PINCTRL_PIN(RTD1619B_ISO_GPIO_64, "gpio_64"), + PINCTRL_PIN(RTD1619B_ISO_GPIO_65, "gpio_65"), + PINCTRL_PIN(RTD1619B_ISO_GPIO_66, "gpio_66"), + PINCTRL_PIN(RTD1619B_ISO_GPIO_67, "gpio_67"), + PINCTRL_PIN(RTD1619B_ISO_GPIO_68, "gpio_68"), + PINCTRL_PIN(RTD1619B_ISO_GPIO_69, "gpio_69"), + PINCTRL_PIN(RTD1619B_ISO_GPIO_70, "gpio_70"), + PINCTRL_PIN(RTD1619B_ISO_GPIO_71, "gpio_71"), + PINCTRL_PIN(RTD1619B_ISO_GPIO_72, "gpio_72"), + PINCTRL_PIN(RTD1619B_ISO_GPIO_73, "gpio_73"), + PINCTRL_PIN(RTD1619B_ISO_GPIO_74, "gpio_74"), + PINCTRL_PIN(RTD1619B_ISO_GPIO_75, "gpio_75"), + PINCTRL_PIN(RTD1619B_ISO_GPIO_76, "gpio_76"), + PINCTRL_PIN(RTD1619B_ISO_EMMC_CMD, "emmc_cmd"), + PINCTRL_PIN(RTD1619B_ISO_SPI_CE_N, "spi_ce_n"), + PINCTRL_PIN(RTD1619B_ISO_SPI_SCK, "spi_sck"), + PINCTRL_PIN(RTD1619B_ISO_SPI_SO, "spi_so"), + PINCTRL_PIN(RTD1619B_ISO_SPI_SI, "spi_si"), + PINCTRL_PIN(RTD1619B_ISO_EMMC_RST_N, "emmc_rst_n"), + PINCTRL_PIN(RTD1619B_ISO_EMMC_DD_SB, "emmc_dd_sb"), + PINCTRL_PIN(RTD1619B_ISO_EMMC_CLK, "emmc_clk"), + PINCTRL_PIN(RTD1619B_ISO_EMMC_DATA_0, "emmc_data_0"), + PINCTRL_PIN(RTD1619B_ISO_EMMC_DATA_1, "emmc_data_1"), + PINCTRL_PIN(RTD1619B_ISO_EMMC_DATA_2, "emmc_data_2"), + PINCTRL_PIN(RTD1619B_ISO_EMMC_DATA_3, "emmc_data_3"), + PINCTRL_PIN(RTD1619B_ISO_EMMC_DATA_4, "emmc_data_4"), + PINCTRL_PIN(RTD1619B_ISO_EMMC_DATA_5, "emmc_data_5"), + PINCTRL_PIN(RTD1619B_ISO_EMMC_DATA_6, "emmc_data_6"), + PINCTRL_PIN(RTD1619B_ISO_EMMC_DATA_7, "emmc_data_7"), + PINCTRL_PIN(RTD1619B_ISO_UR2_LOC, "ur2_loc"), + PINCTRL_PIN(RTD1619B_ISO_GSPI_LOC, "gspi_loc"), + PINCTRL_PIN(RTD1619B_ISO_SDIO_LOC, "sdio_loc"), + PINCTRL_PIN(RTD1619B_ISO_HI_LOC, "hi_loc"), + PINCTRL_PIN(RTD1619B_ISO_HI_WIDTH, "hi_width"), + PINCTRL_PIN(RTD1619B_ISO_SF_EN, "sf_en"), + PINCTRL_PIN(RTD1619B_ISO_ARM_TRACE_DBG_EN, "arm_trace_dbg_en"), + PINCTRL_PIN(RTD1619B_ISO_PWM_01_OPEN_DRAIN_EN_LOC0, "pwm_01_open_drain_en_loc0"), + PINCTRL_PIN(RTD1619B_ISO_PWM_23_OPEN_DRAIN_EN_LOC0, "pwm_23_open_drain_en_loc0"), + PINCTRL_PIN(RTD1619B_ISO_PWM_01_OPEN_DRAIN_EN_LOC1, "pwm_01_open_drain_en_loc1"), + PINCTRL_PIN(RTD1619B_ISO_PWM_23_OPEN_DRAIN_EN_LOC1, "pwm_23_open_drain_en_loc1"), + PINCTRL_PIN(RTD1619B_ISO_EJTAG_ACPU_LOC, "ejtag_acpu_loc"), + PINCTRL_PIN(RTD1619B_ISO_EJTAG_VCPU_LOC, "ejtag_vcpu_loc"), + PINCTRL_PIN(RTD1619B_ISO_EJTAG_SCPU_LOC, "ejtag_scpu_loc"), + PINCTRL_PIN(RTD1619B_ISO_DMIC_LOC, "dmic_loc"), + PINCTRL_PIN(RTD1619B_ISO_ISO_GSPI_LOC, "iso_gspi_loc"), + PINCTRL_PIN(RTD1619B_ISO_EJTAG_VE3_LOC, "ejtag_ve3_loc"), + PINCTRL_PIN(RTD1619B_ISO_EJTAG_AUCPU0_LOC, "ejtag_aucpu0_loc"), + PINCTRL_PIN(RTD1619B_ISO_EJTAG_AUCPU1_LOC, "ejtag_aucpu1_loc"), +}; + +#define DECLARE_RTD1619B_PIN(_pin, _name) \ + static const unsigned int rtd1619b_## _name ##_pins[] = { _pin } + +DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_0, gpio_0); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_1, gpio_1); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_2, gpio_2); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_3, gpio_3); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_4, gpio_4); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_5, gpio_5); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_6, gpio_6); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_7, gpio_7); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_8, gpio_8); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_9, gpio_9); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_10, gpio_10); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_11, gpio_11); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_12, gpio_12); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_13, gpio_13); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_14, gpio_14); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_15, gpio_15); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_16, gpio_16); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_17, gpio_17); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_18, gpio_18); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_19, gpio_19); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_20, gpio_20); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_21, gpio_21); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_22, gpio_22); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_23, gpio_23); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_USB_CC2, usb_cc2); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_25, gpio_25); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_26, gpio_26); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_27, gpio_27); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_28, gpio_28); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_29, gpio_29); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_30, gpio_30); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_31, gpio_31); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_32, gpio_32); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_33, gpio_33); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_34, gpio_34); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_35, gpio_35); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_HIF_DATA, hif_data); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_HIF_EN, hif_en); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_HIF_RDY, hif_rdy); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_HIF_CLK, hif_clk); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_40, gpio_40); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_41, gpio_41); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_42, gpio_42); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_43, gpio_43); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_44, gpio_44); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_45, gpio_45); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_46, gpio_46); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_47, gpio_47); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_48, gpio_48); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_49, gpio_49); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_50, gpio_50); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_USB_CC1, usb_cc1); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_52, gpio_52); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_53, gpio_53); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_IR_RX, ir_rx); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_UR0_RX, ur0_rx); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_UR0_TX, ur0_tx); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_57, gpio_57); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_58, gpio_58); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_59, gpio_59); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_60, gpio_60); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_61, gpio_61); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_62, gpio_62); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_63, gpio_63); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_64, gpio_64); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_65, gpio_65); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_66, gpio_66); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_67, gpio_67); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_68, gpio_68); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_69, gpio_69); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_70, gpio_70); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_71, gpio_71); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_72, gpio_72); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_73, gpio_73); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_74, gpio_74); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_75, gpio_75); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_76, gpio_76); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_EMMC_CMD, emmc_cmd); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_SPI_CE_N, spi_ce_n); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_SPI_SCK, spi_sck); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_SPI_SO, spi_so); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_SPI_SI, spi_si); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_EMMC_RST_N, emmc_rst_n); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_EMMC_DD_SB, emmc_dd_sb); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_EMMC_CLK, emmc_clk); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_EMMC_DATA_0, emmc_data_0); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_EMMC_DATA_1, emmc_data_1); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_EMMC_DATA_2, emmc_data_2); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_EMMC_DATA_3, emmc_data_3); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_EMMC_DATA_4, emmc_data_4); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_EMMC_DATA_5, emmc_data_5); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_EMMC_DATA_6, emmc_data_6); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_EMMC_DATA_7, emmc_data_7); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_UR2_LOC, ur2_loc); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_GSPI_LOC, gspi_loc); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_SDIO_LOC, sdio_loc); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_HI_LOC, hi_loc); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_HI_WIDTH, hi_width); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_SF_EN, sf_en); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_ARM_TRACE_DBG_EN, arm_trace_dbg_en); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_PWM_01_OPEN_DRAIN_EN_LOC0, pwm_01_open_drain_en_loc0); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_PWM_23_OPEN_DRAIN_EN_LOC0, pwm_23_open_drain_en_loc0); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_PWM_01_OPEN_DRAIN_EN_LOC1, pwm_01_open_drain_en_loc1); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_PWM_23_OPEN_DRAIN_EN_LOC1, pwm_23_open_drain_en_loc1); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_EJTAG_ACPU_LOC, ejtag_acpu_loc); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_EJTAG_VCPU_LOC, ejtag_vcpu_loc); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_EJTAG_SCPU_LOC, ejtag_scpu_loc); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_DMIC_LOC, dmic_loc); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_ISO_GSPI_LOC, iso_gspi_loc); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_EJTAG_VE3_LOC, ejtag_ve3_loc); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_EJTAG_AUCPU0_LOC, ejtag_aucpu0_loc); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_EJTAG_AUCPU1_LOC, ejtag_aucpu1_loc); + +#define RTD1619B_GROUP(_name) \ + { \ + .name = # _name, \ + .pins = rtd1619b_ ## _name ## _pins, \ + .num_pins = ARRAY_SIZE(rtd1619b_ ## _name ## _pins), \ + } + +static const struct rtd_pin_group_desc rtd1619b_pin_groups[] = { + RTD1619B_GROUP(gpio_0), + RTD1619B_GROUP(gpio_1), + RTD1619B_GROUP(gpio_2), + RTD1619B_GROUP(gpio_3), + RTD1619B_GROUP(gpio_4), + RTD1619B_GROUP(gpio_5), + RTD1619B_GROUP(gpio_6), + RTD1619B_GROUP(gpio_7), + RTD1619B_GROUP(gpio_8), + RTD1619B_GROUP(gpio_9), + RTD1619B_GROUP(gpio_10), + RTD1619B_GROUP(gpio_11), + RTD1619B_GROUP(gpio_12), + RTD1619B_GROUP(gpio_13), + RTD1619B_GROUP(gpio_14), + RTD1619B_GROUP(gpio_15), + RTD1619B_GROUP(gpio_16), + RTD1619B_GROUP(gpio_17), + RTD1619B_GROUP(gpio_18), + RTD1619B_GROUP(gpio_19), + RTD1619B_GROUP(gpio_20), + RTD1619B_GROUP(gpio_21), + RTD1619B_GROUP(gpio_22), + RTD1619B_GROUP(gpio_23), + RTD1619B_GROUP(usb_cc2), + RTD1619B_GROUP(gpio_25), + RTD1619B_GROUP(gpio_26), + RTD1619B_GROUP(gpio_27), + RTD1619B_GROUP(gpio_28), + RTD1619B_GROUP(gpio_29), + RTD1619B_GROUP(gpio_30), + RTD1619B_GROUP(gpio_31), + RTD1619B_GROUP(gpio_32), + RTD1619B_GROUP(gpio_33), + RTD1619B_GROUP(gpio_34), + RTD1619B_GROUP(gpio_35), + RTD1619B_GROUP(hif_data), + RTD1619B_GROUP(hif_en), + RTD1619B_GROUP(hif_rdy), + RTD1619B_GROUP(hif_clk), + RTD1619B_GROUP(gpio_40), + RTD1619B_GROUP(gpio_41), + RTD1619B_GROUP(gpio_42), + RTD1619B_GROUP(gpio_43), + RTD1619B_GROUP(gpio_44), + RTD1619B_GROUP(gpio_45), + RTD1619B_GROUP(gpio_46), + RTD1619B_GROUP(gpio_47), + RTD1619B_GROUP(gpio_48), + RTD1619B_GROUP(gpio_49), + RTD1619B_GROUP(gpio_50), + RTD1619B_GROUP(usb_cc1), + RTD1619B_GROUP(gpio_52), + RTD1619B_GROUP(gpio_53), + RTD1619B_GROUP(ir_rx), + RTD1619B_GROUP(ur0_rx), + RTD1619B_GROUP(ur0_tx), + RTD1619B_GROUP(gpio_57), + RTD1619B_GROUP(gpio_58), + RTD1619B_GROUP(gpio_59), + RTD1619B_GROUP(gpio_60), + RTD1619B_GROUP(gpio_61), + RTD1619B_GROUP(gpio_62), + RTD1619B_GROUP(gpio_63), + RTD1619B_GROUP(gpio_64), + RTD1619B_GROUP(gpio_65), + RTD1619B_GROUP(gpio_66), + RTD1619B_GROUP(gpio_67), + RTD1619B_GROUP(gpio_68), + RTD1619B_GROUP(gpio_69), + RTD1619B_GROUP(gpio_70), + RTD1619B_GROUP(gpio_71), + RTD1619B_GROUP(gpio_72), + RTD1619B_GROUP(gpio_73), + RTD1619B_GROUP(gpio_74), + RTD1619B_GROUP(gpio_75), + RTD1619B_GROUP(gpio_76), + RTD1619B_GROUP(emmc_cmd), + RTD1619B_GROUP(spi_ce_n), + RTD1619B_GROUP(spi_sck), + RTD1619B_GROUP(spi_so), + RTD1619B_GROUP(spi_si), + RTD1619B_GROUP(emmc_rst_n), + RTD1619B_GROUP(emmc_dd_sb), + RTD1619B_GROUP(emmc_clk), + RTD1619B_GROUP(emmc_data_0), + RTD1619B_GROUP(emmc_data_1), + RTD1619B_GROUP(emmc_data_2), + RTD1619B_GROUP(emmc_data_3), + RTD1619B_GROUP(emmc_data_4), + RTD1619B_GROUP(emmc_data_5), + RTD1619B_GROUP(emmc_data_6), + RTD1619B_GROUP(emmc_data_7), + RTD1619B_GROUP(ur2_loc), + RTD1619B_GROUP(gspi_loc), + RTD1619B_GROUP(sdio_loc), + RTD1619B_GROUP(hi_loc), + RTD1619B_GROUP(hi_width), + RTD1619B_GROUP(sf_en), + RTD1619B_GROUP(arm_trace_dbg_en), + RTD1619B_GROUP(pwm_01_open_drain_en_loc0), + RTD1619B_GROUP(pwm_23_open_drain_en_loc0), + RTD1619B_GROUP(pwm_01_open_drain_en_loc1), + RTD1619B_GROUP(pwm_23_open_drain_en_loc1), + RTD1619B_GROUP(ejtag_acpu_loc), + RTD1619B_GROUP(ejtag_vcpu_loc), + RTD1619B_GROUP(ejtag_scpu_loc), + RTD1619B_GROUP(dmic_loc), + RTD1619B_GROUP(iso_gspi_loc), + RTD1619B_GROUP(ejtag_ve3_loc), + RTD1619B_GROUP(ejtag_aucpu0_loc), + RTD1619B_GROUP(ejtag_aucpu1_loc), +}; + +static const char * const rtd1619b_gpio_groups[] = { + "gpio_0", "gpio_1", "gpio_2", "gpio_3", "gpio_4", + "gpio_5", "gpio_6", "gpio_7", "gpio_8", "gpio_9", + "gpio_10", "gpio_11", "gpio_12", "gpio_13", "gpio_14", + "gpio_15", "gpio_16", "gpio_17", "gpio_18", "gpio_19", + "gpio_20", "gpio_21", "gpio_22", "gpio_23", "usb_cc2", + "gpio_25", "gpio_26", "gpio_27", "gpio_28", "gpio_29", + "gpio_30", "gpio_31", "gpio_32", "gpio_33", "gpio_34", + "gpio_35", "hif_data", "hif_en", "hif_rdy", "hif_clk", + "gpio_40", "gpio_41", "gpio_42", "gpio_43", "gpio_44", + "gpio_45", "gpio_46", "gpio_47", "gpio_48", "gpio_49", + "gpio_50", "usb_cc1", "gpio_52", "gpio_53", "ir_rx", + "ur0_rx", "ur0_tx", "gpio_57", "gpio_58", "gpio_59", + "gpio_60", "gpio_61", "gpio_62", "gpio_63", "gpio_64", + "gpio_65", "gpio_66", "gpio_67", "gpio_68", "gpio_69", + "gpio_70", "gpio_71", "gpio_72", "gpio_73", "gpio_74", + "gpio_75", "gpio_76", "emmc_cmd", "spi_ce_n", "spi_sck", + "spi_so", "spi_si"}; +static const char * const rtd1619b_nf_groups[] = { + "emmc_rst_n", "emmc_clk", "emmc_cmd", "emmc_data_0", "emmc_data_1", + "emmc_data_2", "emmc_data_3", "emmc_data_4", + "emmc_data_5", "emmc_data_6", "emmc_data_7", "spi_ce_n", + "spi_sck", "spi_so", "spi_si" }; +static const char * const rtd1619b_nf_spi_groups[] = { + "emmc_data_0", "emmc_data_1", + "emmc_data_2", "emmc_data_3", "emmc_data_4", + "emmc_data_5" }; +static const char * const rtd1619b_spi_groups[] = { + "spi_ce_n", "spi_sck", "spi_so", "spi_si" }; +static const char * const rtd1619b_emmc_groups[] = { + "emmc_rst_n", "emmc_clk", "emmc_data_0", "emmc_data_1", + "emmc_data_2", "emmc_data_3", "emmc_data_4", + "emmc_data_5", "emmc_data_6", "emmc_data_7", + "emmc_dd_sb", "emmc_cmd"}; + +static const char * const rtd1619b_pmic_groups[] = { "spi_ce_n" }; +static const char * const rtd1619b_spdif_groups[] = { "gpio_50" }; +static const char * const rtd1619b_spdif_coaxial_groups[] = { "gpio_1" }; +static const char * const rtd1619b_spdif_optical_loc0_groups[] = { "gpio_6" }; +static const char * const rtd1619b_spdif_optical_loc1_groups[] = { "gpio_21" }; + +static const char * const rtd1619b_emmc_spi_groups[] = { + "gpio_1", "gpio_2", "gpio_3", "gpio_4", "gpio_5", "gpio_6" }; +static const char * const rtd1619b_sc1_groups[] = { + "gpio_2", "gpio_3", "gpio_4", "gpio_5" }; +static const char * const rtd1619b_uart0_groups[] = { "ur0_rx", "ur0_tx" }; +static const char * const rtd1619b_uart1_groups[] = { + "gpio_8", "gpio_9", "gpio_10", "gpio_11" }; +static const char * const rtd1619b_uart2_loc0_groups[] = { + "gpio_18", "gpio_19", "gpio_20", "gpio_31", "ur2_loc" }; +static const char * const rtd1619b_uart2_loc1_groups[] = { + "gpio_25", "gpio_26", "gpio_27", "gpio_28", "ur2_loc" }; +static const char * const rtd1619b_gspi_loc1_groups[] = { + "gpio_8", "gpio_9", "gpio_10", "gpio_11", "gspi_loc" }; +static const char * const rtd1619b_iso_gspi_loc1_groups[] = { + "gpio_8", "gpio_9", "gpio_10", "gpio_11", "iso_gspi_loc" }; +static const char * const rtd1619b_i2c0_groups[] = { "gpio_12", "gpio_13" }; +static const char * const rtd1619b_i2c1_groups[] = { "gpio_16", "gpio_17" }; +static const char * const rtd1619b_i2c3_groups[] = { "gpio_63", "gpio_64" }; +static const char * const rtd1619b_i2c4_groups[] = { "gpio_34", "gpio_35" }; +static const char * const rtd1619b_i2c5_groups[] = { "gpio_29", "gpio_46" }; +static const char * const rtd1619b_pwm0_groups[] = { "gpio_20", "gpio_26" }; +static const char * const rtd1619b_pwm1_groups[] = { "gpio_21", "gpio_27" }; +static const char * const rtd1619b_pwm2_groups[] = { "gpio_22", "gpio_28" }; +static const char * const rtd1619b_pwm3_groups[] = { "gpio_23", "gpio_47" }; +static const char * const rtd1619b_etn_led_groups[] = { "gpio_14", "gpio_15", "gpio_23" }; +static const char * const rtd1619b_etn_phy_groups[] = { "gpio_14", "gpio_15" }; +static const char * const rtd1619b_etn_clk_groups[] = { "gpio_14" }; +static const char * const rtd1619b_sc0_groups[] = { + "gpio_18", "gpio_19", "gpio_20", "gpio_31" }; +static const char * const rtd1619b_vfd_groups[] = { + "gpio_26", "gpio_27", "gpio_28" }; + +static const char * const rtd1619b_gspi_loc0_groups[] = { + "gpio_18", "gpio_19", "gpio_20", "gpio_31", "gspi_loc" }; +static const char * const rtd1619b_iso_gspi_loc0_groups[] = { + "gpio_18", "gpio_19", "gpio_20", "gpio_31", "iso_gspi_loc" }; +static const char * const rtd1619b_pcie1_groups[] = { "gpio_25" }; +static const char * const rtd1619b_pcie2_groups[] = { "gpio_52" }; +static const char * const rtd1619b_sd_groups[] = { + "gpio_32", "gpio_33", "gpio_34", "gpio_35", "hif_data", + "hif_en", "hif_rdy", "hif_clk" }; +static const char * const rtd1619b_sdio_loc0_groups[] = { + "gpio_32", "gpio_33", "hif_data", "hif_en", + "hif_rdy", "hif_clk", "sdio_loc" }; +static const char * const rtd1619b_sdio_loc1_groups[] = { + "gpio_40", "gpio_41", "gpio_42", "gpio_43", "gpio_44", + "gpio_45", "sdio_loc" }; +static const char * const rtd1619b_hi_groups[] = { + "hif_data", "hif_en", "hif_rdy", "hif_clk" }; +static const char * const rtd1619b_hi_m_groups[] = { + "hif_data", "hif_en", "hif_rdy", "hif_clk" }; +static const char * const rtd1619b_dc_fan_groups[] = { "gpio_47" }; +static const char * const rtd1619b_pll_test_loc0_groups[] = { "gpio_52", "gpio_53" }; +static const char * const rtd1619b_pll_test_loc1_groups[] = { "gpio_48", "gpio_49" }; +static const char * const rtd1619b_tdm_ai_loc0_groups[] = { + "gpio_57", "gpio_58", "gpio_59", "gpio_60" }; +static const char * const rtd1619b_tdm_ai_loc1_groups[] = { + "hif_data", "hif_en", "hif_rdy", "hif_clk" }; +static const char * const rtd1619b_dmic_loc0_groups[] = { + "gpio_57", "gpio_58", "gpio_59", "gpio_60", "gpio_61", + "gpio_62", "gpio_63", "gpio_64", "dmic_loc"}; +static const char * const rtd1619b_dmic_loc1_groups[] = { + "gpio_32", "gpio_33", "gpio_34", "gpio_35", "hif_data", + "hif_en", "hif_rdy", "hif_clk", "dmic_loc" }; +static const char * const rtd1619b_ai_loc0_groups[] = { + "gpio_57", "gpio_58", "gpio_59", "gpio_60", "gpio_61", + "gpio_62", "gpio_63" }; +static const char * const rtd1619b_ai_loc1_groups[] = { + "gpio_32", "gpio_33", "gpio_34", "hif_data", + "hif_en", "hif_rdy", "hif_clk"}; +static const char * const rtd1619b_tp0_groups[] = { + "gpio_66", "gpio_67", "gpio_68", "gpio_69", + "gpio_70", "gpio_71", "gpio_72", "gpio_73", "gpio_74", + "gpio_75", "gpio_76" }; +static const char * const rtd1619b_tp1_groups[] = { + "gpio_69", "gpio_70", "gpio_71", "gpio_72" }; +static const char * const rtd1619b_ao_groups[] = { + "gpio_66", "gpio_67", "gpio_68", "gpio_69", + "gpio_70", "gpio_71", "gpio_72" }; +static const char * const rtd1619b_uart2_disable_groups[] = { "ur2_loc" }; +static const char * const rtd1619b_gspi_disable_groups[] = { "gspi_loc" }; +static const char * const rtd1619b_sdio_disable_groups[] = { "sdio_loc" }; +static const char * const rtd1619b_hi_loc_disable_groups[] = { "hi_loc" }; +static const char * const rtd1619b_hi_loc0_groups[] = { "hi_loc" }; +static const char * const rtd1619b_hi_width_disable_groups[] = { "hi_width" }; +static const char * const rtd1619b_hi_width_1bit_groups[] = { "hi_width" }; + +static const char * const rtd1619b_vtc_i2si_loc0_groups[] = { + "gpio_32", "hif_data", "hif_en", "hif_rdy", "hif_clk" }; +static const char * const rtd1619b_vtc_tdm_loc0_groups[] = { + "hif_data", "hif_en", "hif_rdy", "hif_clk" }; +static const char * const rtd1619b_vtc_dmic_loc0_groups[] = { + "hif_data", "hif_en", "hif_rdy", "hif_clk" }; +static const char * const rtd1619b_vtc_i2si_loc1_groups[] = { + "gpio_57", "gpio_58", "gpio_59", "gpio_60", "gpio_61" }; +static const char * const rtd1619b_vtc_tdm_loc1_groups[] = { + "gpio_57", "gpio_58", "gpio_59", "gpio_60" }; +static const char * const rtd1619b_vtc_dmic_loc1_groups[] = { + "gpio_57", "gpio_58", "gpio_59", "gpio_60" }; +static const char * const rtd1619b_vtc_i2so_groups[] = { + "gpio_66", "gpio_67", "gpio_68", "gpio_69" }; +static const char * const rtd1619b_ve3_ejtag_loc0_groups[] = { + "gpio_2", "gpio_3", "gpio_4", + "gpio_5", "gpio_6", "ejtag_ve3_loc" }; +static const char * const rtd1619b_aucpu0_ejtag_loc0_groups[] = { + "gpio_2", "gpio_3", "gpio_4", + "gpio_5", "gpio_6", "ejtag_aucpu0_loc" }; +static const char * const rtd1619b_aucpu1_ejtag_loc0_groups[] = { + "gpio_2", "gpio_3", "gpio_4", + "gpio_5", "gpio_6", "ejtag_aucpu1_loc" }; +static const char * const rtd1619b_ve3_ejtag_loc1_groups[] = { + "gpio_32", "gpio_33", "hif_data", "hif_en", + "hif_clk", "ejtag_ve3_loc" }; +static const char * const rtd1619b_aucpu0_ejtag_loc1_groups[] = { + "gpio_32", "gpio_33", "hif_data", "hif_en", + "hif_clk", "ejtag_aucpu0_loc" }; +static const char * const rtd1619b_aucpu1_ejtag_loc1_groups[] = { + "gpio_32", "gpio_33", "hif_data", "hif_en", + "hif_clk", "ejtag_aucpu1_loc" }; + +static const char * const rtd1619b_ve3_ejtag_loc2_groups[] = { + "gpio_71", "gpio_72", "gpio_73", "gpio_74", + "gpio_75", "gpio_76", "ejtag_ve3_loc" }; +static const char * const rtd1619b_aucpu0_ejtag_loc2_groups[] = { + "gpio_71", "gpio_72", "gpio_73", "gpio_74", + "gpio_75", "gpio_76", "ejtag_aucpu0_loc" }; +static const char * const rtd1619b_aucpu1_ejtag_loc2_groups[] = { + "gpio_71", "gpio_72", "gpio_73", "gpio_74", + "gpio_75", "gpio_76", "ejtag_aucpu1_loc" }; + +static const char * const rtd1619b_scpu_ejtag_loc0_groups[] = { + "gpio_2", "gpio_3", "gpio_4", + "gpio_5", "gpio_6", "ejtag_scpu_loc" }; +static const char * const rtd1619b_acpu_ejtag_loc0_groups[] = { + "gpio_2", "gpio_3", "gpio_4", + "gpio_5", "gpio_6", "ejtag_acpu_loc" }; +static const char * const rtd1619b_vcpu_ejtag_loc0_groups[] = { + "gpio_2", "gpio_3", "gpio_4", + "gpio_5", "gpio_6", "ejtag_vcpu_loc" }; +static const char * const rtd1619b_scpu_ejtag_loc1_groups[] = { + "gpio_32", "gpio_33", "hif_data", "hif_en", + "hif_clk", "ejtag_scpu_loc" }; +static const char * const rtd1619b_acpu_ejtag_loc1_groups[] = { + "gpio_32", "gpio_33", "hif_data", "hif_en", + "hif_clk", "ejtag_acpu_loc" }; +static const char * const rtd1619b_vcpu_ejtag_loc1_groups[] = { + "gpio_32", "gpio_33", "hif_data", "hif_en", + "hif_clk", "ejtag_vcpu_loc" }; + +static const char * const rtd1619b_scpu_ejtag_loc2_groups[] = { + "gpio_71", "gpio_72", "gpio_73", "gpio_74", + "gpio_75", "gpio_76", "ejtag_scpu_loc" }; +static const char * const rtd1619b_acpu_ejtag_loc2_groups[] = { + "gpio_71", "gpio_72", "gpio_73", "gpio_74", + "gpio_75", "gpio_76", "ejtag_acpu_loc" }; +static const char * const rtd1619b_vcpu_ejtag_loc2_groups[] = { + "gpio_71", "gpio_72", "gpio_73", "gpio_74", + "gpio_75", "gpio_76", "ejtag_vcpu_loc"}; +static const char * const rtd1619b_ve3_ejtag_disable_groups[] = { "ejtag_ve3_loc" }; +static const char * const rtd1619b_aucpu0_ejtag_disable_groups[] = { "ejtag_aucpu0_loc" }; +static const char * const rtd1619b_aucpu1_ejtag_disable_groups[] = { "ejtag_aucpu1_loc" }; + +static const char * const rtd1619b_acpu_ejtag_disable_groups[] = { "ejtag_acpu_loc" }; +static const char * const rtd1619b_vcpu_ejtag_disable_groups[] = { "ejtag_vcpu_loc" }; +static const char * const rtd1619b_scpu_ejtag_disable_groups[] = { "ejtag_scpu_loc" }; +static const char * const rtd1619b_sf_disable_groups[] = { "sf_en" }; +static const char * const rtd1619b_sf_enable_groups[] = { "sf_en" }; +static const char * const rtd1619b_iso_gspi_disable_groups[] = { "iso_gspi_loc" }; +static const char * const rtd1619b_arm_trace_debug_disable_groups[] = { "arm_trace_dbg_en" }; +static const char * const rtd1619b_arm_trace_debug_enable_groups[] = { "arm_trace_dbg_en" }; +static const char * const rtd1619b_pwm_normal_groups[] = { + "pwm_01_open_drain_en_loc0", "pwm_23_open_drain_en_loc0", + "pwm_01_open_drain_en_loc1", "pwm_23_open_drain_en_loc1" }; +static const char * const rtd1619b_pwm_open_drain_groups[] = { + "pwm_01_open_drain_en_loc0", "pwm_23_open_drain_en_loc0", + "pwm_01_open_drain_en_loc1", "pwm_23_open_drain_en_loc1" }; +static const char * const rtd1619b_standby_dbg_groups[] = { + "gpio_2", "gpio_3", "ir_rx" }; + +static const char * const rtd1619b_usb_cc1_groups[] = { "usb_cc1" }; +static const char * const rtd1619b_usb_cc2_groups[] = { "usb_cc2" }; +static const char * const rtd1619b_ir_rx_groups[] = { "ir_rx" }; +static const char * const rtd1619b_test_loop_dis_groups[] = { "gpio_50" }; + +#define RTD1619B_FUNC(_name) \ + { \ + .name = # _name, \ + .groups = rtd1619b_ ## _name ## _groups, \ + .num_groups = ARRAY_SIZE(rtd1619b_ ## _name ## _groups), \ + } + +static const struct rtd_pin_func_desc rtd1619b_pin_functions[] = { + RTD1619B_FUNC(gpio), + RTD1619B_FUNC(nf), + RTD1619B_FUNC(nf_spi), + RTD1619B_FUNC(spi), + RTD1619B_FUNC(pmic), + RTD1619B_FUNC(spdif), + RTD1619B_FUNC(spdif_coaxial), + RTD1619B_FUNC(spdif_optical_loc0), + RTD1619B_FUNC(spdif_optical_loc1), + RTD1619B_FUNC(emmc_spi), + RTD1619B_FUNC(emmc), + RTD1619B_FUNC(sc1), + RTD1619B_FUNC(uart0), + RTD1619B_FUNC(uart1), + RTD1619B_FUNC(uart2_loc0), + RTD1619B_FUNC(uart2_loc1), + RTD1619B_FUNC(gspi_loc1), + RTD1619B_FUNC(iso_gspi_loc1), + RTD1619B_FUNC(i2c0), + RTD1619B_FUNC(i2c1), + RTD1619B_FUNC(i2c3), + RTD1619B_FUNC(i2c4), + RTD1619B_FUNC(i2c5), + RTD1619B_FUNC(pwm0), + RTD1619B_FUNC(pwm1), + RTD1619B_FUNC(pwm2), + RTD1619B_FUNC(pwm3), + RTD1619B_FUNC(etn_led), + RTD1619B_FUNC(etn_phy), + RTD1619B_FUNC(etn_clk), + RTD1619B_FUNC(sc0), + RTD1619B_FUNC(vfd), + RTD1619B_FUNC(gspi_loc0), + RTD1619B_FUNC(iso_gspi_loc0), + RTD1619B_FUNC(pcie1), + RTD1619B_FUNC(pcie2), + RTD1619B_FUNC(sd), + RTD1619B_FUNC(sdio_loc0), + RTD1619B_FUNC(sdio_loc1), + RTD1619B_FUNC(hi), + RTD1619B_FUNC(hi_m), + RTD1619B_FUNC(dc_fan), + RTD1619B_FUNC(pll_test_loc0), + RTD1619B_FUNC(pll_test_loc1), + RTD1619B_FUNC(usb_cc1), + RTD1619B_FUNC(usb_cc2), + RTD1619B_FUNC(ir_rx), + RTD1619B_FUNC(tdm_ai_loc0), + RTD1619B_FUNC(tdm_ai_loc1), + RTD1619B_FUNC(dmic_loc0), + RTD1619B_FUNC(dmic_loc1), + RTD1619B_FUNC(ai_loc0), + RTD1619B_FUNC(ai_loc1), + RTD1619B_FUNC(tp0), + RTD1619B_FUNC(tp1), + RTD1619B_FUNC(ao), + RTD1619B_FUNC(uart2_disable), + RTD1619B_FUNC(gspi_disable), + RTD1619B_FUNC(sdio_disable), + RTD1619B_FUNC(hi_loc_disable), + RTD1619B_FUNC(hi_loc0), + RTD1619B_FUNC(hi_width_disable), + RTD1619B_FUNC(hi_width_1bit), + RTD1619B_FUNC(vtc_i2si_loc0), + RTD1619B_FUNC(vtc_tdm_loc0), + RTD1619B_FUNC(vtc_dmic_loc0), + RTD1619B_FUNC(vtc_i2si_loc1), + RTD1619B_FUNC(vtc_tdm_loc1), + RTD1619B_FUNC(vtc_dmic_loc1), + RTD1619B_FUNC(vtc_i2so), + RTD1619B_FUNC(ve3_ejtag_loc0), + RTD1619B_FUNC(aucpu0_ejtag_loc0), + RTD1619B_FUNC(aucpu1_ejtag_loc0), + RTD1619B_FUNC(ve3_ejtag_loc1), + RTD1619B_FUNC(aucpu0_ejtag_loc1), + RTD1619B_FUNC(aucpu1_ejtag_loc1), + RTD1619B_FUNC(ve3_ejtag_loc2), + RTD1619B_FUNC(aucpu0_ejtag_loc2), + RTD1619B_FUNC(aucpu1_ejtag_loc2), + RTD1619B_FUNC(scpu_ejtag_loc0), + RTD1619B_FUNC(acpu_ejtag_loc0), + RTD1619B_FUNC(vcpu_ejtag_loc0), + RTD1619B_FUNC(scpu_ejtag_loc1), + RTD1619B_FUNC(acpu_ejtag_loc1), + RTD1619B_FUNC(vcpu_ejtag_loc1), + RTD1619B_FUNC(scpu_ejtag_loc2), + RTD1619B_FUNC(acpu_ejtag_loc2), + RTD1619B_FUNC(vcpu_ejtag_loc2), + RTD1619B_FUNC(ve3_ejtag_disable), + RTD1619B_FUNC(aucpu0_ejtag_disable), + RTD1619B_FUNC(aucpu1_ejtag_disable), + RTD1619B_FUNC(acpu_ejtag_disable), + RTD1619B_FUNC(vcpu_ejtag_disable), + RTD1619B_FUNC(scpu_ejtag_disable), + RTD1619B_FUNC(iso_gspi_disable), + RTD1619B_FUNC(sf_disable), + RTD1619B_FUNC(sf_enable), + RTD1619B_FUNC(arm_trace_debug_disable), + RTD1619B_FUNC(arm_trace_debug_enable), + RTD1619B_FUNC(pwm_normal), + RTD1619B_FUNC(pwm_open_drain), + RTD1619B_FUNC(standby_dbg), + RTD1619B_FUNC(test_loop_dis), +}; + +#undef RTD1619B_FUNC + +static const struct rtd_pin_desc rtd1619b_iso_muxes[] = { + [RTD1619B_ISO_EMMC_RST_N] = RTK_PIN_MUX(emmc_rst_n, 0x0, GENMASK(1, 0), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "nf"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 0), "emmc")), + [RTD1619B_ISO_EMMC_DD_SB] = RTK_PIN_MUX(emmc_dd_sb, 0x0, GENMASK(3, 2), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 2), "emmc")), + [RTD1619B_ISO_EMMC_CLK] = RTK_PIN_MUX(emmc_clk, 0x0, GENMASK(5, 4), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 4), "nf"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 4), "emmc")), + [RTD1619B_ISO_EMMC_CMD] = RTK_PIN_MUX(emmc_cmd, 0x0, GENMASK(7, 6), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 6), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 6), "nf"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 6), "emmc")), + [RTD1619B_ISO_EMMC_DATA_0] = RTK_PIN_MUX(emmc_data_0, 0x0, GENMASK(9, 8), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 8), "nf"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 8), "emmc"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 8), "nf_spi")), + [RTD1619B_ISO_EMMC_DATA_1] = RTK_PIN_MUX(emmc_data_1, 0x0, GENMASK(11, 10), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 10), "nf"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 10), "emmc"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 10), "nf_spi")), + [RTD1619B_ISO_EMMC_DATA_2] = RTK_PIN_MUX(emmc_data_2, 0x0, GENMASK(13, 12), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 12), "nf"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 12), "emmc"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 12), "nf_spi")), + [RTD1619B_ISO_EMMC_DATA_3] = RTK_PIN_MUX(emmc_data_3, 0x0, GENMASK(15, 14), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 14), "nf"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 14), "emmc"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 14), "nf_spi")), + [RTD1619B_ISO_EMMC_DATA_4] = RTK_PIN_MUX(emmc_data_4, 0x0, GENMASK(17, 16), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 16), "nf"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 16), "emmc"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 16), "nf_spi")), + [RTD1619B_ISO_EMMC_DATA_5] = RTK_PIN_MUX(emmc_data_5, 0x0, GENMASK(19, 18), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 18), "nf"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 18), "emmc"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 18), "nf_spi")), + [RTD1619B_ISO_EMMC_DATA_6] = RTK_PIN_MUX(emmc_data_6, 0x0, GENMASK(21, 20), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 20), "nf"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 20), "emmc")), + [RTD1619B_ISO_EMMC_DATA_7] = RTK_PIN_MUX(emmc_data_7, 0x0, GENMASK(23, 22), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 22), "nf"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 22), "emmc")), + [RTD1619B_ISO_SPI_CE_N] = RTK_PIN_MUX(spi_ce_n, 0x0, GENMASK(25, 24), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 24), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 24), "nf"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 24), "spi"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 24), "pmic")), + [RTD1619B_ISO_SPI_SCK] = RTK_PIN_MUX(spi_sck, 0x0, GENMASK(27, 26), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 26), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 26), "nf"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 26), "spi")), + [RTD1619B_ISO_SPI_SO] = RTK_PIN_MUX(spi_so, 0x0, GENMASK(29, 28), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 28), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 28), "nf"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 28), "spi")), + [RTD1619B_ISO_SPI_SI] = RTK_PIN_MUX(spi_si, 0x0, GENMASK(31, 30), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 30), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 30), "nf"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 30), "spi")), + + [RTD1619B_ISO_GPIO_0] = RTK_PIN_MUX(gpio_0, 0x4, GENMASK(0, 0), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio")), + [RTD1619B_ISO_GPIO_1] = RTK_PIN_MUX(gpio_1, 0x4, GENMASK(3, 1), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 1), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 1), "emmc_spi"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 1), "spdif_coaxial")), + [RTD1619B_ISO_GPIO_2] = RTK_PIN_MUX(gpio_2, 0x4, GENMASK(7, 4), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 4), "standby_dbg"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 4), "emmc_spi"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 4), "sc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 4), "scpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x6, 4), "acpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x7, 4), "vcpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x8, 4), "ve3_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x9, 4), "aucpu0_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x10, 4), "aucpu1_ejtag_loc0")), + [RTD1619B_ISO_GPIO_3] = RTK_PIN_MUX(gpio_3, 0x4, GENMASK(11, 8), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 8), "standby_dbg"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 8), "emmc_spi"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 8), "sc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 8), "scpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x6, 8), "acpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x7, 8), "vcpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x8, 8), "ve3_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x9, 8), "aucpu0_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x10, 8), "aucpu1_ejtag_loc0")), + [RTD1619B_ISO_GPIO_4] = RTK_PIN_MUX(gpio_4, 0x4, GENMASK(15, 12), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 12), "emmc_spi"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 12), "sc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 12), "scpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x6, 12), "acpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x7, 12), "vcpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x8, 12), "ve3_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x9, 12), "aucpu0_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x10, 12), "aucpu1_ejtag_loc0")), + [RTD1619B_ISO_GPIO_5] = RTK_PIN_MUX(gpio_5, 0x4, GENMASK(19, 16), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 16), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 16), "emmc_spi"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 16), "sc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 16), "scpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x6, 16), "acpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x7, 16), "vcpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x8, 16), "ve3_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x9, 16), "aucpu0_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x10, 16), "aucpu1_ejtag_loc0")), + [RTD1619B_ISO_GPIO_6] = RTK_PIN_MUX(gpio_6, 0x4, GENMASK(23, 20), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 20), "emmc_spi"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 20), "spdif_optical_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 20), "scpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x6, 20), "acpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x7, 20), "vcpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x8, 20), "ve3_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x9, 20), "aucpu0_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x10, 20), "aucpu1_ejtag_loc0")), + [RTD1619B_ISO_GPIO_7] = RTK_PIN_MUX(gpio_7, 0x4, GENMASK(24, 24), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 24), "gpio")), + [RTD1619B_ISO_GPIO_8] = RTK_PIN_MUX(gpio_8, 0x4, GENMASK(27, 25), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 25), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 25), "uart1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 25), "gspi_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 25), "iso_gspi_loc1")), + [RTD1619B_ISO_GPIO_9] = RTK_PIN_MUX(gpio_9, 0x4, GENMASK(30, 28), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 28), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 28), "uart1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 28), "gspi_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 28), "iso_gspi_loc1")), + [RTD1619B_ISO_GPIO_10] = RTK_PIN_MUX(gpio_10, 0x8, GENMASK(2, 0), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "uart1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 0), "gspi_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 0), "iso_gspi_loc1")), + [RTD1619B_ISO_GPIO_11] = RTK_PIN_MUX(gpio_11, 0x8, GENMASK(5, 3), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 3), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 3), "uart1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 3), "gspi_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 3), "iso_gspi_loc1")), + + [RTD1619B_ISO_GPIO_12] = RTK_PIN_MUX(gpio_12, 0x8, GENMASK(6, 6), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 6), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 6), "i2c0")), + [RTD1619B_ISO_GPIO_13] = RTK_PIN_MUX(gpio_13, 0x8, GENMASK(7, 7), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 7), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 7), "i2c0")), + [RTD1619B_ISO_GPIO_14] = RTK_PIN_MUX(gpio_14, 0x8, GENMASK(10, 8), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 8), "etn_led"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 8), "etn_phy"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 8), "etn_clk")), + [RTD1619B_ISO_GPIO_15] = RTK_PIN_MUX(gpio_15, 0x8, GENMASK(12, 11), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 11), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 11), "etn_led"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 11), "etn_phy")), + [RTD1619B_ISO_GPIO_16] = RTK_PIN_MUX(gpio_16, 0x8, GENMASK(13, 13), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 13), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 13), "i2c1")), + [RTD1619B_ISO_GPIO_17] = RTK_PIN_MUX(gpio_17, 0x8, GENMASK(14, 14), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 14), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 14), "i2c1")), + [RTD1619B_ISO_GPIO_18] = RTK_PIN_MUX(gpio_18, 0x8, GENMASK(17, 15), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 15), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 15), "uart2_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 15), "sc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 15), "gspi_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 15), "iso_gspi_loc0")), + [RTD1619B_ISO_GPIO_19] = RTK_PIN_MUX(gpio_19, 0x8, GENMASK(20, 18), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 18), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 18), "uart2_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 18), "sc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 18), "gspi_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 18), "iso_gspi_loc0")), + [RTD1619B_ISO_GPIO_20] = RTK_PIN_MUX(gpio_20, 0x8, GENMASK(23, 21), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 21), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 21), "uart2_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 21), "pwm0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 21), "gspi_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 21), "sc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 21), "iso_gspi_loc0")), + [RTD1619B_ISO_GPIO_21] = RTK_PIN_MUX(gpio_21, 0x8, GENMASK(26, 24), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 24), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 24), "pwm1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 24), "spdif_optical_loc1")), + [RTD1619B_ISO_GPIO_22] = RTK_PIN_MUX(gpio_22, 0x8, GENMASK(28, 27), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 27), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 27), "pwm2")), + [RTD1619B_ISO_GPIO_23] = RTK_PIN_MUX(gpio_23, 0x8, GENMASK(30, 29), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 29), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 29), "etn_led"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 29), "pwm3")), + [RTD1619B_ISO_USB_CC2] = RTK_PIN_MUX(usb_cc2, 0x8, GENMASK(31, 31), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 31), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 31), "usb_cc2")), + [RTD1619B_ISO_GPIO_25] = RTK_PIN_MUX(gpio_25, 0xc, GENMASK(1, 0), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "uart2_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 0), "pcie1")), + [RTD1619B_ISO_GPIO_26] = RTK_PIN_MUX(gpio_26, 0xc, GENMASK(3, 2), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 2), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 2), "uart2_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 2), "vfd"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 2), "pwm0")), + [RTD1619B_ISO_GPIO_27] = RTK_PIN_MUX(gpio_27, 0xc, GENMASK(5, 4), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 4), "uart2_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 4), "vfd"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 4), "pwm1")), + + [RTD1619B_ISO_GPIO_28] = RTK_PIN_MUX(gpio_28, 0xc, GENMASK(7, 6), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 6), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 6), "uart2_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 6), "vfd"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 6), "pwm2")), + [RTD1619B_ISO_GPIO_29] = RTK_PIN_MUX(gpio_29, 0xc, GENMASK(8, 8), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 8), "i2c5")), + [RTD1619B_ISO_GPIO_30] = RTK_PIN_MUX(gpio_30, 0xc, GENMASK(9, 9), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 9), "gpio")), + [RTD1619B_ISO_GPIO_31] = RTK_PIN_MUX(gpio_31, 0xc, GENMASK(12, 10), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 10), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 10), "uart2_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 10), "sc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 10), "gspi_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 10), "iso_gspi_loc0")), + [RTD1619B_ISO_GPIO_32] = RTK_PIN_MUX(gpio_32, 0xc, GENMASK(17, 13), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 13), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 13), "sd"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 13), "sdio_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 13), "dmic_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 13), "ai_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 13), "scpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x6, 13), "acpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x7, 13), "vcpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x11, 13), "vtc_i2si_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x14, 13), "ve3_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x15, 13), "aucpu0_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x16, 13), "aucpu1_ejtag_loc1")), + [RTD1619B_ISO_GPIO_33] = RTK_PIN_MUX(gpio_33, 0xc, GENMASK(22, 18), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 18), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 18), "sd"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 18), "sdio_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 18), "dmic_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 18), "ai_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 18), "scpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x6, 18), "acpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x7, 18), "vcpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x14, 18), "ve3_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x15, 18), "aucpu0_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x16, 18), "aucpu1_ejtag_loc1")), + [RTD1619B_ISO_GPIO_34] = RTK_PIN_MUX(gpio_34, 0xc, GENMASK(25, 23), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 23), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 23), "sd"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 23), "dmic_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 23), "ai_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 23), "i2c4")), + [RTD1619B_ISO_GPIO_35] = RTK_PIN_MUX(gpio_35, 0xc, GENMASK(28, 26), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 26), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 26), "sd"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 26), "dmic_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 26), "i2c4")), + [RTD1619B_ISO_HIF_DATA] = RTK_PIN_MUX(hif_data, 0x10, GENMASK(4, 0), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "sd"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 0), "sdio_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 0), "dmic_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 0), "tdm_ai_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 0), "scpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x6, 0), "acpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x7, 0), "vcpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x8, 0), "ai_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x9, 0), "hi"), + RTK_PIN_FUNC(SHIFT_LEFT(0x10, 0), "hi_m"), + RTK_PIN_FUNC(SHIFT_LEFT(0x11, 0), "vtc_i2si_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x12, 0), "vtc_tdm_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x13, 0), "vtc_dmic_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x14, 0), "ve3_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x15, 0), "aucpu0_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x16, 0), "aucpu1_ejtag_loc1")), + [RTD1619B_ISO_HIF_EN] = RTK_PIN_MUX(hif_en, 0x10, GENMASK(9, 5), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 5), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 5), "sd"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 5), "sdio_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 5), "dmic_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 5), "tdm_ai_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 5), "scpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x6, 5), "acpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x7, 5), "vcpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x8, 5), "ai_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x9, 5), "hi"), + RTK_PIN_FUNC(SHIFT_LEFT(0x10, 5), "hi_m"), + RTK_PIN_FUNC(SHIFT_LEFT(0x11, 5), "vtc_i2si_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x12, 5), "vtc_tdm_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x13, 5), "vtc_dmic_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x14, 5), "ve3_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x15, 5), "aucpu0_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x16, 5), "aucpu1_ejtag_loc1")), + [RTD1619B_ISO_HIF_RDY] = RTK_PIN_MUX(hif_rdy, 0x10, GENMASK(13, 10), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 10), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 10), "sd"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 10), "sdio_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 10), "dmic_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 10), "tdm_ai_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x8, 10), "ai_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x9, 10), "hi"), + RTK_PIN_FUNC(SHIFT_LEFT(0x10, 10), "hi_m"), + RTK_PIN_FUNC(SHIFT_LEFT(0x11, 10), "vtc_i2si_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x12, 10), "vtc_tdm_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x13, 10), "vtc_dmic_loc0")), + + [RTD1619B_ISO_HIF_CLK] = RTK_PIN_MUX(hif_clk, 0x10, GENMASK(18, 14), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 14), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 14), "sd"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 14), "sdio_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 14), "dmic_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 14), "tdm_ai_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 14), "scpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x6, 14), "acpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x7, 14), "vcpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x8, 14), "ai_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x9, 14), "hi"), + RTK_PIN_FUNC(SHIFT_LEFT(0x10, 14), "hi_m"), + RTK_PIN_FUNC(SHIFT_LEFT(0x11, 14), "vtc_i2si_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x12, 14), "vtc_tdm_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x13, 14), "vtc_dmic_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x14, 14), "ve3_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x15, 14), "aucpu0_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x16, 14), "aucpu1_ejtag_loc1")), + [RTD1619B_ISO_GPIO_40] = RTK_PIN_MUX(gpio_40, 0x10, GENMASK(20, 19), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 19), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 19), "sdio_loc1")), + [RTD1619B_ISO_GPIO_41] = RTK_PIN_MUX(gpio_41, 0x10, GENMASK(22, 21), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 21), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 21), "sdio_loc1")), + [RTD1619B_ISO_GPIO_42] = RTK_PIN_MUX(gpio_42, 0x10, GENMASK(24, 23), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 23), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 23), "sdio_loc1")), + [RTD1619B_ISO_GPIO_43] = RTK_PIN_MUX(gpio_43, 0x10, GENMASK(26, 25), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 25), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 25), "sdio_loc1")), + [RTD1619B_ISO_GPIO_44] = RTK_PIN_MUX(gpio_44, 0x10, GENMASK(28, 27), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 27), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 27), "sdio_loc1")), + [RTD1619B_ISO_GPIO_45] = RTK_PIN_MUX(gpio_45, 0x10, GENMASK(30, 29), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 29), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 29), "sdio_loc1")), + [RTD1619B_ISO_GPIO_46] = RTK_PIN_MUX(gpio_46, 0x10, GENMASK(31, 31), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 31), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 31), "i2c5")), + [RTD1619B_ISO_GPIO_47] = RTK_PIN_MUX(gpio_47, 0x14, GENMASK(1, 0), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 0), "dc_fan"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 0), "pwm3")), + [RTD1619B_ISO_GPIO_48] = RTK_PIN_MUX(gpio_48, 0x14, GENMASK(2, 2), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 2), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 2), "pll_test_loc1")), + [RTD1619B_ISO_GPIO_49] = RTK_PIN_MUX(gpio_49, 0x14, GENMASK(3, 3), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 3), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 3), "pll_test_loc1")), + [RTD1619B_ISO_GPIO_50] = RTK_PIN_MUX(gpio_50, 0x14, GENMASK(5, 4), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 4), "spdif"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 4), "test_loop_dis")), + [RTD1619B_ISO_USB_CC1] = RTK_PIN_MUX(usb_cc1, 0x14, GENMASK(6, 6), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 6), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 6), "usb_cc1")), + [RTD1619B_ISO_GPIO_52] = RTK_PIN_MUX(gpio_52, 0x14, GENMASK(8, 7), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 7), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 7), "pll_test_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 7), "pcie2")), + [RTD1619B_ISO_GPIO_53] = RTK_PIN_MUX(gpio_53, 0x14, GENMASK(9, 9), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 9), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 9), "pll_test_loc0")), + [RTD1619B_ISO_IR_RX] = RTK_PIN_MUX(ir_rx, 0x14, GENMASK(11, 10), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 10), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 10), "ir_rx"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 10), "standby_dbg")), + [RTD1619B_ISO_UR0_RX] = RTK_PIN_MUX(ur0_rx, 0x14, GENMASK(12, 12), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 12), "uart0")), + + [RTD1619B_ISO_UR0_TX] = RTK_PIN_MUX(ur0_tx, 0x14, GENMASK(13, 13), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 13), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 13), "uart0")), + [RTD1619B_ISO_GPIO_57] = RTK_PIN_MUX(gpio_57, 0x14, GENMASK(17, 14), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 14), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 14), "tdm_ai_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 14), "ai_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 14), "dmic_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x11, 14), "vtc_i2si_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x12, 14), "vtc_tdm_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x13, 14), "vtc_dmic_loc1")), + [RTD1619B_ISO_GPIO_58] = RTK_PIN_MUX(gpio_58, 0x14, GENMASK(21, 18), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 18), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 18), "tdm_ai_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 18), "ai_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 18), "dmic_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x11, 18), "vtc_i2si_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x12, 18), "vtc_tdm_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x13, 18), "vtc_dmic_loc1")), + [RTD1619B_ISO_GPIO_59] = RTK_PIN_MUX(gpio_59, 0x14, GENMASK(25, 22), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 22), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 22), "tdm_ai_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 22), "ai_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 22), "dmic_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x11, 22), "vtc_i2si_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x12, 22), "vtc_tdm_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x13, 22), "vtc_dmic_loc1")), + [RTD1619B_ISO_GPIO_60] = RTK_PIN_MUX(gpio_60, 0x14, GENMASK(29, 26), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 26), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 26), "tdm_ai_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 26), "ai_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 26), "dmic_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x11, 26), "vtc_i2si_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x12, 26), "vtc_tdm_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x13, 26), "vtc_dmic_loc1")), + [RTD1619B_ISO_GPIO_61] = RTK_PIN_MUX(gpio_61, 0x18, GENMASK(3, 0), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "ai_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 0), "dmic_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x11, 0), "vtc_i2si_loc1")), + [RTD1619B_ISO_GPIO_62] = RTK_PIN_MUX(gpio_62, 0x18, GENMASK(5, 4), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 4), "ai_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 4), "dmic_loc0")), + [RTD1619B_ISO_GPIO_63] = RTK_PIN_MUX(gpio_63, 0x18, GENMASK(7, 6), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 6), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 6), "ai_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 6), "i2c3"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 6), "dmic_loc0")), + [RTD1619B_ISO_GPIO_64] = RTK_PIN_MUX(gpio_64, 0x18, GENMASK(9, 8), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 8), "i2c3"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 8), "dmic_loc0")), + [RTD1619B_ISO_GPIO_65] = RTK_PIN_MUX(gpio_65, 0x18, GENMASK(10, 10), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 10), "gpio")), + [RTD1619B_ISO_GPIO_66] = RTK_PIN_MUX(gpio_66, 0x18, GENMASK(14, 11), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 11), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 11), "tp0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 11), "ao"), + RTK_PIN_FUNC(SHIFT_LEFT(0x11, 11), "vtc_i2so")), + [RTD1619B_ISO_GPIO_67] = RTK_PIN_MUX(gpio_67, 0x18, GENMASK(18, 15), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 15), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 15), "tp0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 15), "ao"), + RTK_PIN_FUNC(SHIFT_LEFT(0x11, 15), "vtc_i2so")), + [RTD1619B_ISO_GPIO_68] = RTK_PIN_MUX(gpio_68, 0x18, GENMASK(22, 19), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 19), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 19), "tp0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 19), "ao"), + RTK_PIN_FUNC(SHIFT_LEFT(0x11, 19), "vtc_i2so")), + [RTD1619B_ISO_GPIO_69] = RTK_PIN_MUX(gpio_69, 0x18, GENMASK(26, 23), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 23), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 23), "tp0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 23), "tp1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 23), "ao"), + RTK_PIN_FUNC(SHIFT_LEFT(0x11, 23), "vtc_i2so")), + + [RTD1619B_ISO_GPIO_70] = RTK_PIN_MUX(gpio_70, 0x18, GENMASK(29, 27), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 27), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 27), "tp0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 27), "tp1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 27), "ao")), + [RTD1619B_ISO_GPIO_71] = RTK_PIN_MUX(gpio_71, 0x1c, GENMASK(2, 0), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 0), "tp0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 0), "tp1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 0), "ao"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 0), "scpu_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0x6, 0), "acpu_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0x7, 0), "vcpu_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0x8, 0), "ve3_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0x9, 0), "aucpu0_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0x10, 0), "aucpu1_ejtag_loc2")), + [RTD1619B_ISO_GPIO_72] = RTK_PIN_MUX(gpio_72, 0x1c, GENMASK(6, 3), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 3), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 3), "tp0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 3), "tp1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 3), "ao"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 3), "scpu_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0x6, 3), "acpu_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0x7, 3), "vcpu_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0x8, 3), "ve3_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0x9, 3), "aucpu0_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0x10, 3), "aucpu1_ejtag_loc2")), + [RTD1619B_ISO_GPIO_73] = RTK_PIN_MUX(gpio_73, 0x1c, GENMASK(10, 7), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 7), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 7), "tp0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 7), "scpu_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0x6, 7), "acpu_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0x7, 7), "vcpu_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0x8, 7), "ve3_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0x9, 7), "aucpu0_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0x10, 7), "aucpu1_ejtag_loc2")), + [RTD1619B_ISO_GPIO_74] = RTK_PIN_MUX(gpio_74, 0x1c, GENMASK(14, 11), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 11), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 11), "tp0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 11), "scpu_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0x6, 11), "acpu_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0x7, 11), "vcpu_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0x8, 11), "ve3_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0x9, 11), "aucpu0_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0x10, 11), "aucpu1_ejtag_loc2")), + [RTD1619B_ISO_GPIO_75] = RTK_PIN_MUX(gpio_75, 0x1c, GENMASK(18, 15), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 15), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 15), "tp0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 15), "scpu_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0x6, 15), "acpu_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0x7, 15), "vcpu_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0x8, 15), "ve3_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0x9, 15), "aucpu0_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0x10, 15), "aucpu1_ejtag_loc2")), + [RTD1619B_ISO_GPIO_76] = RTK_PIN_MUX(gpio_76, 0x1c, GENMASK(22, 19), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 19), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 19), "tp0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 19), "scpu_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0x6, 19), "acpu_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0x7, 19), "vcpu_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0x8, 19), "ve3_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0x9, 19), "aucpu0_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0x10, 19), "aucpu1_ejtag_loc2")), + + [RTD1619B_ISO_UR2_LOC] = RTK_PIN_MUX(ur2_loc, 0x120, GENMASK(1, 0), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "uart2_disable"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "uart2_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 0), "uart2_loc1")), + [RTD1619B_ISO_GSPI_LOC] = RTK_PIN_MUX(gspi_loc, 0x120, GENMASK(3, 2), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 2), "gspi_disable"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 2), "gspi_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 2), "gspi_loc1")), + [RTD1619B_ISO_SDIO_LOC] = RTK_PIN_MUX(sdio_loc, 0x120, GENMASK(5, 4), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "sdio_disable"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 4), "sdio_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 4), "sdio_loc1")), + [RTD1619B_ISO_HI_LOC] = RTK_PIN_MUX(hi_loc, 0x120, GENMASK(7, 6), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 6), "hi_loc_disable"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 6), "hi_loc0")), + [RTD1619B_ISO_HI_WIDTH] = RTK_PIN_MUX(hi_width, 0x120, GENMASK(9, 8), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "hi_width_disable"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 8), "hi_width_1bit")), + [RTD1619B_ISO_SF_EN] = RTK_PIN_MUX(sf_en, 0x120, GENMASK(11, 11), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 11), "sf_disable"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 11), "sf_enable")), + [RTD1619B_ISO_ARM_TRACE_DBG_EN] = RTK_PIN_MUX(arm_trace_dbg_en, 0x120, GENMASK(12, 12), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "arm_trace_debug_disable"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 12), "arm_trace_debug_enable")), + [RTD1619B_ISO_PWM_01_OPEN_DRAIN_EN_LOC0] = RTK_PIN_MUX(pwm_01_open_drain_en_loc0, 0x120, + GENMASK(13, 13), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 13), "pwm_normal"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 13), "pwm_open_drain")), + [RTD1619B_ISO_PWM_23_OPEN_DRAIN_EN_LOC0] = RTK_PIN_MUX(pwm_23_open_drain_en_loc0, 0x120, + GENMASK(14, 14), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 14), "pwm_normal"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 14), "pwm_open_drain")), + [RTD1619B_ISO_PWM_01_OPEN_DRAIN_EN_LOC1] = RTK_PIN_MUX(pwm_01_open_drain_en_loc1, 0x120, + GENMASK(15, 15), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 15), "pwm_normal"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 15), "pwm_open_drain")), + [RTD1619B_ISO_PWM_23_OPEN_DRAIN_EN_LOC1] = RTK_PIN_MUX(pwm_23_open_drain_en_loc1, 0x120, + GENMASK(16, 16), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 16), "pwm_normal"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 16), "pwm_open_drain")), + [RTD1619B_ISO_EJTAG_ACPU_LOC] = RTK_PIN_MUX(ejtag_acpu_loc, 0x120, GENMASK(19, 17), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 17), "acpu_ejtag_disable"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 17), "acpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 17), "acpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 17), "acpu_ejtag_loc2")), + [RTD1619B_ISO_EJTAG_VCPU_LOC] = RTK_PIN_MUX(ejtag_vcpu_loc, 0x120, GENMASK(22, 20), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "vcpu_ejtag_disable"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 20), "vcpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 20), "vcpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 20), "vcpu_ejtag_loc2")), + [RTD1619B_ISO_EJTAG_SCPU_LOC] = RTK_PIN_MUX(ejtag_scpu_loc, 0x120, GENMASK(25, 23), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 23), "scpu_ejtag_disable"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 23), "scpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 23), "scpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 23), "scpu_ejtag_loc2")), + [RTD1619B_ISO_DMIC_LOC] = RTK_PIN_MUX(dmic_loc, 0x120, GENMASK(27, 26), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 26), "dmic_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 26), "dmic_loc1")), + [RTD1619B_ISO_ISO_GSPI_LOC] = RTK_PIN_MUX(iso_gspi_loc, 0x120, GENMASK(29, 28), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 28), "iso_gspi_disable"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 28), "iso_gspi_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 28), "iso_gspi_loc1")), + [RTD1619B_ISO_EJTAG_VE3_LOC] = RTK_PIN_MUX(ejtag_ve3_loc, 0x124, GENMASK(20, 18), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 18), "ve3_ejtag_disable"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 18), "ve3_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 18), "ve3_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 18), "ve3_ejtag_loc2")), + [RTD1619B_ISO_EJTAG_AUCPU1_LOC] = RTK_PIN_MUX(ejtag_aucpu1_loc, 0x124, GENMASK(23, 21), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 21), "aucpu1_ejtag_disable"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 21), "aucpu1_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 21), "aucpu1_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 21), "aucpu1_ejtag_loc2")), + [RTD1619B_ISO_EJTAG_AUCPU0_LOC] = RTK_PIN_MUX(ejtag_aucpu0_loc, 0x124, GENMASK(26, 24), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 24), "aucpu0_ejtag_disable"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 24), "aucpu0_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 24), "aucpu0_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 24), "aucpu0_ejtag_loc2")), +}; + +static const struct rtd_pin_config_desc rtd1619b_iso_configs[] = { + [RTD1619B_ISO_GPIO_17] = RTK_PIN_CONFIG(gpio_17, 0x20, 0, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1619B_ISO_GPIO_19] = RTK_PIN_CONFIG(gpio_19, 0x20, 5, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1619B_ISO_GPIO_50] = RTK_PIN_CONFIG(gpio_50, 0x20, 10, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1619B_ISO_GPIO_21] = RTK_PIN_CONFIG(gpio_21, 0x20, 15, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1619B_ISO_GPIO_66] = RTK_PIN_CONFIG(gpio_66, 0x20, 20, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1619B_ISO_GPIO_67] = RTK_PIN_CONFIG(gpio_67, 0x20, 25, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1619B_ISO_GPIO_68] = RTK_PIN_CONFIG(gpio_68, 0x24, 0, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1619B_ISO_GPIO_69] = RTK_PIN_CONFIG(gpio_69, 0x24, 5, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1619B_ISO_GPIO_70] = RTK_PIN_CONFIG(gpio_70, 0x24, 10, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1619B_ISO_GPIO_71] = RTK_PIN_CONFIG(gpio_71, 0x24, 15, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1619B_ISO_GPIO_72] = RTK_PIN_CONFIG(gpio_72, 0x24, 20, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1619B_ISO_GPIO_73] = RTK_PIN_CONFIG(gpio_73, 0x24, 25, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1619B_ISO_GPIO_74] = RTK_PIN_CONFIG(gpio_74, 0x28, 0, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1619B_ISO_GPIO_75] = RTK_PIN_CONFIG(gpio_75, 0x28, 5, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1619B_ISO_GPIO_76] = RTK_PIN_CONFIG(gpio_76, 0x28, 10, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1619B_ISO_SPI_SI] = RTK_PIN_CONFIG(spi_si, 0x28, 15, 0, 1, 3, 2, 12, NA), + [RTD1619B_ISO_SPI_SCK] = RTK_PIN_CONFIG(spi_sck, 0x2c, 0, 0, 1, 3, 2, 12, NA), + [RTD1619B_ISO_SPI_CE_N] = RTK_PIN_CONFIG(spi_ce_n, 0x2c, 13, 0, 1, 3, 2, 12, NA), + [RTD1619B_ISO_SPI_SO] = RTK_PIN_CONFIG(spi_so, 0x2c, 26, 0, 1, 3, 2, 12, NA), + [RTD1619B_ISO_EMMC_CLK] = RTK_PIN_CONFIG(emmc_clk, 0x30, 7, 0, 1, 3, 2, 12, NA), + [RTD1619B_ISO_EMMC_CMD] = RTK_PIN_CONFIG(emmc_cmd, 0x34, 0, 0, 1, 3, 2, 13, NA), + [RTD1619B_ISO_EMMC_RST_N] = RTK_PIN_CONFIG(emmc_rst_n, 0x34, 14, 0, 1, 3, 2, 12, NA), + [RTD1619B_ISO_EMMC_DD_SB] = RTK_PIN_CONFIG(emmc_dd_sb, 0x34, 27, 0, 1, 3, 2, 12, NA), + [RTD1619B_ISO_EMMC_DATA_5] = RTK_PIN_CONFIG(emmc_data_5, 0x38, 8, 0, 1, 3, 2, 12, NA), + [RTD1619B_ISO_EMMC_DATA_3] = RTK_PIN_CONFIG(emmc_data_3, 0x3c, 0, 0, 1, 3, 2, 12, NA), + [RTD1619B_ISO_EMMC_DATA_4] = RTK_PIN_CONFIG(emmc_data_4, 0x3c, 13, 0, 1, 3, 2, 12, NA), + [RTD1619B_ISO_EMMC_DATA_0] = RTK_PIN_CONFIG(emmc_data_0, 0x3c, 26, 0, 1, 3, 2, 12, NA), + [RTD1619B_ISO_EMMC_DATA_1] = RTK_PIN_CONFIG(emmc_data_1, 0x40, 7, 0, 1, 3, 2, 12, NA), + [RTD1619B_ISO_EMMC_DATA_2] = RTK_PIN_CONFIG(emmc_data_2, 0x44, 0, 0, 1, 3, 2, 12, NA), + [RTD1619B_ISO_EMMC_DATA_7] = RTK_PIN_CONFIG(emmc_data_7, 0x44, 13, 0, 1, 3, 2, 12, NA), + [RTD1619B_ISO_EMMC_DATA_6] = RTK_PIN_CONFIG(emmc_data_6, 0x44, 26, 0, 1, 3, 2, 12, NA), + [RTD1619B_ISO_USB_CC1] = RTK_PIN_CONFIG(usb_cc1, 0x48, 7, NA, NA, 0, 1, 9, PADDRI_4_8), + [RTD1619B_ISO_USB_CC2] = RTK_PIN_CONFIG(usb_cc2, 0x48, 10, NA, NA, 0, 1, 9, PADDRI_4_8), + [RTD1619B_ISO_GPIO_26] = RTK_PIN_CONFIG(gpio_26, 0x48, 13, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1619B_ISO_GPIO_27] = RTK_PIN_CONFIG(gpio_27, 0x48, 18, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1619B_ISO_GPIO_28] = RTK_PIN_CONFIG(gpio_28, 0x48, 23, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1619B_ISO_GPIO_29] = RTK_PIN_CONFIG(gpio_29, 0x4c, 0, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1619B_ISO_GPIO_46] = RTK_PIN_CONFIG(gpio_46, 0x4c, 5, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1619B_ISO_GPIO_48] = RTK_PIN_CONFIG(gpio_48, 0x4c, 10, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1619B_ISO_GPIO_49] = RTK_PIN_CONFIG(gpio_49, 0x4c, 15, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1619B_ISO_GPIO_53] = RTK_PIN_CONFIG(gpio_53, 0x4c, 20, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1619B_ISO_GPIO_65] = RTK_PIN_CONFIG(gpio_65, 0x4c, 25, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1619B_ISO_GPIO_14] = RTK_PIN_CONFIG(gpio_14, 0x50, 0, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1619B_ISO_GPIO_15] = RTK_PIN_CONFIG(gpio_15, 0x50, 5, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1619B_ISO_GPIO_23] = RTK_PIN_CONFIG(gpio_23, 0x50, 10, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1619B_ISO_IR_RX] = RTK_PIN_CONFIG(ir_rx, 0x50, 20, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1619B_ISO_GPIO_57] = RTK_PIN_CONFIG(gpio_57, 0x50, 25, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1619B_ISO_GPIO_58] = RTK_PIN_CONFIG(gpio_58, 0x50, 30, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1619B_ISO_GPIO_59] = RTK_PIN_CONFIG(gpio_59, 0x54, 3, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1619B_ISO_GPIO_60] = RTK_PIN_CONFIG(gpio_60, 0x54, 8, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1619B_ISO_GPIO_61] = RTK_PIN_CONFIG(gpio_61, 0x54, 13, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1619B_ISO_GPIO_62] = RTK_PIN_CONFIG(gpio_62, 0x54, 18, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1619B_ISO_GPIO_63] = RTK_PIN_CONFIG(gpio_63, 0x54, 23, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1619B_ISO_GPIO_64] = RTK_PIN_CONFIG(gpio_64, 0x58, 0, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1619B_ISO_UR0_TX] = RTK_PIN_CONFIG(ur0_tx, 0x58, 5, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1619B_ISO_UR0_RX] = RTK_PIN_CONFIG(ur0_rx, 0x58, 13, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1619B_ISO_GPIO_12] = RTK_PIN_CONFIG(gpio_12, 0x58, 18, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1619B_ISO_GPIO_13] = RTK_PIN_CONFIG(gpio_13, 0x58, 23, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1619B_ISO_GPIO_30] = RTK_PIN_CONFIG(gpio_30, 0x58, 28, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1619B_ISO_GPIO_7] = RTK_PIN_CONFIG(gpio_7, 0x5c, 1, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1619B_ISO_GPIO_16] = RTK_PIN_CONFIG(gpio_16, 0x5c, 6, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1619B_ISO_GPIO_18] = RTK_PIN_CONFIG(gpio_18, 0x5c, 11, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1619B_ISO_GPIO_20] = RTK_PIN_CONFIG(gpio_20, 0x5c, 16, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1619B_ISO_GPIO_22] = RTK_PIN_CONFIG(gpio_22, 0x5c, 21, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1619B_ISO_GPIO_31] = RTK_PIN_CONFIG(gpio_31, 0x5c, 26, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1619B_ISO_GPIO_47] = RTK_PIN_CONFIG(gpio_47, 0x60, 12, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1619B_ISO_GPIO_25] = RTK_PIN_CONFIG(gpio_25, 0x60, 17, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1619B_ISO_GPIO_6] = RTK_PIN_CONFIG(gpio_6, 0x60, 22, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1619B_ISO_GPIO_5] = RTK_PIN_CONFIG(gpio_5, 0x60, 27, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1619B_ISO_GPIO_4] = RTK_PIN_CONFIG(gpio_4, 0x64, 0, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1619B_ISO_GPIO_3] = RTK_PIN_CONFIG(gpio_3, 0x64, 5, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1619B_ISO_GPIO_2] = RTK_PIN_CONFIG(gpio_2, 0x64, 10, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1619B_ISO_GPIO_1] = RTK_PIN_CONFIG(gpio_1, 0x64, 15, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1619B_ISO_GPIO_0] = RTK_PIN_CONFIG(gpio_0, 0x64, 20, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1619B_ISO_GPIO_52] = RTK_PIN_CONFIG(gpio_52, 0x64, 25, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1619B_ISO_GPIO_35] = RTK_PIN_CONFIG(gpio_35, 0x68, 0, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1619B_ISO_GPIO_34] = RTK_PIN_CONFIG(gpio_34, 0x68, 5, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1619B_ISO_GPIO_40] = RTK_PIN_CONFIG(gpio_40, 0x68, 10, 0, 1, 3, 2, 12, NA), + [RTD1619B_ISO_GPIO_41] = RTK_PIN_CONFIG(gpio_41, 0x6c, 0, 0, 1, 3, 2, 12, NA), + [RTD1619B_ISO_GPIO_42] = RTK_PIN_CONFIG(gpio_42, 0x6c, 13, 0, 1, 3, 2, 12, NA), + [RTD1619B_ISO_GPIO_43] = RTK_PIN_CONFIG(gpio_43, 0x70, 0, 0, 1, 3, 2, 12, NA), + [RTD1619B_ISO_GPIO_44] = RTK_PIN_CONFIG(gpio_44, 0x70, 13, 0, 1, 3, 2, 12, NA), + [RTD1619B_ISO_GPIO_45] = RTK_PIN_CONFIG(gpio_45, 0x70, 26, 0, 1, 3, 2, 12, NA), + [RTD1619B_ISO_GPIO_8] = RTK_PIN_CONFIG(gpio_8, 0x74, 7, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1619B_ISO_GPIO_9] = RTK_PIN_CONFIG(gpio_9, 0x74, 12, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1619B_ISO_GPIO_10] = RTK_PIN_CONFIG(gpio_10, 0x74, 17, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1619B_ISO_GPIO_11] = RTK_PIN_CONFIG(gpio_11, 0x74, 22, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1619B_ISO_HIF_RDY] = RTK_PIN_CONFIG(hif_rdy, 0x78, 0, 0, 1, 3, 2, 12, NA), + [RTD1619B_ISO_HIF_CLK] = RTK_PIN_CONFIG(hif_clk, 0x78, 13, 0, 1, 3, 2, 12, NA), + [RTD1619B_ISO_GPIO_32] = RTK_PIN_CONFIG(gpio_32, 0x78, 26, 0, 1, 3, 2, 12, NA), + [RTD1619B_ISO_GPIO_33] = RTK_PIN_CONFIG(gpio_33, 0x7c, 7, 0, 1, 3, 2, 12, NA), + [RTD1619B_ISO_HIF_DATA] = RTK_PIN_CONFIG(hif_data, 0x80, 0, 0, 1, 3, 2, 12, NA), + [RTD1619B_ISO_HIF_EN] = RTK_PIN_CONFIG(hif_en, 0x80, 13, 0, 1, 3, 2, 12, NA), +}; + +static const struct rtd_pin_sconfig_desc rtd1619b_iso_sconfigs[] = { + RTK_PIN_SCONFIG(spi_si, 0x28, 18, 3, 21, 3, 24, 3), + RTK_PIN_SCONFIG(spi_sck, 0x2c, 3, 3, 6, 3, 9, 3), + RTK_PIN_SCONFIG(spi_ce_n, 0x2c, 16, 3, 19, 3, 22, 3), + RTK_PIN_SCONFIG(spi_so, 0x2c, 29, 3, 32, 3, 35, 3), + RTK_PIN_SCONFIG(emmc_clk, 0x30, 10, 3, 13, 3, 16, 3), + RTK_PIN_SCONFIG(emmc_cmd, 0x34, 3, 3, 6, 3, 9, 3), + RTK_PIN_SCONFIG(emmc_rst_n, 0x34, 17, 3, 20, 3, 23, 3), + RTK_PIN_SCONFIG(emmc_dd_sb, 0x34, 30, 3, 33, 3, 36, 3), + RTK_PIN_SCONFIG(emmc_data_5, 0x38, 11, 3, 14, 3, 17, 3), + RTK_PIN_SCONFIG(emmc_data_3, 0x3c, 3, 3, 6, 3, 9, 3), + RTK_PIN_SCONFIG(emmc_data_4, 0x3c, 16, 3, 19, 3, 22, 3), + RTK_PIN_SCONFIG(emmc_data_0, 0x3c, 29, 3, 32, 3, 35, 3), + RTK_PIN_SCONFIG(emmc_data_1, 0x40, 10, 3, 13, 3, 16, 3), + RTK_PIN_SCONFIG(emmc_data_2, 0x44, 3, 3, 6, 3, 9, 3), + RTK_PIN_SCONFIG(emmc_data_7, 0x44, 16, 3, 19, 3, 22, 3), + RTK_PIN_SCONFIG(emmc_data_6, 0x44, 29, 3, 32, 3, 35, 3), + RTK_PIN_SCONFIG(gpio_40, 0x68, 13, 3, 16, 3, 19, 3), + RTK_PIN_SCONFIG(gpio_41, 0x6c, 3, 3, 6, 3, 9, 3), + RTK_PIN_SCONFIG(gpio_42, 0x6c, 16, 3, 19, 3, 22, 3), + RTK_PIN_SCONFIG(gpio_43, 0x70, 3, 3, 6, 3, 9, 3), + RTK_PIN_SCONFIG(gpio_44, 0x70, 16, 3, 19, 3, 22, 3), + RTK_PIN_SCONFIG(gpio_45, 0x70, 29, 3, 32, 3, 35, 3), + RTK_PIN_SCONFIG(hif_rdy, 0x78, 3, 3, 6, 3, 9, 3), + RTK_PIN_SCONFIG(hif_clk, 0x78, 16, 3, 19, 3, 22, 3), + RTK_PIN_SCONFIG(gpio_32, 0x78, 29, 3, 32, 3, 35, 3), + RTK_PIN_SCONFIG(gpio_33, 0x7c, 10, 3, 13, 3, 16, 3), + RTK_PIN_SCONFIG(hif_data, 0x80, 3, 3, 6, 3, 9, 3), + RTK_PIN_SCONFIG(hif_en, 0x80, 16, 3, 19, 3, 22, 3), +}; + +static const struct rtd_pinctrl_desc rtd1619b_iso_pinctrl_desc = { + .pins = rtd1619b_iso_pins, + .num_pins = ARRAY_SIZE(rtd1619b_iso_pins), + .groups = rtd1619b_pin_groups, + .num_groups = ARRAY_SIZE(rtd1619b_pin_groups), + .functions = rtd1619b_pin_functions, + .num_functions = ARRAY_SIZE(rtd1619b_pin_functions), + .muxes = rtd1619b_iso_muxes, + .num_muxes = ARRAY_SIZE(rtd1619b_iso_muxes), + .configs = rtd1619b_iso_configs, + .num_configs = ARRAY_SIZE(rtd1619b_iso_configs), + .sconfigs = rtd1619b_iso_sconfigs, + .num_sconfigs = ARRAY_SIZE(rtd1619b_iso_sconfigs), +}; + +static int rtd1619b_pinctrl_probe(struct platform_device *pdev) +{ + return rtd_pinctrl_probe(pdev, &rtd1619b_iso_pinctrl_desc); +} + +static const struct of_device_id rtd1619b_pinctrl_of_match[] = { + { .compatible = "realtek,rtd1619b-pinctrl", }, + {}, +}; + +static struct platform_driver rtd1619b_pinctrl_driver = { + .driver = { + .name = "rtd1619b-pinctrl", + .of_match_table = rtd1619b_pinctrl_of_match, + }, + .probe = rtd1619b_pinctrl_probe, +}; + +static int __init rtd1619b_pinctrl_init(void) +{ + return platform_driver_register(&rtd1619b_pinctrl_driver); +} +arch_initcall(rtd1619b_pinctrl_init); + +static void __exit rtd1619b_pinctrl_exit(void) +{ + platform_driver_unregister(&rtd1619b_pinctrl_driver); +} +module_exit(rtd1619b_pinctrl_exit); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Realtek Semiconductor Corporation"); +MODULE_DESCRIPTION("Realtek DHC SoC RTD1619B pinctrl driver"); |