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path: root/drivers/platform/x86/intel/pmc/core.c
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Diffstat (limited to 'drivers/platform/x86/intel/pmc/core.c')
-rw-r--r--drivers/platform/x86/intel/pmc/core.c994
1 files changed, 51 insertions, 943 deletions
diff --git a/drivers/platform/x86/intel/pmc/core.c b/drivers/platform/x86/intel/pmc/core.c
index 17ec5825d13d..f1d802f6ec3f 100644
--- a/drivers/platform/x86/intel/pmc/core.c
+++ b/drivers/platform/x86/intel/pmc/core.c
@@ -11,7 +11,6 @@
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
-#include <linux/acpi.h>
#include <linux/bitfield.h>
#include <linux/debugfs.h>
#include <linux/delay.h>
@@ -19,13 +18,9 @@
#include <linux/io.h>
#include <linux/module.h>
#include <linux/pci.h>
-#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/suspend.h>
-#include <linux/uaccess.h>
-#include <linux/uuid.h>
-#include <acpi/acpi_bus.h>
#include <asm/cpu_device_id.h>
#include <asm/intel-family.h>
#include <asm/msr.h>
@@ -33,11 +28,21 @@
#include "core.h"
-#define ACPI_S0IX_DSM_UUID "57a6512e-3979-4e9d-9708-ff13b2508972"
-#define ACPI_GET_LOW_MODE_REGISTERS 1
+/* Maximum number of modes supported by platfoms that has low power mode capability */
+const char *pmc_lpm_modes[] = {
+ "S0i2.0",
+ "S0i2.1",
+ "S0i2.2",
+ "S0i3.0",
+ "S0i3.1",
+ "S0i3.2",
+ "S0i3.3",
+ "S0i3.4",
+ NULL
+};
/* PKGC MSRs are common across Intel Core SoCs */
-static const struct pmc_bit_map msr_map[] = {
+const struct pmc_bit_map msr_map[] = {
{"Package C2", MSR_PKG_C2_RESIDENCY},
{"Package C3", MSR_PKG_C3_RESIDENCY},
{"Package C6", MSR_PKG_C6_RESIDENCY},
@@ -48,903 +53,6 @@ static const struct pmc_bit_map msr_map[] = {
{}
};
-static const struct pmc_bit_map spt_pll_map[] = {
- {"MIPI PLL", SPT_PMC_BIT_MPHY_CMN_LANE0},
- {"GEN2 USB2PCIE2 PLL", SPT_PMC_BIT_MPHY_CMN_LANE1},
- {"DMIPCIE3 PLL", SPT_PMC_BIT_MPHY_CMN_LANE2},
- {"SATA PLL", SPT_PMC_BIT_MPHY_CMN_LANE3},
- {}
-};
-
-static const struct pmc_bit_map spt_mphy_map[] = {
- {"MPHY CORE LANE 0", SPT_PMC_BIT_MPHY_LANE0},
- {"MPHY CORE LANE 1", SPT_PMC_BIT_MPHY_LANE1},
- {"MPHY CORE LANE 2", SPT_PMC_BIT_MPHY_LANE2},
- {"MPHY CORE LANE 3", SPT_PMC_BIT_MPHY_LANE3},
- {"MPHY CORE LANE 4", SPT_PMC_BIT_MPHY_LANE4},
- {"MPHY CORE LANE 5", SPT_PMC_BIT_MPHY_LANE5},
- {"MPHY CORE LANE 6", SPT_PMC_BIT_MPHY_LANE6},
- {"MPHY CORE LANE 7", SPT_PMC_BIT_MPHY_LANE7},
- {"MPHY CORE LANE 8", SPT_PMC_BIT_MPHY_LANE8},
- {"MPHY CORE LANE 9", SPT_PMC_BIT_MPHY_LANE9},
- {"MPHY CORE LANE 10", SPT_PMC_BIT_MPHY_LANE10},
- {"MPHY CORE LANE 11", SPT_PMC_BIT_MPHY_LANE11},
- {"MPHY CORE LANE 12", SPT_PMC_BIT_MPHY_LANE12},
- {"MPHY CORE LANE 13", SPT_PMC_BIT_MPHY_LANE13},
- {"MPHY CORE LANE 14", SPT_PMC_BIT_MPHY_LANE14},
- {"MPHY CORE LANE 15", SPT_PMC_BIT_MPHY_LANE15},
- {}
-};
-
-static const struct pmc_bit_map spt_pfear_map[] = {
- {"PMC", SPT_PMC_BIT_PMC},
- {"OPI-DMI", SPT_PMC_BIT_OPI},
- {"SPI / eSPI", SPT_PMC_BIT_SPI},
- {"XHCI", SPT_PMC_BIT_XHCI},
- {"SPA", SPT_PMC_BIT_SPA},
- {"SPB", SPT_PMC_BIT_SPB},
- {"SPC", SPT_PMC_BIT_SPC},
- {"GBE", SPT_PMC_BIT_GBE},
- {"SATA", SPT_PMC_BIT_SATA},
- {"HDA-PGD0", SPT_PMC_BIT_HDA_PGD0},
- {"HDA-PGD1", SPT_PMC_BIT_HDA_PGD1},
- {"HDA-PGD2", SPT_PMC_BIT_HDA_PGD2},
- {"HDA-PGD3", SPT_PMC_BIT_HDA_PGD3},
- {"RSVD", SPT_PMC_BIT_RSVD_0B},
- {"LPSS", SPT_PMC_BIT_LPSS},
- {"LPC", SPT_PMC_BIT_LPC},
- {"SMB", SPT_PMC_BIT_SMB},
- {"ISH", SPT_PMC_BIT_ISH},
- {"P2SB", SPT_PMC_BIT_P2SB},
- {"DFX", SPT_PMC_BIT_DFX},
- {"SCC", SPT_PMC_BIT_SCC},
- {"RSVD", SPT_PMC_BIT_RSVD_0C},
- {"FUSE", SPT_PMC_BIT_FUSE},
- {"CAMERA", SPT_PMC_BIT_CAMREA},
- {"RSVD", SPT_PMC_BIT_RSVD_0D},
- {"USB3-OTG", SPT_PMC_BIT_USB3_OTG},
- {"EXI", SPT_PMC_BIT_EXI},
- {"CSE", SPT_PMC_BIT_CSE},
- {"CSME_KVM", SPT_PMC_BIT_CSME_KVM},
- {"CSME_PMT", SPT_PMC_BIT_CSME_PMT},
- {"CSME_CLINK", SPT_PMC_BIT_CSME_CLINK},
- {"CSME_PTIO", SPT_PMC_BIT_CSME_PTIO},
- {"CSME_USBR", SPT_PMC_BIT_CSME_USBR},
- {"CSME_SUSRAM", SPT_PMC_BIT_CSME_SUSRAM},
- {"CSME_SMT", SPT_PMC_BIT_CSME_SMT},
- {"RSVD", SPT_PMC_BIT_RSVD_1A},
- {"CSME_SMS2", SPT_PMC_BIT_CSME_SMS2},
- {"CSME_SMS1", SPT_PMC_BIT_CSME_SMS1},
- {"CSME_RTC", SPT_PMC_BIT_CSME_RTC},
- {"CSME_PSF", SPT_PMC_BIT_CSME_PSF},
- {}
-};
-
-static const struct pmc_bit_map *ext_spt_pfear_map[] = {
- /*
- * Check intel_pmc_core_ids[] users of spt_reg_map for
- * a list of core SoCs using this.
- */
- spt_pfear_map,
- NULL
-};
-
-static const struct pmc_bit_map spt_ltr_show_map[] = {
- {"SOUTHPORT_A", SPT_PMC_LTR_SPA},
- {"SOUTHPORT_B", SPT_PMC_LTR_SPB},
- {"SATA", SPT_PMC_LTR_SATA},
- {"GIGABIT_ETHERNET", SPT_PMC_LTR_GBE},
- {"XHCI", SPT_PMC_LTR_XHCI},
- {"Reserved", SPT_PMC_LTR_RESERVED},
- {"ME", SPT_PMC_LTR_ME},
- /* EVA is Enterprise Value Add, doesn't really exist on PCH */
- {"EVA", SPT_PMC_LTR_EVA},
- {"SOUTHPORT_C", SPT_PMC_LTR_SPC},
- {"HD_AUDIO", SPT_PMC_LTR_AZ},
- {"LPSS", SPT_PMC_LTR_LPSS},
- {"SOUTHPORT_D", SPT_PMC_LTR_SPD},
- {"SOUTHPORT_E", SPT_PMC_LTR_SPE},
- {"CAMERA", SPT_PMC_LTR_CAM},
- {"ESPI", SPT_PMC_LTR_ESPI},
- {"SCC", SPT_PMC_LTR_SCC},
- {"ISH", SPT_PMC_LTR_ISH},
- /* Below two cannot be used for LTR_IGNORE */
- {"CURRENT_PLATFORM", SPT_PMC_LTR_CUR_PLT},
- {"AGGREGATED_SYSTEM", SPT_PMC_LTR_CUR_ASLT},
- {}
-};
-
-static const struct pmc_reg_map spt_reg_map = {
- .pfear_sts = ext_spt_pfear_map,
- .mphy_sts = spt_mphy_map,
- .pll_sts = spt_pll_map,
- .ltr_show_sts = spt_ltr_show_map,
- .msr_sts = msr_map,
- .slp_s0_offset = SPT_PMC_SLP_S0_RES_COUNTER_OFFSET,
- .slp_s0_res_counter_step = SPT_PMC_SLP_S0_RES_COUNTER_STEP,
- .ltr_ignore_offset = SPT_PMC_LTR_IGNORE_OFFSET,
- .regmap_length = SPT_PMC_MMIO_REG_LEN,
- .ppfear0_offset = SPT_PMC_XRAM_PPFEAR0A,
- .ppfear_buckets = SPT_PPFEAR_NUM_ENTRIES,
- .pm_cfg_offset = SPT_PMC_PM_CFG_OFFSET,
- .pm_read_disable_bit = SPT_PMC_READ_DISABLE_BIT,
- .ltr_ignore_max = SPT_NUM_IP_IGN_ALLOWED,
- .pm_vric1_offset = SPT_PMC_VRIC1_OFFSET,
-};
-
-/* Cannon Lake: PGD PFET Enable Ack Status Register(s) bitmap */
-static const struct pmc_bit_map cnp_pfear_map[] = {
- {"PMC", BIT(0)},
- {"OPI-DMI", BIT(1)},
- {"SPI/eSPI", BIT(2)},
- {"XHCI", BIT(3)},
- {"SPA", BIT(4)},
- {"SPB", BIT(5)},
- {"SPC", BIT(6)},
- {"GBE", BIT(7)},
-
- {"SATA", BIT(0)},
- {"HDA_PGD0", BIT(1)},
- {"HDA_PGD1", BIT(2)},
- {"HDA_PGD2", BIT(3)},
- {"HDA_PGD3", BIT(4)},
- {"SPD", BIT(5)},
- {"LPSS", BIT(6)},
- {"LPC", BIT(7)},
-
- {"SMB", BIT(0)},
- {"ISH", BIT(1)},
- {"P2SB", BIT(2)},
- {"NPK_VNN", BIT(3)},
- {"SDX", BIT(4)},
- {"SPE", BIT(5)},
- {"Fuse", BIT(6)},
- {"SBR8", BIT(7)},
-
- {"CSME_FSC", BIT(0)},
- {"USB3_OTG", BIT(1)},
- {"EXI", BIT(2)},
- {"CSE", BIT(3)},
- {"CSME_KVM", BIT(4)},
- {"CSME_PMT", BIT(5)},
- {"CSME_CLINK", BIT(6)},
- {"CSME_PTIO", BIT(7)},
-
- {"CSME_USBR", BIT(0)},
- {"CSME_SUSRAM", BIT(1)},
- {"CSME_SMT1", BIT(2)},
- {"CSME_SMT4", BIT(3)},
- {"CSME_SMS2", BIT(4)},
- {"CSME_SMS1", BIT(5)},
- {"CSME_RTC", BIT(6)},
- {"CSME_PSF", BIT(7)},
-
- {"SBR0", BIT(0)},
- {"SBR1", BIT(1)},
- {"SBR2", BIT(2)},
- {"SBR3", BIT(3)},
- {"SBR4", BIT(4)},
- {"SBR5", BIT(5)},
- {"CSME_PECI", BIT(6)},
- {"PSF1", BIT(7)},
-
- {"PSF2", BIT(0)},
- {"PSF3", BIT(1)},
- {"PSF4", BIT(2)},
- {"CNVI", BIT(3)},
- {"UFS0", BIT(4)},
- {"EMMC", BIT(5)},
- {"SPF", BIT(6)},
- {"SBR6", BIT(7)},
-
- {"SBR7", BIT(0)},
- {"NPK_AON", BIT(1)},
- {"HDA_PGD4", BIT(2)},
- {"HDA_PGD5", BIT(3)},
- {"HDA_PGD6", BIT(4)},
- {"PSF6", BIT(5)},
- {"PSF7", BIT(6)},
- {"PSF8", BIT(7)},
- {}
-};
-
-static const struct pmc_bit_map *ext_cnp_pfear_map[] = {
- /*
- * Check intel_pmc_core_ids[] users of cnp_reg_map for
- * a list of core SoCs using this.
- */
- cnp_pfear_map,
- NULL
-};
-
-static const struct pmc_bit_map icl_pfear_map[] = {
- {"RES_65", BIT(0)},
- {"RES_66", BIT(1)},
- {"RES_67", BIT(2)},
- {"TAM", BIT(3)},
- {"GBETSN", BIT(4)},
- {"TBTLSX", BIT(5)},
- {"RES_71", BIT(6)},
- {"RES_72", BIT(7)},
- {}
-};
-
-static const struct pmc_bit_map *ext_icl_pfear_map[] = {
- /*
- * Check intel_pmc_core_ids[] users of icl_reg_map for
- * a list of core SoCs using this.
- */
- cnp_pfear_map,
- icl_pfear_map,
- NULL
-};
-
-static const struct pmc_bit_map tgl_pfear_map[] = {
- {"PSF9", BIT(0)},
- {"RES_66", BIT(1)},
- {"RES_67", BIT(2)},
- {"RES_68", BIT(3)},
- {"RES_69", BIT(4)},
- {"RES_70", BIT(5)},
- {"TBTLSX", BIT(6)},
- {}
-};
-
-static const struct pmc_bit_map *ext_tgl_pfear_map[] = {
- /*
- * Check intel_pmc_core_ids[] users of tgl_reg_map for
- * a list of core SoCs using this.
- */
- cnp_pfear_map,
- tgl_pfear_map,
- NULL
-};
-
-static const struct pmc_bit_map cnp_slps0_dbg0_map[] = {
- {"AUDIO_D3", BIT(0)},
- {"OTG_D3", BIT(1)},
- {"XHCI_D3", BIT(2)},
- {"LPIO_D3", BIT(3)},
- {"SDX_D3", BIT(4)},
- {"SATA_D3", BIT(5)},
- {"UFS0_D3", BIT(6)},
- {"UFS1_D3", BIT(7)},
- {"EMMC_D3", BIT(8)},
- {}
-};
-
-static const struct pmc_bit_map cnp_slps0_dbg1_map[] = {
- {"SDIO_PLL_OFF", BIT(0)},
- {"USB2_PLL_OFF", BIT(1)},
- {"AUDIO_PLL_OFF", BIT(2)},
- {"OC_PLL_OFF", BIT(3)},
- {"MAIN_PLL_OFF", BIT(4)},
- {"XOSC_OFF", BIT(5)},
- {"LPC_CLKS_GATED", BIT(6)},
- {"PCIE_CLKREQS_IDLE", BIT(7)},
- {"AUDIO_ROSC_OFF", BIT(8)},
- {"HPET_XOSC_CLK_REQ", BIT(9)},
- {"PMC_ROSC_SLOW_CLK", BIT(10)},
- {"AON2_ROSC_GATED", BIT(11)},
- {"CLKACKS_DEASSERTED", BIT(12)},
- {}
-};
-
-static const struct pmc_bit_map cnp_slps0_dbg2_map[] = {
- {"MPHY_CORE_GATED", BIT(0)},
- {"CSME_GATED", BIT(1)},
- {"USB2_SUS_GATED", BIT(2)},
- {"DYN_FLEX_IO_IDLE", BIT(3)},
- {"GBE_NO_LINK", BIT(4)},
- {"THERM_SEN_DISABLED", BIT(5)},
- {"PCIE_LOW_POWER", BIT(6)},
- {"ISH_VNNAON_REQ_ACT", BIT(7)},
- {"ISH_VNN_REQ_ACT", BIT(8)},
- {"CNV_VNNAON_REQ_ACT", BIT(9)},
- {"CNV_VNN_REQ_ACT", BIT(10)},
- {"NPK_VNNON_REQ_ACT", BIT(11)},
- {"PMSYNC_STATE_IDLE", BIT(12)},
- {"ALST_GT_THRES", BIT(13)},
- {"PMC_ARC_PG_READY", BIT(14)},
- {}
-};
-
-static const struct pmc_bit_map *cnp_slps0_dbg_maps[] = {
- cnp_slps0_dbg0_map,
- cnp_slps0_dbg1_map,
- cnp_slps0_dbg2_map,
- NULL
-};
-
-static const struct pmc_bit_map cnp_ltr_show_map[] = {
- {"SOUTHPORT_A", CNP_PMC_LTR_SPA},
- {"SOUTHPORT_B", CNP_PMC_LTR_SPB},
- {"SATA", CNP_PMC_LTR_SATA},
- {"GIGABIT_ETHERNET", CNP_PMC_LTR_GBE},
- {"XHCI", CNP_PMC_LTR_XHCI},
- {"Reserved", CNP_PMC_LTR_RESERVED},
- {"ME", CNP_PMC_LTR_ME},
- /* EVA is Enterprise Value Add, doesn't really exist on PCH */
- {"EVA", CNP_PMC_LTR_EVA},
- {"SOUTHPORT_C", CNP_PMC_LTR_SPC},
- {"HD_AUDIO", CNP_PMC_LTR_AZ},
- {"CNV", CNP_PMC_LTR_CNV},
- {"LPSS", CNP_PMC_LTR_LPSS},
- {"SOUTHPORT_D", CNP_PMC_LTR_SPD},
- {"SOUTHPORT_E", CNP_PMC_LTR_SPE},
- {"CAMERA", CNP_PMC_LTR_CAM},
- {"ESPI", CNP_PMC_LTR_ESPI},
- {"SCC", CNP_PMC_LTR_SCC},
- {"ISH", CNP_PMC_LTR_ISH},
- {"UFSX2", CNP_PMC_LTR_UFSX2},
- {"EMMC", CNP_PMC_LTR_EMMC},
- /*
- * Check intel_pmc_core_ids[] users of cnp_reg_map for
- * a list of core SoCs using this.
- */
- {"WIGIG", ICL_PMC_LTR_WIGIG},
- {"THC0", TGL_PMC_LTR_THC0},
- {"THC1", TGL_PMC_LTR_THC1},
- /* Below two cannot be used for LTR_IGNORE */
- {"CURRENT_PLATFORM", CNP_PMC_LTR_CUR_PLT},
- {"AGGREGATED_SYSTEM", CNP_PMC_LTR_CUR_ASLT},
- {}
-};
-
-static const struct pmc_reg_map cnp_reg_map = {
- .pfear_sts = ext_cnp_pfear_map,
- .slp_s0_offset = CNP_PMC_SLP_S0_RES_COUNTER_OFFSET,
- .slp_s0_res_counter_step = SPT_PMC_SLP_S0_RES_COUNTER_STEP,
- .slps0_dbg_maps = cnp_slps0_dbg_maps,
- .ltr_show_sts = cnp_ltr_show_map,
- .msr_sts = msr_map,
- .slps0_dbg_offset = CNP_PMC_SLPS0_DBG_OFFSET,
- .ltr_ignore_offset = CNP_PMC_LTR_IGNORE_OFFSET,
- .regmap_length = CNP_PMC_MMIO_REG_LEN,
- .ppfear0_offset = CNP_PMC_HOST_PPFEAR0A,
- .ppfear_buckets = CNP_PPFEAR_NUM_ENTRIES,
- .pm_cfg_offset = CNP_PMC_PM_CFG_OFFSET,
- .pm_read_disable_bit = CNP_PMC_READ_DISABLE_BIT,
- .ltr_ignore_max = CNP_NUM_IP_IGN_ALLOWED,
- .etr3_offset = ETR3_OFFSET,
-};
-
-static const struct pmc_reg_map icl_reg_map = {
- .pfear_sts = ext_icl_pfear_map,
- .slp_s0_offset = CNP_PMC_SLP_S0_RES_COUNTER_OFFSET,
- .slp_s0_res_counter_step = ICL_PMC_SLP_S0_RES_COUNTER_STEP,
- .slps0_dbg_maps = cnp_slps0_dbg_maps,
- .ltr_show_sts = cnp_ltr_show_map,
- .msr_sts = msr_map,
- .slps0_dbg_offset = CNP_PMC_SLPS0_DBG_OFFSET,
- .ltr_ignore_offset = CNP_PMC_LTR_IGNORE_OFFSET,
- .regmap_length = CNP_PMC_MMIO_REG_LEN,
- .ppfear0_offset = CNP_PMC_HOST_PPFEAR0A,
- .ppfear_buckets = ICL_PPFEAR_NUM_ENTRIES,
- .pm_cfg_offset = CNP_PMC_PM_CFG_OFFSET,
- .pm_read_disable_bit = CNP_PMC_READ_DISABLE_BIT,
- .ltr_ignore_max = ICL_NUM_IP_IGN_ALLOWED,
- .etr3_offset = ETR3_OFFSET,
-};
-
-static const struct pmc_bit_map tgl_clocksource_status_map[] = {
- {"USB2PLL_OFF_STS", BIT(18)},
- {"PCIe/USB3.1_Gen2PLL_OFF_STS", BIT(19)},
- {"PCIe_Gen3PLL_OFF_STS", BIT(20)},
- {"OPIOPLL_OFF_STS", BIT(21)},
- {"OCPLL_OFF_STS", BIT(22)},
- {"MainPLL_OFF_STS", BIT(23)},
- {"MIPIPLL_OFF_STS", BIT(24)},
- {"Fast_XTAL_Osc_OFF_STS", BIT(25)},
- {"AC_Ring_Osc_OFF_STS", BIT(26)},
- {"MC_Ring_Osc_OFF_STS", BIT(27)},
- {"SATAPLL_OFF_STS", BIT(29)},
- {"XTAL_USB2PLL_OFF_STS", BIT(31)},
- {}
-};
-
-static const struct pmc_bit_map tgl_power_gating_status_map[] = {
- {"CSME_PG_STS", BIT(0)},
- {"SATA_PG_STS", BIT(1)},
- {"xHCI_PG_STS", BIT(2)},
- {"UFSX2_PG_STS", BIT(3)},
- {"OTG_PG_STS", BIT(5)},
- {"SPA_PG_STS", BIT(6)},
- {"SPB_PG_STS", BIT(7)},
- {"SPC_PG_STS", BIT(8)},
- {"SPD_PG_STS", BIT(9)},
- {"SPE_PG_STS", BIT(10)},
- {"SPF_PG_STS", BIT(11)},
- {"LSX_PG_STS", BIT(13)},
- {"P2SB_PG_STS", BIT(14)},
- {"PSF_PG_STS", BIT(15)},
- {"SBR_PG_STS", BIT(16)},
- {"OPIDMI_PG_STS", BIT(17)},
- {"THC0_PG_STS", BIT(18)},
- {"THC1_PG_STS", BIT(19)},
- {"GBETSN_PG_STS", BIT(20)},
- {"GBE_PG_STS", BIT(21)},
- {"LPSS_PG_STS", BIT(22)},
- {"MMP_UFSX2_PG_STS", BIT(23)},
- {"MMP_UFSX2B_PG_STS", BIT(24)},
- {"FIA_PG_STS", BIT(25)},
- {}
-};
-
-static const struct pmc_bit_map tgl_d3_status_map[] = {
- {"ADSP_D3_STS", BIT(0)},
- {"SATA_D3_STS", BIT(1)},
- {"xHCI0_D3_STS", BIT(2)},
- {"xDCI1_D3_STS", BIT(5)},
- {"SDX_D3_STS", BIT(6)},
- {"EMMC_D3_STS", BIT(7)},
- {"IS_D3_STS", BIT(8)},
- {"THC0_D3_STS", BIT(9)},
- {"THC1_D3_STS", BIT(10)},
- {"GBE_D3_STS", BIT(11)},
- {"GBE_TSN_D3_STS", BIT(12)},
- {}
-};
-
-static const struct pmc_bit_map tgl_vnn_req_status_map[] = {
- {"GPIO_COM0_VNN_REQ_STS", BIT(1)},
- {"GPIO_COM1_VNN_REQ_STS", BIT(2)},
- {"GPIO_COM2_VNN_REQ_STS", BIT(3)},
- {"GPIO_COM3_VNN_REQ_STS", BIT(4)},
- {"GPIO_COM4_VNN_REQ_STS", BIT(5)},
- {"GPIO_COM5_VNN_REQ_STS", BIT(6)},
- {"Audio_VNN_REQ_STS", BIT(7)},
- {"ISH_VNN_REQ_STS", BIT(8)},
- {"CNVI_VNN_REQ_STS", BIT(9)},
- {"eSPI_VNN_REQ_STS", BIT(10)},
- {"Display_VNN_REQ_STS", BIT(11)},
- {"DTS_VNN_REQ_STS", BIT(12)},
- {"SMBUS_VNN_REQ_STS", BIT(14)},
- {"CSME_VNN_REQ_STS", BIT(15)},
- {"SMLINK0_VNN_REQ_STS", BIT(16)},
- {"SMLINK1_VNN_REQ_STS", BIT(17)},
- {"CLINK_VNN_REQ_STS", BIT(20)},
- {"DCI_VNN_REQ_STS", BIT(21)},
- {"ITH_VNN_REQ_STS", BIT(22)},
- {"CSME_VNN_REQ_STS", BIT(24)},
- {"GBE_VNN_REQ_STS", BIT(25)},
- {}
-};
-
-static const struct pmc_bit_map tgl_vnn_misc_status_map[] = {
- {"CPU_C10_REQ_STS_0", BIT(0)},
- {"PCIe_LPM_En_REQ_STS_3", BIT(3)},
- {"ITH_REQ_STS_5", BIT(5)},
- {"CNVI_REQ_STS_6", BIT(6)},
- {"ISH_REQ_STS_7", BIT(7)},
- {"USB2_SUS_PG_Sys_REQ_STS_10", BIT(10)},
- {"PCIe_Clk_REQ_STS_12", BIT(12)},
- {"MPHY_Core_DL_REQ_STS_16", BIT(16)},
- {"Break-even_En_REQ_STS_17", BIT(17)},
- {"Auto-demo_En_REQ_STS_18", BIT(18)},
- {"MPHY_SUS_REQ_STS_22", BIT(22)},
- {"xDCI_attached_REQ_STS_24", BIT(24)},
- {}
-};
-
-static const struct pmc_bit_map tgl_signal_status_map[] = {
- {"LSX_Wake0_En_STS", BIT(0)},
- {"LSX_Wake0_Pol_STS", BIT(1)},
- {"LSX_Wake1_En_STS", BIT(2)},
- {"LSX_Wake1_Pol_STS", BIT(3)},
- {"LSX_Wake2_En_STS", BIT(4)},
- {"LSX_Wake2_Pol_STS", BIT(5)},
- {"LSX_Wake3_En_STS", BIT(6)},
- {"LSX_Wake3_Pol_STS", BIT(7)},
- {"LSX_Wake4_En_STS", BIT(8)},
- {"LSX_Wake4_Pol_STS", BIT(9)},
- {"LSX_Wake5_En_STS", BIT(10)},
- {"LSX_Wake5_Pol_STS", BIT(11)},
- {"LSX_Wake6_En_STS", BIT(12)},
- {"LSX_Wake6_Pol_STS", BIT(13)},
- {"LSX_Wake7_En_STS", BIT(14)},
- {"LSX_Wake7_Pol_STS", BIT(15)},
- {"Intel_Se_IO_Wake0_En_STS", BIT(16)},
- {"Intel_Se_IO_Wake0_Pol_STS", BIT(17)},
- {"Intel_Se_IO_Wake1_En_STS", BIT(18)},
- {"Intel_Se_IO_Wake1_Pol_STS", BIT(19)},
- {"Int_Timer_SS_Wake0_En_STS", BIT(20)},
- {"Int_Timer_SS_Wake0_Pol_STS", BIT(21)},
- {"Int_Timer_SS_Wake1_En_STS", BIT(22)},
- {"Int_Timer_SS_Wake1_Pol_STS", BIT(23)},
- {"Int_Timer_SS_Wake2_En_STS", BIT(24)},
- {"Int_Timer_SS_Wake2_Pol_STS", BIT(25)},
- {"Int_Timer_SS_Wake3_En_STS", BIT(26)},
- {"Int_Timer_SS_Wake3_Pol_STS", BIT(27)},
- {"Int_Timer_SS_Wake4_En_STS", BIT(28)},
- {"Int_Timer_SS_Wake4_Pol_STS", BIT(29)},
- {"Int_Timer_SS_Wake5_En_STS", BIT(30)},
- {"Int_Timer_SS_Wake5_Pol_STS", BIT(31)},
- {}
-};
-
-static const struct pmc_bit_map *tgl_lpm_maps[] = {
- tgl_clocksource_status_map,
- tgl_power_gating_status_map,
- tgl_d3_status_map,
- tgl_vnn_req_status_map,
- tgl_vnn_misc_status_map,
- tgl_signal_status_map,
- NULL
-};
-
-static const struct pmc_reg_map tgl_reg_map = {
- .pfear_sts = ext_tgl_pfear_map,
- .slp_s0_offset = CNP_PMC_SLP_S0_RES_COUNTER_OFFSET,
- .slp_s0_res_counter_step = TGL_PMC_SLP_S0_RES_COUNTER_STEP,
- .ltr_show_sts = cnp_ltr_show_map,
- .msr_sts = msr_map,
- .ltr_ignore_offset = CNP_PMC_LTR_IGNORE_OFFSET,
- .regmap_length = CNP_PMC_MMIO_REG_LEN,
- .ppfear0_offset = CNP_PMC_HOST_PPFEAR0A,
- .ppfear_buckets = ICL_PPFEAR_NUM_ENTRIES,
- .pm_cfg_offset = CNP_PMC_PM_CFG_OFFSET,
- .pm_read_disable_bit = CNP_PMC_READ_DISABLE_BIT,
- .ltr_ignore_max = TGL_NUM_IP_IGN_ALLOWED,
- .lpm_num_maps = TGL_LPM_NUM_MAPS,
- .lpm_res_counter_step_x2 = TGL_PMC_LPM_RES_COUNTER_STEP_X2,
- .lpm_sts_latch_en_offset = TGL_LPM_STS_LATCH_EN_OFFSET,
- .lpm_en_offset = TGL_LPM_EN_OFFSET,
- .lpm_priority_offset = TGL_LPM_PRI_OFFSET,
- .lpm_residency_offset = TGL_LPM_RESIDENCY_OFFSET,
- .lpm_sts = tgl_lpm_maps,
- .lpm_status_offset = TGL_LPM_STATUS_OFFSET,
- .lpm_live_status_offset = TGL_LPM_LIVE_STATUS_OFFSET,
- .etr3_offset = ETR3_OFFSET,
-};
-
-static void pmc_core_get_tgl_lpm_reqs(struct platform_device *pdev)
-{
- struct pmc_dev *pmcdev = platform_get_drvdata(pdev);
- const int num_maps = pmcdev->map->lpm_num_maps;
- u32 lpm_size = LPM_MAX_NUM_MODES * num_maps * 4;
- union acpi_object *out_obj;
- struct acpi_device *adev;
- guid_t s0ix_dsm_guid;
- u32 *lpm_req_regs, *addr;
-
- adev = ACPI_COMPANION(&pdev->dev);
- if (!adev)
- return;
-
- guid_parse(ACPI_S0IX_DSM_UUID, &s0ix_dsm_guid);
-
- out_obj = acpi_evaluate_dsm(adev->handle, &s0ix_dsm_guid, 0,
- ACPI_GET_LOW_MODE_REGISTERS, NULL);
- if (out_obj && out_obj->type == ACPI_TYPE_BUFFER) {
- u32 size = out_obj->buffer.length;
-
- if (size != lpm_size) {
- acpi_handle_debug(adev->handle,
- "_DSM returned unexpected buffer size, have %u, expect %u\n",
- size, lpm_size);
- goto free_acpi_obj;
- }
- } else {
- acpi_handle_debug(adev->handle,
- "_DSM function 0 evaluation failed\n");
- goto free_acpi_obj;
- }
-
- addr = (u32 *)out_obj->buffer.pointer;
-
- lpm_req_regs = devm_kzalloc(&pdev->dev, lpm_size * sizeof(u32),
- GFP_KERNEL);
- if (!lpm_req_regs)
- goto free_acpi_obj;
-
- memcpy(lpm_req_regs, addr, lpm_size);
- pmcdev->lpm_req_regs = lpm_req_regs;
-
-free_acpi_obj:
- ACPI_FREE(out_obj);
-}
-
-/* Alder Lake: PGD PFET Enable Ack Status Register(s) bitmap */
-static const struct pmc_bit_map adl_pfear_map[] = {
- {"SPI/eSPI", BIT(2)},
- {"XHCI", BIT(3)},
- {"SPA", BIT(4)},
- {"SPB", BIT(5)},
- {"SPC", BIT(6)},
- {"GBE", BIT(7)},
-
- {"SATA", BIT(0)},
- {"HDA_PGD0", BIT(1)},
- {"HDA_PGD1", BIT(2)},
- {"HDA_PGD2", BIT(3)},
- {"HDA_PGD3", BIT(4)},
- {"SPD", BIT(5)},
- {"LPSS", BIT(6)},
-
- {"SMB", BIT(0)},
- {"ISH", BIT(1)},
- {"ITH", BIT(3)},
-
- {"XDCI", BIT(1)},
- {"DCI", BIT(2)},
- {"CSE", BIT(3)},
- {"CSME_KVM", BIT(4)},
- {"CSME_PMT", BIT(5)},
- {"CSME_CLINK", BIT(6)},
- {"CSME_PTIO", BIT(7)},
-
- {"CSME_USBR", BIT(0)},
- {"CSME_SUSRAM", BIT(1)},
- {"CSME_SMT1", BIT(2)},
- {"CSME_SMS2", BIT(4)},
- {"CSME_SMS1", BIT(5)},
- {"CSME_RTC", BIT(6)},
- {"CSME_PSF", BIT(7)},
-
- {"CNVI", BIT(3)},
-
- {"HDA_PGD4", BIT(2)},
- {"HDA_PGD5", BIT(3)},
- {"HDA_PGD6", BIT(4)},
- {}
-};
-
-static const struct pmc_bit_map *ext_adl_pfear_map[] = {
- /*
- * Check intel_pmc_core_ids[] users of cnp_reg_map for
- * a list of core SoCs using this.
- */
- adl_pfear_map,
- NULL
-};
-
-static const struct pmc_bit_map adl_ltr_show_map[] = {
- {"SOUTHPORT_A", CNP_PMC_LTR_SPA},
- {"SOUTHPORT_B", CNP_PMC_LTR_SPB},
- {"SATA", CNP_PMC_LTR_SATA},
- {"GIGABIT_ETHERNET", CNP_PMC_LTR_GBE},
- {"XHCI", CNP_PMC_LTR_XHCI},
- {"SOUTHPORT_F", ADL_PMC_LTR_SPF},
- {"ME", CNP_PMC_LTR_ME},
- /* EVA is Enterprise Value Add, doesn't really exist on PCH */
- {"SATA1", CNP_PMC_LTR_EVA},
- {"SOUTHPORT_C", CNP_PMC_LTR_SPC},
- {"HD_AUDIO", CNP_PMC_LTR_AZ},
- {"CNV", CNP_PMC_LTR_CNV},
- {"LPSS", CNP_PMC_LTR_LPSS},
- {"SOUTHPORT_D", CNP_PMC_LTR_SPD},
- {"SOUTHPORT_E", CNP_PMC_LTR_SPE},
- {"SATA2", CNP_PMC_LTR_CAM},
- {"ESPI", CNP_PMC_LTR_ESPI},
- {"SCC", CNP_PMC_LTR_SCC},
- {"ISH", CNP_PMC_LTR_ISH},
- {"UFSX2", CNP_PMC_LTR_UFSX2},
- {"EMMC", CNP_PMC_LTR_EMMC},
- /*
- * Check intel_pmc_core_ids[] users of cnp_reg_map for
- * a list of core SoCs using this.
- */
- {"WIGIG", ICL_PMC_LTR_WIGIG},
- {"THC0", TGL_PMC_LTR_THC0},
- {"THC1", TGL_PMC_LTR_THC1},
- {"SOUTHPORT_G", CNP_PMC_LTR_RESERVED},
-
- /* Below two cannot be used for LTR_IGNORE */
- {"CURRENT_PLATFORM", CNP_PMC_LTR_CUR_PLT},
- {"AGGREGATED_SYSTEM", CNP_PMC_LTR_CUR_ASLT},
- {}
-};
-
-static const struct pmc_bit_map adl_clocksource_status_map[] = {
- {"CLKPART1_OFF_STS", BIT(0)},
- {"CLKPART2_OFF_STS", BIT(1)},
- {"CLKPART3_OFF_STS", BIT(2)},
- {"CLKPART4_OFF_STS", BIT(3)},
- {"CLKPART5_OFF_STS", BIT(4)},
- {"CLKPART6_OFF_STS", BIT(5)},
- {"CLKPART7_OFF_STS", BIT(6)},
- {"CLKPART8_OFF_STS", BIT(7)},
- {"PCIE0PLL_OFF_STS", BIT(10)},
- {"PCIE1PLL_OFF_STS", BIT(11)},
- {"PCIE2PLL_OFF_STS", BIT(12)},
- {"PCIE3PLL_OFF_STS", BIT(13)},
- {"PCIE4PLL_OFF_STS", BIT(14)},
- {"PCIE5PLL_OFF_STS", BIT(15)},
- {"PCIE6PLL_OFF_STS", BIT(16)},
- {"USB2PLL_OFF_STS", BIT(18)},
- {"OCPLL_OFF_STS", BIT(22)},
- {"AUDIOPLL_OFF_STS", BIT(23)},
- {"GBEPLL_OFF_STS", BIT(24)},
- {"Fast_XTAL_Osc_OFF_STS", BIT(25)},
- {"AC_Ring_Osc_OFF_STS", BIT(26)},
- {"MC_Ring_Osc_OFF_STS", BIT(27)},
- {"SATAPLL_OFF_STS", BIT(29)},
- {"USB3PLL_OFF_STS", BIT(31)},
- {}
-};
-
-static const struct pmc_bit_map adl_power_gating_status_0_map[] = {
- {"PMC_PGD0_PG_STS", BIT(0)},
- {"DMI_PGD0_PG_STS", BIT(1)},
- {"ESPISPI_PGD0_PG_STS", BIT(2)},
- {"XHCI_PGD0_PG_STS", BIT(3)},
- {"SPA_PGD0_PG_STS", BIT(4)},
- {"SPB_PGD0_PG_STS", BIT(5)},
- {"SPC_PGD0_PG_STS", BIT(6)},
- {"GBE_PGD0_PG_STS", BIT(7)},
- {"SATA_PGD0_PG_STS", BIT(8)},
- {"DSP_PGD0_PG_STS", BIT(9)},
- {"DSP_PGD1_PG_STS", BIT(10)},
- {"DSP_PGD2_PG_STS", BIT(11)},
- {"DSP_PGD3_PG_STS", BIT(12)},
- {"SPD_PGD0_PG_STS", BIT(13)},
- {"LPSS_PGD0_PG_STS", BIT(14)},
- {"SMB_PGD0_PG_STS", BIT(16)},
- {"ISH_PGD0_PG_STS", BIT(17)},
- {"NPK_PGD0_PG_STS", BIT(19)},
- {"PECI_PGD0_PG_STS", BIT(21)},
- {"XDCI_PGD0_PG_STS", BIT(25)},
- {"EXI_PGD0_PG_STS", BIT(26)},
- {"CSE_PGD0_PG_STS", BIT(27)},
- {"KVMCC_PGD0_PG_STS", BIT(28)},
- {"PMT_PGD0_PG_STS", BIT(29)},
- {"CLINK_PGD0_PG_STS", BIT(30)},
- {"PTIO_PGD0_PG_STS", BIT(31)},
- {}
-};
-
-static const struct pmc_bit_map adl_power_gating_status_1_map[] = {
- {"USBR0_PGD0_PG_STS", BIT(0)},
- {"SMT1_PGD0_PG_STS", BIT(2)},
- {"CSMERTC_PGD0_PG_STS", BIT(6)},
- {"CSMEPSF_PGD0_PG_STS", BIT(7)},
- {"CNVI_PGD0_PG_STS", BIT(19)},
- {"DSP_PGD4_PG_STS", BIT(26)},
- {"SPG_PGD0_PG_STS", BIT(27)},
- {"SPE_PGD0_PG_STS", BIT(28)},
- {}
-};
-
-static const struct pmc_bit_map adl_power_gating_status_2_map[] = {
- {"THC0_PGD0_PG_STS", BIT(7)},
- {"THC1_PGD0_PG_STS", BIT(8)},
- {"SPF_PGD0_PG_STS", BIT(14)},
- {}
-};
-
-static const struct pmc_bit_map adl_d3_status_0_map[] = {
- {"ISH_D3_STS", BIT(2)},
- {"LPSS_D3_STS", BIT(3)},
- {"XDCI_D3_STS", BIT(4)},
- {"XHCI_D3_STS", BIT(5)},
- {"SPA_D3_STS", BIT(12)},
- {"SPB_D3_STS", BIT(13)},
- {"SPC_D3_STS", BIT(14)},
- {"SPD_D3_STS", BIT(15)},
- {"SPE_D3_STS", BIT(16)},
- {"DSP_D3_STS", BIT(19)},
- {"SATA_D3_STS", BIT(20)},
- {"DMI_D3_STS", BIT(22)},
- {}
-};
-
-static const struct pmc_bit_map adl_d3_status_1_map[] = {
- {"GBE_D3_STS", BIT(19)},
- {"CNVI_D3_STS", BIT(27)},
- {}
-};
-
-static const struct pmc_bit_map adl_d3_status_2_map[] = {
- {"CSMERTC_D3_STS", BIT(1)},
- {"CSE_D3_STS", BIT(4)},
- {"KVMCC_D3_STS", BIT(5)},
- {"USBR0_D3_STS", BIT(6)},
- {"SMT1_D3_STS", BIT(8)},
- {"PTIO_D3_STS", BIT(16)},
- {"PMT_D3_STS", BIT(17)},
- {}
-};
-
-static const struct pmc_bit_map adl_d3_status_3_map[] = {
- {"THC0_D3_STS", BIT(14)},
- {"THC1_D3_STS", BIT(15)},
- {}
-};
-
-static const struct pmc_bit_map adl_vnn_req_status_0_map[] = {
- {"ISH_VNN_REQ_STS", BIT(2)},
- {"ESPISPI_VNN_REQ_STS", BIT(18)},
- {"DSP_VNN_REQ_STS", BIT(19)},
- {}
-};
-
-static const struct pmc_bit_map adl_vnn_req_status_1_map[] = {
- {"NPK_VNN_REQ_STS", BIT(4)},
- {"EXI_VNN_REQ_STS", BIT(9)},
- {"GBE_VNN_REQ_STS", BIT(19)},
- {"SMB_VNN_REQ_STS", BIT(25)},
- {"CNVI_VNN_REQ_STS", BIT(27)},
- {}
-};
-
-static const struct pmc_bit_map adl_vnn_req_status_2_map[] = {
- {"CSMERTC_VNN_REQ_STS", BIT(1)},
- {"CSE_VNN_REQ_STS", BIT(4)},
- {"SMT1_VNN_REQ_STS", BIT(8)},
- {"CLINK_VNN_REQ_STS", BIT(14)},
- {"GPIOCOM4_VNN_REQ_STS", BIT(20)},
- {"GPIOCOM3_VNN_REQ_STS", BIT(21)},
- {"GPIOCOM2_VNN_REQ_STS", BIT(22)},
- {"GPIOCOM1_VNN_REQ_STS", BIT(23)},
- {"GPIOCOM0_VNN_REQ_STS", BIT(24)},
- {}
-};
-
-static const struct pmc_bit_map adl_vnn_req_status_3_map[] = {
- {"GPIOCOM5_VNN_REQ_STS", BIT(11)},
- {}
-};
-
-static const struct pmc_bit_map adl_vnn_misc_status_map[] = {
- {"CPU_C10_REQ_STS", BIT(0)},
- {"PCIe_LPM_En_REQ_STS", BIT(3)},
- {"ITH_REQ_STS", BIT(5)},
- {"CNVI_REQ_STS", BIT(6)},
- {"ISH_REQ_STS", BIT(7)},
- {"USB2_SUS_PG_Sys_REQ_STS", BIT(10)},
- {"PCIe_Clk_REQ_STS", BIT(12)},
- {"MPHY_Core_DL_REQ_STS", BIT(16)},
- {"Break-even_En_REQ_STS", BIT(17)},
- {"MPHY_SUS_REQ_STS", BIT(22)},
- {"xDCI_attached_REQ_STS", BIT(24)},
- {}
-};
-
-static const struct pmc_bit_map *adl_lpm_maps[] = {
- adl_clocksource_status_map,
- adl_power_gating_status_0_map,
- adl_power_gating_status_1_map,
- adl_power_gating_status_2_map,
- adl_d3_status_0_map,
- adl_d3_status_1_map,
- adl_d3_status_2_map,
- adl_d3_status_3_map,
- adl_vnn_req_status_0_map,
- adl_vnn_req_status_1_map,
- adl_vnn_req_status_2_map,
- adl_vnn_req_status_3_map,
- adl_vnn_misc_status_map,
- tgl_signal_status_map,
- NULL
-};
-
-static const struct pmc_reg_map adl_reg_map = {
- .pfear_sts = ext_adl_pfear_map,
- .slp_s0_offset = ADL_PMC_SLP_S0_RES_COUNTER_OFFSET,
- .slp_s0_res_counter_step = TGL_PMC_SLP_S0_RES_COUNTER_STEP,
- .ltr_show_sts = adl_ltr_show_map,
- .msr_sts = msr_map,
- .ltr_ignore_offset = CNP_PMC_LTR_IGNORE_OFFSET,
- .regmap_length = CNP_PMC_MMIO_REG_LEN,
- .ppfear0_offset = CNP_PMC_HOST_PPFEAR0A,
- .ppfear_buckets = CNP_PPFEAR_NUM_ENTRIES,
- .pm_cfg_offset = CNP_PMC_PM_CFG_OFFSET,
- .pm_read_disable_bit = CNP_PMC_READ_DISABLE_BIT,
- .ltr_ignore_max = ADL_NUM_IP_IGN_ALLOWED,
- .lpm_num_modes = ADL_LPM_NUM_MODES,
- .lpm_num_maps = ADL_LPM_NUM_MAPS,
- .lpm_res_counter_step_x2 = TGL_PMC_LPM_RES_COUNTER_STEP_X2,
- .etr3_offset = ETR3_OFFSET,
- .lpm_sts_latch_en_offset = ADL_LPM_STATUS_LATCH_EN_OFFSET,
- .lpm_priority_offset = ADL_LPM_PRI_OFFSET,
- .lpm_en_offset = ADL_LPM_EN_OFFSET,
- .lpm_residency_offset = ADL_LPM_RESIDENCY_OFFSET,
- .lpm_sts = adl_lpm_maps,
- .lpm_status_offset = ADL_LPM_STATUS_OFFSET,
- .lpm_live_status_offset = ADL_LPM_LIVE_STATUS_OFFSET,
-};
-
static inline u32 pmc_core_reg_read(struct pmc_dev *pmcdev, int reg_offset)
{
return readl(pmcdev->regbase + reg_offset);
@@ -1327,7 +435,7 @@ out_unlock:
}
DEFINE_SHOW_ATTRIBUTE(pmc_core_pll);
-static int pmc_core_send_ltr_ignore(struct pmc_dev *pmcdev, u32 value)
+int pmc_core_send_ltr_ignore(struct pmc_dev *pmcdev, u32 value)
{
const struct pmc_reg_map *map = pmcdev->map;
u32 reg;
@@ -1793,7 +901,11 @@ static void pmc_core_get_low_power_modes(struct platform_device *pdev)
return;
lpm_en = pmc_core_reg_read(pmcdev, pmcdev->map->lpm_en_offset);
- pmcdev->num_lpm_modes = hweight32(lpm_en);
+ /* For MTL, BIT 31 is not an lpm mode but a enable bit.
+ * Lower byte is enough to cover the number of lpm modes for all
+ * platforms and hence mask the upper 3 bytes.
+ */
+ pmcdev->num_lpm_modes = hweight32(lpm_en & 0xFF);
/* Read 32 bit LPM_PRI register */
lpm_pri = pmc_core_reg_read(pmcdev, pmcdev->map->lpm_priority_offset);
@@ -1896,26 +1008,27 @@ static void pmc_core_dbgfs_register(struct pmc_dev *pmcdev)
}
static const struct x86_cpu_id intel_pmc_core_ids[] = {
- X86_MATCH_INTEL_FAM6_MODEL(SKYLAKE_L, &spt_reg_map),
- X86_MATCH_INTEL_FAM6_MODEL(SKYLAKE, &spt_reg_map),
- X86_MATCH_INTEL_FAM6_MODEL(KABYLAKE_L, &spt_reg_map),
- X86_MATCH_INTEL_FAM6_MODEL(KABYLAKE, &spt_reg_map),
- X86_MATCH_INTEL_FAM6_MODEL(CANNONLAKE_L, &cnp_reg_map),
- X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_L, &icl_reg_map),
- X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_NNPI, &icl_reg_map),
- X86_MATCH_INTEL_FAM6_MODEL(COMETLAKE, &cnp_reg_map),
- X86_MATCH_INTEL_FAM6_MODEL(COMETLAKE_L, &cnp_reg_map),
- X86_MATCH_INTEL_FAM6_MODEL(TIGERLAKE_L, &tgl_reg_map),
- X86_MATCH_INTEL_FAM6_MODEL(TIGERLAKE, &tgl_reg_map),
- X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT, &tgl_reg_map),
- X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT_L, &icl_reg_map),
- X86_MATCH_INTEL_FAM6_MODEL(ROCKETLAKE, &tgl_reg_map),
- X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_L, &tgl_reg_map),
- X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_N, &tgl_reg_map),
- X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE, &adl_reg_map),
- X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE_P, &tgl_reg_map),
- X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE, &adl_reg_map),
- X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE_S, &adl_reg_map),
+ X86_MATCH_INTEL_FAM6_MODEL(SKYLAKE_L, spt_core_init),
+ X86_MATCH_INTEL_FAM6_MODEL(SKYLAKE, spt_core_init),
+ X86_MATCH_INTEL_FAM6_MODEL(KABYLAKE_L, spt_core_init),
+ X86_MATCH_INTEL_FAM6_MODEL(KABYLAKE, spt_core_init),
+ X86_MATCH_INTEL_FAM6_MODEL(CANNONLAKE_L, cnp_core_init),
+ X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_L, icl_core_init),
+ X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_NNPI, icl_core_init),
+ X86_MATCH_INTEL_FAM6_MODEL(COMETLAKE, cnp_core_init),
+ X86_MATCH_INTEL_FAM6_MODEL(COMETLAKE_L, cnp_core_init),
+ X86_MATCH_INTEL_FAM6_MODEL(TIGERLAKE_L, tgl_core_init),
+ X86_MATCH_INTEL_FAM6_MODEL(TIGERLAKE, tgl_core_init),
+ X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT, tgl_core_init),
+ X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT_L, icl_core_init),
+ X86_MATCH_INTEL_FAM6_MODEL(ROCKETLAKE, tgl_core_init),
+ X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_L, tgl_core_init),
+ X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_N, tgl_core_init),
+ X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE, adl_core_init),
+ X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE_P, tgl_core_init),
+ X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE, adl_core_init),
+ X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE_S, adl_core_init),
+ X86_MATCH_INTEL_FAM6_MODEL(METEORLAKE, mtl_core_init),
{}
};
@@ -1975,6 +1088,7 @@ static int pmc_core_probe(struct platform_device *pdev)
static bool device_initialized;
struct pmc_dev *pmcdev;
const struct x86_cpu_id *cpu_id;
+ void (*core_init)(struct pmc_dev *pmcdev);
u64 slp_s0_addr;
if (device_initialized)
@@ -1985,20 +1099,25 @@ static int pmc_core_probe(struct platform_device *pdev)
return -ENOMEM;
platform_set_drvdata(pdev, pmcdev);
+ pmcdev->pdev = pdev;
cpu_id = x86_match_cpu(intel_pmc_core_ids);
if (!cpu_id)
return -ENODEV;
- pmcdev->map = (struct pmc_reg_map *)cpu_id->driver_data;
+ core_init = (void (*)(struct pmc_dev *))cpu_id->driver_data;
/*
* Coffee Lake has CPU ID of Kaby Lake and Cannon Lake PCH. So here
* Sunrisepoint PCH regmap can't be used. Use Cannon Lake PCH regmap
* in this case.
*/
- if (pmcdev->map == &spt_reg_map && !pci_dev_present(pmc_pci_ids))
- pmcdev->map = &cnp_reg_map;
+ if (core_init == spt_core_init && !pci_dev_present(pmc_pci_ids))
+ core_init = cnp_core_init;
+
+ mutex_init(&pmcdev->lock);
+ core_init(pmcdev);
+
if (lpit_read_residency_count_address(&slp_s0_addr)) {
pmcdev->base_addr = PMC_BASE_ADDR_DEFAULT;
@@ -2014,24 +1133,13 @@ static int pmc_core_probe(struct platform_device *pdev)
if (!pmcdev->regbase)
return -ENOMEM;
- mutex_init(&pmcdev->lock);
+ if (pmcdev->core_configure)
+ pmcdev->core_configure(pmcdev);
pmcdev->pmc_xram_read_bit = pmc_core_check_read_lock_bit(pmcdev);
pmc_core_get_low_power_modes(pdev);
pmc_core_do_dmi_quirks(pmcdev);
- if (pmcdev->map == &tgl_reg_map)
- pmc_core_get_tgl_lpm_reqs(pdev);
-
- /*
- * On TGL and ADL, due to a hardware limitation, the GBE LTR blocks PC10
- * when a cable is attached. Tell the PMC to ignore it.
- */
- if (pmcdev->map == &tgl_reg_map || pmcdev->map == &adl_reg_map) {
- dev_dbg(&pdev->dev, "ignoring GBE LTR\n");
- pmc_core_send_ltr_ignore(pmcdev, 3);
- }
-
pmc_core_dbgfs_register(pmcdev);
device_initialized = true;
generated by cgit v1.2.3 (git 2.39.0) at 2024-09-03 15:35:57 +0300