diff options
Diffstat (limited to 'drivers/platform/x86/intel_pmc_core.h')
| -rw-r--r-- | drivers/platform/x86/intel_pmc_core.h | 53 |
1 files changed, 50 insertions, 3 deletions
diff --git a/drivers/platform/x86/intel_pmc_core.h b/drivers/platform/x86/intel_pmc_core.h index f33cd2c34835..e8dae9c6c45f 100644 --- a/drivers/platform/x86/intel_pmc_core.h +++ b/drivers/platform/x86/intel_pmc_core.h @@ -187,20 +187,38 @@ enum ppfear_regs { #define ICL_PMC_LTR_WIGIG 0x1BFC #define ICL_PMC_SLP_S0_RES_COUNTER_STEP 0x64 -#define TGL_NUM_IP_IGN_ALLOWED 22 +#define LPM_MAX_NUM_MODES 8 +#define GET_X2_COUNTER(v) ((v) >> 1) +#define LPM_STS_LATCH_MODE BIT(31) + #define TGL_PMC_SLP_S0_RES_COUNTER_STEP 0x7A +#define TGL_PMC_LTR_THC0 0x1C04 +#define TGL_PMC_LTR_THC1 0x1C08 +#define TGL_NUM_IP_IGN_ALLOWED 23 +#define TGL_PMC_LPM_RES_COUNTER_STEP_X2 61 /* 30.5us * 2 */ /* * Tigerlake Power Management Controller register offsets */ +#define TGL_LPM_STS_LATCH_EN_OFFSET 0x1C34 #define TGL_LPM_EN_OFFSET 0x1C78 #define TGL_LPM_RESIDENCY_OFFSET 0x1C80 /* Tigerlake Low Power Mode debug registers */ #define TGL_LPM_STATUS_OFFSET 0x1C3C #define TGL_LPM_LIVE_STATUS_OFFSET 0x1C5C +#define TGL_LPM_PRI_OFFSET 0x1C7C +#define TGL_LPM_NUM_MAPS 6 + +/* Extended Test Mode Register 3 (CNL and later) */ +#define ETR3_OFFSET 0x1048 +#define ETR3_CF9GR BIT(20) +#define ETR3_CF9LOCK BIT(31) + +/* Extended Test Mode Register LPM bits (TGL and later */ +#define ETR3_CLEAR_LPM_EVENTS BIT(28) -const char *tgl_lpm_modes[] = { +const char *pmc_lpm_modes[] = { "S0i2.0", "S0i2.1", "S0i2.2", @@ -258,11 +276,15 @@ struct pmc_reg_map { const u32 ltr_ignore_max; const u32 pm_vric1_offset; /* Low Power Mode registers */ - const char **lpm_modes; + const int lpm_num_maps; + const int lpm_res_counter_step_x2; + const u32 lpm_sts_latch_en_offset; const u32 lpm_en_offset; + const u32 lpm_priority_offset; const u32 lpm_residency_offset; const u32 lpm_status_offset; const u32 lpm_live_status_offset; + const u32 etr3_offset; }; /** @@ -278,6 +300,9 @@ struct pmc_reg_map { * @check_counters: On resume, check if counters are getting incremented * @pc10_counter: PC10 residency counter * @s0ix_counter: S0ix residency (step adjusted) + * @num_lpm_modes: Count of enabled modes + * @lpm_en_modes: Array of enabled modes from lowest to highest priority + * @lpm_req_regs: List of substate requirements * * pmc_dev contains info about power management controller device. */ @@ -292,6 +317,28 @@ struct pmc_dev { bool check_counters; /* Check for counter increments on resume */ u64 pc10_counter; u64 s0ix_counter; + int num_lpm_modes; + int lpm_en_modes[LPM_MAX_NUM_MODES]; + u32 *lpm_req_regs; }; +#define pmc_for_each_mode(i, mode, pmcdev) \ + for (i = 0, mode = pmcdev->lpm_en_modes[i]; \ + i < pmcdev->num_lpm_modes; \ + i++, mode = pmcdev->lpm_en_modes[i]) + +#define DEFINE_PMC_CORE_ATTR_WRITE(__name) \ +static int __name ## _open(struct inode *inode, struct file *file) \ +{ \ + return single_open(file, __name ## _show, inode->i_private); \ +} \ + \ +static const struct file_operations __name ## _fops = { \ + .owner = THIS_MODULE, \ + .open = __name ## _open, \ + .read = seq_read, \ + .write = __name ## _write, \ + .release = single_release, \ +} + #endif /* PMC_CORE_H */ |