diff options
Diffstat (limited to 'drivers/pmdomain/renesas')
| -rw-r--r-- | drivers/pmdomain/renesas/r8a77960-sysc.c | 6 | ||||
| -rw-r--r-- | drivers/pmdomain/renesas/rcar-sysc.c | 4 | ||||
| -rw-r--r-- | drivers/pmdomain/renesas/rcar-sysc.h | 1 |
3 files changed, 9 insertions, 2 deletions
diff --git a/drivers/pmdomain/renesas/r8a77960-sysc.c b/drivers/pmdomain/renesas/r8a77960-sysc.c index e6f2c3f96125..2ab3f565d2b0 100644 --- a/drivers/pmdomain/renesas/r8a77960-sysc.c +++ b/drivers/pmdomain/renesas/r8a77960-sysc.c @@ -32,12 +32,14 @@ static const struct rcar_sysc_area r8a77960_areas[] __initconst = { { "ca53-cpu3", 0x200, 3, R8A7796_PD_CA53_CPU3, R8A7796_PD_CA53_SCU, PD_CPU_NOCR }, { "cr7", 0x240, 0, R8A7796_PD_CR7, R8A7796_PD_ALWAYS_ON }, - { "a3vc", 0x380, 0, R8A7796_PD_A3VC, R8A7796_PD_ALWAYS_ON }, + { "a3vc", 0x380, 0, R8A7796_PD_A3VC, R8A7796_PD_ALWAYS_ON, + PD_OFF_DELAY }, { "a2vc0", 0x3c0, 0, R8A7796_PD_A2VC0, R8A7796_PD_A3VC }, { "a2vc1", 0x3c0, 1, R8A7796_PD_A2VC1, R8A7796_PD_A3VC }, { "3dg-a", 0x100, 0, R8A7796_PD_3DG_A, R8A7796_PD_ALWAYS_ON }, { "3dg-b", 0x100, 1, R8A7796_PD_3DG_B, R8A7796_PD_3DG_A }, - { "a3ir", 0x180, 0, R8A7796_PD_A3IR, R8A7796_PD_ALWAYS_ON }, + { "a3ir", 0x180, 0, R8A7796_PD_A3IR, R8A7796_PD_ALWAYS_ON, + PD_OFF_DELAY }, }; diff --git a/drivers/pmdomain/renesas/rcar-sysc.c b/drivers/pmdomain/renesas/rcar-sysc.c index a9d92e38fcee..b99326917330 100644 --- a/drivers/pmdomain/renesas/rcar-sysc.c +++ b/drivers/pmdomain/renesas/rcar-sysc.c @@ -90,6 +90,10 @@ static int rcar_sysc_pwr_on_off(const struct rcar_sysc_pd *pd, bool on) if (ret) return -EAGAIN; + /* Power-off delay quirk */ + if (!on && (pd->flags & PD_OFF_DELAY)) + udelay(1); + /* Submit power shutoff or power resume request */ iowrite32(BIT(pd->chan_bit), rcar_sysc_base + pd->chan_offs + reg_offs); diff --git a/drivers/pmdomain/renesas/rcar-sysc.h b/drivers/pmdomain/renesas/rcar-sysc.h index 8c4ec36ed7da..07ffce310686 100644 --- a/drivers/pmdomain/renesas/rcar-sysc.h +++ b/drivers/pmdomain/renesas/rcar-sysc.h @@ -16,6 +16,7 @@ #define PD_CPU BIT(0) /* Area contains main CPU core */ #define PD_SCU BIT(1) /* Area contains SCU and L2 cache */ #define PD_NO_CR BIT(2) /* Area lacks PWR{ON,OFF}CR registers */ +#define PD_OFF_DELAY BIT(3) /* Area is subject to power-off delay quirk */ #define PD_CPU_CR PD_CPU /* CPU area has CR (R-Car H1) */ #define PD_CPU_NOCR PD_CPU | PD_NO_CR /* CPU area lacks CR (R-Car Gen2/3) */ |