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path: root/drivers/staging/vt6655/baseband.c
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Diffstat (limited to 'drivers/staging/vt6655/baseband.c')
-rw-r--r--drivers/staging/vt6655/baseband.c86
1 files changed, 43 insertions, 43 deletions
diff --git a/drivers/staging/vt6655/baseband.c b/drivers/staging/vt6655/baseband.c
index 696d4dd03aa2..f7824396c5ff 100644
--- a/drivers/staging/vt6655/baseband.c
+++ b/drivers/staging/vt6655/baseband.c
@@ -761,7 +761,7 @@ static const unsigned char vt3253b0_rfmd[CB_VT3253B0_INIT_FOR_RFMD][2] = {
#define CB_VT3253B0_AGC_FOR_RFMD2959 195
/* For RFMD2959 */
static
-unsigned char byVT3253B0_AGC4_RFMD2959[CB_VT3253B0_AGC_FOR_RFMD2959][2] = {
+unsigned char vt3253b0_agc4_rfmd2959[CB_VT3253B0_AGC_FOR_RFMD2959][2] = {
{0xF0, 0x00},
{0xF1, 0x3E},
{0xF0, 0x80},
@@ -962,7 +962,7 @@ unsigned char byVT3253B0_AGC4_RFMD2959[CB_VT3253B0_AGC_FOR_RFMD2959][2] = {
#define CB_VT3253B0_INIT_FOR_AIROHA2230 256
/* For AIROHA */
static
-unsigned char byVT3253B0_AIROHA2230[CB_VT3253B0_INIT_FOR_AIROHA2230][2] = {
+unsigned char vt3253b0_airoha2230[CB_VT3253B0_INIT_FOR_AIROHA2230][2] = {
{0x00, 0x31},
{0x01, 0x00},
{0x02, 0x00},
@@ -1223,7 +1223,7 @@ unsigned char byVT3253B0_AIROHA2230[CB_VT3253B0_INIT_FOR_AIROHA2230][2] = {
#define CB_VT3253B0_INIT_FOR_UW2451 256
/* For UW2451 */
-static unsigned char byVT3253B0_UW2451[CB_VT3253B0_INIT_FOR_UW2451][2] = {
+static unsigned char vt3253b0_uw2451[CB_VT3253B0_INIT_FOR_UW2451][2] = {
{0x00, 0x31},
{0x01, 0x00},
{0x02, 0x00},
@@ -1484,7 +1484,7 @@ static unsigned char byVT3253B0_UW2451[CB_VT3253B0_INIT_FOR_UW2451][2] = {
#define CB_VT3253B0_AGC 193
/* For AIROHA */
-static unsigned char byVT3253B0_AGC[CB_VT3253B0_AGC][2] = {
+static unsigned char vt3253b0_agc[CB_VT3253B0_AGC][2] = {
{0xF0, 0x00},
{0xF1, 0x00},
{0xF0, 0x80},
@@ -1979,7 +1979,7 @@ bool bb_write_embedded(struct vnt_private *priv, unsigned char by_bb_addr,
* In:
* iobase - I/O base address
* byRevId - Revision ID
- * byRFType - RF type
+ * rf_type - RF type
* Out:
* none
*
@@ -1992,10 +1992,10 @@ bool bb_vt3253_init(struct vnt_private *priv)
bool result = true;
int ii;
void __iomem *iobase = priv->port_offset;
- unsigned char by_rf_type = priv->byRFType;
+ unsigned char rf_type = priv->rf_type;
unsigned char by_local_id = priv->local_id;
- if (by_rf_type == RF_RFMD2959) {
+ if (rf_type == RF_RFMD2959) {
if (by_local_id <= REV_ID_VT3253_A1) {
for (ii = 0; ii < CB_VT3253_INIT_FOR_RFMD; ii++)
result &= bb_write_embedded(priv,
@@ -2010,74 +2010,74 @@ bool bb_vt3253_init(struct vnt_private *priv)
for (ii = 0; ii < CB_VT3253B0_AGC_FOR_RFMD2959; ii++)
result &= bb_write_embedded(priv,
- byVT3253B0_AGC4_RFMD2959[ii][0],
- byVT3253B0_AGC4_RFMD2959[ii][1]);
+ vt3253b0_agc4_rfmd2959[ii][0],
+ vt3253b0_agc4_rfmd2959[ii][1]);
iowrite32(0x23, iobase + MAC_REG_ITRTMSET);
vt6655_mac_reg_bits_on(iobase, MAC_REG_PAPEDELAY, BIT(0));
}
- priv->abyBBVGA[0] = 0x18;
- priv->abyBBVGA[1] = 0x0A;
- priv->abyBBVGA[2] = 0x0;
- priv->abyBBVGA[3] = 0x0;
+ priv->bbvga[0] = 0x18;
+ priv->bbvga[1] = 0x0A;
+ priv->bbvga[2] = 0x0;
+ priv->bbvga[3] = 0x0;
priv->dbm_threshold[0] = -70;
priv->dbm_threshold[1] = -50;
priv->dbm_threshold[2] = 0;
priv->dbm_threshold[3] = 0;
- } else if ((by_rf_type == RF_AIROHA) || (by_rf_type == RF_AL2230S)) {
+ } else if ((rf_type == RF_AIROHA) || (rf_type == RF_AL2230S)) {
for (ii = 0; ii < CB_VT3253B0_INIT_FOR_AIROHA2230; ii++)
result &= bb_write_embedded(priv,
- byVT3253B0_AIROHA2230[ii][0],
- byVT3253B0_AIROHA2230[ii][1]);
+ vt3253b0_airoha2230[ii][0],
+ vt3253b0_airoha2230[ii][1]);
for (ii = 0; ii < CB_VT3253B0_AGC; ii++)
result &= bb_write_embedded(priv,
- byVT3253B0_AGC[ii][0], byVT3253B0_AGC[ii][1]);
+ vt3253b0_agc[ii][0], vt3253b0_agc[ii][1]);
- priv->abyBBVGA[0] = 0x1C;
- priv->abyBBVGA[1] = 0x10;
- priv->abyBBVGA[2] = 0x0;
- priv->abyBBVGA[3] = 0x0;
+ priv->bbvga[0] = 0x1C;
+ priv->bbvga[1] = 0x10;
+ priv->bbvga[2] = 0x0;
+ priv->bbvga[3] = 0x0;
priv->dbm_threshold[0] = -70;
priv->dbm_threshold[1] = -48;
priv->dbm_threshold[2] = 0;
priv->dbm_threshold[3] = 0;
- } else if (by_rf_type == RF_UW2451) {
+ } else if (rf_type == RF_UW2451) {
for (ii = 0; ii < CB_VT3253B0_INIT_FOR_UW2451; ii++)
result &= bb_write_embedded(priv,
- byVT3253B0_UW2451[ii][0],
- byVT3253B0_UW2451[ii][1]);
+ vt3253b0_uw2451[ii][0],
+ vt3253b0_uw2451[ii][1]);
for (ii = 0; ii < CB_VT3253B0_AGC; ii++)
result &= bb_write_embedded(priv,
- byVT3253B0_AGC[ii][0],
- byVT3253B0_AGC[ii][1]);
+ vt3253b0_agc[ii][0],
+ vt3253b0_agc[ii][1]);
iowrite8(0x23, iobase + MAC_REG_ITRTMSET);
vt6655_mac_reg_bits_on(iobase, MAC_REG_PAPEDELAY, BIT(0));
- priv->abyBBVGA[0] = 0x14;
- priv->abyBBVGA[1] = 0x0A;
- priv->abyBBVGA[2] = 0x0;
- priv->abyBBVGA[3] = 0x0;
+ priv->bbvga[0] = 0x14;
+ priv->bbvga[1] = 0x0A;
+ priv->bbvga[2] = 0x0;
+ priv->bbvga[3] = 0x0;
priv->dbm_threshold[0] = -60;
priv->dbm_threshold[1] = -50;
priv->dbm_threshold[2] = 0;
priv->dbm_threshold[3] = 0;
- } else if (by_rf_type == RF_VT3226) {
+ } else if (rf_type == RF_VT3226) {
for (ii = 0; ii < CB_VT3253B0_INIT_FOR_AIROHA2230; ii++)
result &= bb_write_embedded(priv,
- byVT3253B0_AIROHA2230[ii][0],
- byVT3253B0_AIROHA2230[ii][1]);
+ vt3253b0_airoha2230[ii][0],
+ vt3253b0_airoha2230[ii][1]);
for (ii = 0; ii < CB_VT3253B0_AGC; ii++)
result &= bb_write_embedded(priv,
- byVT3253B0_AGC[ii][0], byVT3253B0_AGC[ii][1]);
+ vt3253b0_agc[ii][0], vt3253b0_agc[ii][1]);
- priv->abyBBVGA[0] = 0x1C;
- priv->abyBBVGA[1] = 0x10;
- priv->abyBBVGA[2] = 0x0;
- priv->abyBBVGA[3] = 0x0;
+ priv->bbvga[0] = 0x1C;
+ priv->bbvga[1] = 0x10;
+ priv->bbvga[2] = 0x0;
+ priv->bbvga[3] = 0x0;
priv->dbm_threshold[0] = -70;
priv->dbm_threshold[1] = -48;
priv->dbm_threshold[2] = 0;
@@ -2087,8 +2087,8 @@ bool bb_vt3253_init(struct vnt_private *priv)
/* {{ RobertYu: 20050104 */
} else {
/* No VGA Table now */
- priv->bUpdateBBVGA = false;
- priv->abyBBVGA[0] = 0x1C;
+ priv->update_bbvga = false;
+ priv->bbvga[0] = 0x1C;
}
if (by_local_id > REV_ID_VT3253_A1) {
@@ -2126,7 +2126,7 @@ bb_set_short_slot_time(struct vnt_private *priv)
/* patch for 3253B0 Baseband with Cardbus module */
bb_read_embedded(priv, 0xE7, &by_bb_vga);
- if (by_bb_vga == priv->abyBBVGA[0])
+ if (by_bb_vga == priv->bbvga[0])
by_bb_rx_conf |= 0x20; /* 0010 0000 */
bb_write_embedded(priv, 0x0A, by_bb_rx_conf); /* CR10 */
@@ -2140,13 +2140,13 @@ void bb_set_vga_gain_offset(struct vnt_private *priv, unsigned char by_data)
bb_read_embedded(priv, 0x0A, &by_bb_rx_conf); /* CR10 */
/* patch for 3253B0 Baseband with Cardbus module */
- if (by_data == priv->abyBBVGA[0])
+ if (by_data == priv->bbvga[0])
by_bb_rx_conf |= 0x20; /* 0010 0000 */
else if (priv->short_slot_time)
by_bb_rx_conf &= 0xDF; /* 1101 1111 */
else
by_bb_rx_conf |= 0x20; /* 0010 0000 */
- priv->byBBVGACurrent = by_data;
+ priv->bbvga_current = by_data;
bb_write_embedded(priv, 0x0A, by_bb_rx_conf); /* CR10 */
}
generated by cgit v1.2.3 (git 2.39.0) at 2024-07-13 08:19:23 +0300