diff options
Diffstat (limited to 'include/dt-bindings')
| -rw-r--r-- | include/dt-bindings/clock/ast2600-clock.h | 1 | ||||
| -rw-r--r-- | include/dt-bindings/clock/exynos850.h | 54 | ||||
| -rw-r--r-- | include/dt-bindings/clock/microchip,mpfs-clock.h | 5 | ||||
| -rw-r--r-- | include/dt-bindings/clock/mobileye,eyeq5-clk.h | 22 | ||||
| -rw-r--r-- | include/dt-bindings/clock/qcom,gcc-sm8150.h | 3 | ||||
| -rw-r--r-- | include/dt-bindings/clock/r8a779g0-cpg-mssr.h | 1 | ||||
| -rw-r--r-- | include/dt-bindings/interconnect/qcom,msm8909.h | 93 | ||||
| -rw-r--r-- | include/dt-bindings/interconnect/qcom,sm7150-rpmh.h | 150 | ||||
| -rw-r--r-- | include/dt-bindings/interconnect/qcom,x1e80100-rpmh.h | 24 | ||||
| -rw-r--r-- | include/dt-bindings/leds/common.h | 4 | ||||
| -rw-r--r-- | include/dt-bindings/power/amlogic,c3-pwrc.h | 2 | ||||
| -rw-r--r-- | include/dt-bindings/power/qcom-rpmpd.h | 7 | ||||
| -rw-r--r-- | include/dt-bindings/reset/mediatek,mt7988-resets.h | 6 | ||||
| -rw-r--r-- | include/dt-bindings/reset/sophgo,sg2042-reset.h | 87 |
14 files changed, 434 insertions, 25 deletions
diff --git a/include/dt-bindings/clock/ast2600-clock.h b/include/dt-bindings/clock/ast2600-clock.h index 712782177c90..7ae96c7bd72f 100644 --- a/include/dt-bindings/clock/ast2600-clock.h +++ b/include/dt-bindings/clock/ast2600-clock.h @@ -86,6 +86,7 @@ #define ASPEED_CLK_MAC3RCLK 69 #define ASPEED_CLK_MAC4RCLK 70 #define ASPEED_CLK_I3C 71 +#define ASPEED_CLK_FSI 72 /* Only list resets here that are not part of a clock gate + reset pair */ #define ASPEED_RESET_ADC 55 diff --git a/include/dt-bindings/clock/exynos850.h b/include/dt-bindings/clock/exynos850.h index bc15108aa3c2..7666241520f8 100644 --- a/include/dt-bindings/clock/exynos850.h +++ b/include/dt-bindings/clock/exynos850.h @@ -88,6 +88,18 @@ #define CLK_MOUT_G3D_SWITCH 76 #define CLK_GOUT_G3D_SWITCH 77 #define CLK_DOUT_G3D_SWITCH 78 +#define CLK_MOUT_CPUCL0_DBG 79 +#define CLK_MOUT_CPUCL0_SWITCH 80 +#define CLK_GOUT_CPUCL0_DBG 81 +#define CLK_GOUT_CPUCL0_SWITCH 82 +#define CLK_DOUT_CPUCL0_DBG 83 +#define CLK_DOUT_CPUCL0_SWITCH 84 +#define CLK_MOUT_CPUCL1_DBG 85 +#define CLK_MOUT_CPUCL1_SWITCH 86 +#define CLK_GOUT_CPUCL1_DBG 87 +#define CLK_GOUT_CPUCL1_SWITCH 88 +#define CLK_DOUT_CPUCL1_DBG 89 +#define CLK_DOUT_CPUCL1_SWITCH 90 /* CMU_APM */ #define CLK_RCO_I3C_PMIC 1 @@ -195,6 +207,48 @@ #define CLK_GOUT_CMGP_USI1_PCLK 14 #define CLK_GOUT_SYSREG_CMGP_PCLK 15 +/* CMU_CPUCL0 */ +#define CLK_FOUT_CPUCL0_PLL 1 +#define CLK_MOUT_PLL_CPUCL0 2 +#define CLK_MOUT_CPUCL0_SWITCH_USER 3 +#define CLK_MOUT_CPUCL0_DBG_USER 4 +#define CLK_MOUT_CPUCL0_PLL 5 +#define CLK_DOUT_CPUCL0_CPU 6 +#define CLK_DOUT_CPUCL0_CMUREF 7 +#define CLK_DOUT_CPUCL0_PCLK 8 +#define CLK_DOUT_CLUSTER0_ACLK 9 +#define CLK_DOUT_CLUSTER0_ATCLK 10 +#define CLK_DOUT_CLUSTER0_PCLKDBG 11 +#define CLK_DOUT_CLUSTER0_PERIPHCLK 12 +#define CLK_GOUT_CLUSTER0_ATCLK 13 +#define CLK_GOUT_CLUSTER0_PCLK 14 +#define CLK_GOUT_CLUSTER0_PERIPHCLK 15 +#define CLK_GOUT_CLUSTER0_SCLK 16 +#define CLK_GOUT_CPUCL0_CMU_CPUCL0_PCLK 17 +#define CLK_GOUT_CLUSTER0_CPU 18 +#define CLK_CLUSTER0_SCLK 19 + +/* CMU_CPUCL1 */ +#define CLK_FOUT_CPUCL1_PLL 1 +#define CLK_MOUT_PLL_CPUCL1 2 +#define CLK_MOUT_CPUCL1_SWITCH_USER 3 +#define CLK_MOUT_CPUCL1_DBG_USER 4 +#define CLK_MOUT_CPUCL1_PLL 5 +#define CLK_DOUT_CPUCL1_CPU 6 +#define CLK_DOUT_CPUCL1_CMUREF 7 +#define CLK_DOUT_CPUCL1_PCLK 8 +#define CLK_DOUT_CLUSTER1_ACLK 9 +#define CLK_DOUT_CLUSTER1_ATCLK 10 +#define CLK_DOUT_CLUSTER1_PCLKDBG 11 +#define CLK_DOUT_CLUSTER1_PERIPHCLK 12 +#define CLK_GOUT_CLUSTER1_ATCLK 13 +#define CLK_GOUT_CLUSTER1_PCLK 14 +#define CLK_GOUT_CLUSTER1_PERIPHCLK 15 +#define CLK_GOUT_CLUSTER1_SCLK 16 +#define CLK_GOUT_CPUCL1_CMU_CPUCL1_PCLK 17 +#define CLK_GOUT_CLUSTER1_CPU 18 +#define CLK_CLUSTER1_SCLK 19 + /* CMU_G3D */ #define CLK_FOUT_G3D_PLL 1 #define CLK_MOUT_G3D_PLL 2 diff --git a/include/dt-bindings/clock/microchip,mpfs-clock.h b/include/dt-bindings/clock/microchip,mpfs-clock.h index 79775a5134ca..b52f19a2b480 100644 --- a/include/dt-bindings/clock/microchip,mpfs-clock.h +++ b/include/dt-bindings/clock/microchip,mpfs-clock.h @@ -44,6 +44,11 @@ #define CLK_RTCREF 33 #define CLK_MSSPLL 34 +#define CLK_MSSPLL0 34 +#define CLK_MSSPLL1 35 +#define CLK_MSSPLL2 36 +#define CLK_MSSPLL3 37 +/* 38 is reserved for MSS PLL internals */ /* Clock Conditioning Circuitry Clock IDs */ diff --git a/include/dt-bindings/clock/mobileye,eyeq5-clk.h b/include/dt-bindings/clock/mobileye,eyeq5-clk.h new file mode 100644 index 000000000000..26d8930335e4 --- /dev/null +++ b/include/dt-bindings/clock/mobileye,eyeq5-clk.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (C) 2024 Mobileye Vision Technologies Ltd. + */ + +#ifndef _DT_BINDINGS_CLOCK_MOBILEYE_EYEQ5_CLK_H +#define _DT_BINDINGS_CLOCK_MOBILEYE_EYEQ5_CLK_H + +#define EQ5C_PLL_CPU 0 +#define EQ5C_PLL_VMP 1 +#define EQ5C_PLL_PMA 2 +#define EQ5C_PLL_VDI 3 +#define EQ5C_PLL_DDR0 4 +#define EQ5C_PLL_PCI 5 +#define EQ5C_PLL_PER 6 +#define EQ5C_PLL_PMAC 7 +#define EQ5C_PLL_MPC 8 +#define EQ5C_PLL_DDR1 9 + +#define EQ5C_DIV_OSPI 10 + +#endif diff --git a/include/dt-bindings/clock/qcom,gcc-sm8150.h b/include/dt-bindings/clock/qcom,gcc-sm8150.h index dfefd5e8bf6e..921a33f24d33 100644 --- a/include/dt-bindings/clock/qcom,gcc-sm8150.h +++ b/include/dt-bindings/clock/qcom,gcc-sm8150.h @@ -239,6 +239,9 @@ #define GCC_USB30_PRIM_BCR 26 #define GCC_USB30_SEC_BCR 27 #define GCC_USB_PHY_CFG_AHB2PHY_BCR 28 +#define GCC_VIDEO_AXIC_CLK_BCR 29 +#define GCC_VIDEO_AXI0_CLK_BCR 30 +#define GCC_VIDEO_AXI1_CLK_BCR 31 /* GCC GDSCRs */ #define PCIE_0_GDSC 0 diff --git a/include/dt-bindings/clock/r8a779g0-cpg-mssr.h b/include/dt-bindings/clock/r8a779g0-cpg-mssr.h index 754c54a6eb06..7850cdc62e28 100644 --- a/include/dt-bindings/clock/r8a779g0-cpg-mssr.h +++ b/include/dt-bindings/clock/r8a779g0-cpg-mssr.h @@ -86,5 +86,6 @@ #define R8A779G0_CLK_CPEX 74 #define R8A779G0_CLK_CBFUSA 75 #define R8A779G0_CLK_R 76 +#define R8A779G0_CLK_CP 77 #endif /* __DT_BINDINGS_CLOCK_R8A779G0_CPG_MSSR_H__ */ diff --git a/include/dt-bindings/interconnect/qcom,msm8909.h b/include/dt-bindings/interconnect/qcom,msm8909.h new file mode 100644 index 000000000000..76365d8aec21 --- /dev/null +++ b/include/dt-bindings/interconnect/qcom,msm8909.h @@ -0,0 +1,93 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Qualcomm MSM8909 interconnect IDs + */ + +#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_MSM8909_H +#define __DT_BINDINGS_INTERCONNECT_QCOM_MSM8909_H + +/* BIMC fabric */ +#define MAS_APPS_PROC 0 +#define MAS_OXILI 1 +#define MAS_SNOC_BIMC_0 2 +#define MAS_SNOC_BIMC_1 3 +#define MAS_TCU_0 4 +#define MAS_TCU_1 5 +#define SLV_EBI 6 +#define SLV_BIMC_SNOC 7 + +/* PCNOC fabric */ +#define MAS_AUDIO 0 +#define MAS_SPDM 1 +#define MAS_DEHR 2 +#define MAS_QPIC 3 +#define MAS_BLSP_1 4 +#define MAS_USB_HS 5 +#define MAS_CRYPTO 6 +#define MAS_SDCC_1 7 +#define MAS_SDCC_2 8 +#define MAS_SNOC_PCNOC 9 +#define PCNOC_M_0 10 +#define PCNOC_M_1 11 +#define PCNOC_INT_0 12 +#define PCNOC_INT_1 13 +#define PCNOC_S_0 14 +#define PCNOC_S_1 15 +#define PCNOC_S_2 16 +#define PCNOC_S_3 17 +#define PCNOC_S_4 18 +#define PCNOC_S_5 19 +#define PCNOC_S_7 20 +#define SLV_TCSR 21 +#define SLV_SDCC_1 22 +#define SLV_BLSP_1 23 +#define SLV_CRYPTO_0_CFG 24 +#define SLV_MESSAGE_RAM 25 +#define SLV_PDM 26 +#define SLV_PRNG 27 +#define SLV_USB_HS 28 +#define SLV_QPIC 29 +#define SLV_SPDM 30 +#define SLV_SDCC_2 31 +#define SLV_AUDIO 32 +#define SLV_DEHR_CFG 33 +#define SLV_SNOC_CFG 34 +#define SLV_QDSS_CFG 35 +#define SLV_USB_PHY 36 +#define SLV_CAMERA_SS_CFG 37 +#define SLV_DISP_SS_CFG 38 +#define SLV_VENUS_CFG 39 +#define SLV_TLMM 40 +#define SLV_GPU_CFG 41 +#define SLV_IMEM_CFG 42 +#define SLV_BIMC_CFG 43 +#define SLV_PMIC_ARB 44 +#define SLV_TCU 45 +#define SLV_PCNOC_SNOC 46 + +/* SNOC fabric */ +#define MAS_QDSS_BAM 0 +#define MAS_BIMC_SNOC 1 +#define MAS_MDP 2 +#define MAS_PCNOC_SNOC 3 +#define MAS_VENUS 4 +#define MAS_VFE 5 +#define MAS_QDSS_ETR 6 +#define MM_INT_0 7 +#define MM_INT_1 8 +#define MM_INT_2 9 +#define MM_INT_BIMC 10 +#define QDSS_INT 11 +#define SNOC_INT_0 12 +#define SNOC_INT_1 13 +#define SNOC_INT_BIMC 14 +#define SLV_KPSS_AHB 15 +#define SLV_SNOC_BIMC_0 16 +#define SLV_SNOC_BIMC_1 17 +#define SLV_IMEM 18 +#define SLV_SNOC_PCNOC 19 +#define SLV_QDSS_STM 20 +#define SLV_CATS_0 21 +#define SLV_CATS_1 22 + +#endif /* __DT_BINDINGS_INTERCONNECT_QCOM_MSM8909_H */ diff --git a/include/dt-bindings/interconnect/qcom,sm7150-rpmh.h b/include/dt-bindings/interconnect/qcom,sm7150-rpmh.h new file mode 100644 index 000000000000..1f610eb832aa --- /dev/null +++ b/include/dt-bindings/interconnect/qcom,sm7150-rpmh.h @@ -0,0 +1,150 @@ +/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */ +/* + * Qualcomm SM7150 interconnect IDs + * + * Copyright (c) 2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2024, Danila Tikhonov <danila@jiaxyga.com> + */ + +#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_SM7150_H +#define __DT_BINDINGS_INTERCONNECT_QCOM_SM7150_H + +#define MASTER_A1NOC_CFG 0 +#define MASTER_QUP_0 1 +#define MASTER_TSIF 2 +#define MASTER_EMMC 3 +#define MASTER_SDCC_2 4 +#define MASTER_SDCC_4 5 +#define MASTER_UFS_MEM 6 +#define A1NOC_SNOC_SLV 7 +#define SLAVE_SERVICE_A1NOC 8 + +#define MASTER_A2NOC_CFG 0 +#define MASTER_QDSS_BAM 1 +#define MASTER_QUP_1 2 +#define MASTER_CNOC_A2NOC 3 +#define MASTER_CRYPTO_CORE_0 4 +#define MASTER_IPA 5 +#define MASTER_PCIE 6 +#define MASTER_QDSS_ETR 7 +#define MASTER_USB3 8 +#define A2NOC_SNOC_SLV 9 +#define SLAVE_ANOC_PCIE_GEM_NOC 10 +#define SLAVE_SERVICE_A2NOC 11 + +#define MASTER_CAMNOC_HF0_UNCOMP 0 +#define MASTER_CAMNOC_RT_UNCOMP 1 +#define MASTER_CAMNOC_SF_UNCOMP 2 +#define MASTER_CAMNOC_NRT_UNCOMP 3 +#define SLAVE_CAMNOC_UNCOMP 4 + +#define MASTER_NPU 0 +#define SLAVE_CDSP_GEM_NOC 1 + +#define MASTER_SPDM 0 +#define SNOC_CNOC_MAS 1 +#define MASTER_QDSS_DAP 2 +#define SLAVE_A1NOC_CFG 3 +#define SLAVE_A2NOC_CFG 4 +#define SLAVE_AHB2PHY_NORTH 5 +#define SLAVE_AHB2PHY_SOUTH 6 +#define SLAVE_AHB2PHY_WEST 7 +#define SLAVE_AOP 8 +#define SLAVE_AOSS 9 +#define SLAVE_CAMERA_CFG 10 +#define SLAVE_CAMERA_NRT_THROTTLE_CFG 11 +#define SLAVE_CAMERA_RT_THROTTLE_CFG 12 +#define SLAVE_CLK_CTL 13 +#define SLAVE_CDSP_CFG 14 +#define SLAVE_RBCPR_CX_CFG 15 +#define SLAVE_RBCPR_MX_CFG 16 +#define SLAVE_CRYPTO_0_CFG 17 +#define SLAVE_CNOC_DDRSS 18 +#define SLAVE_DISPLAY_CFG 19 +#define SLAVE_DISPLAY_THROTTLE_CFG 20 +#define SLAVE_EMMC_CFG 21 +#define SLAVE_GLM 22 +#define SLAVE_GRAPHICS_3D_CFG 23 +#define SLAVE_IMEM_CFG 24 +#define SLAVE_IPA_CFG 25 +#define SLAVE_CNOC_MNOC_CFG 26 +#define SLAVE_PCIE_CFG 27 +#define SLAVE_PDM 28 +#define SLAVE_PIMEM_CFG 29 +#define SLAVE_PRNG 30 +#define SLAVE_QDSS_CFG 31 +#define SLAVE_QUP_0 32 +#define SLAVE_QUP_1 33 +#define SLAVE_SDCC_2 34 +#define SLAVE_SDCC_4 35 +#define SLAVE_SNOC_CFG 36 +#define SLAVE_SPDM_WRAPPER 37 +#define SLAVE_TCSR 38 +#define SLAVE_TLMM_NORTH 39 +#define SLAVE_TLMM_SOUTH 40 +#define SLAVE_TLMM_WEST 41 +#define SLAVE_TSIF 42 +#define SLAVE_UFS_MEM_CFG 43 +#define SLAVE_USB3 44 +#define SLAVE_VENUS_CFG 45 +#define SLAVE_VENUS_CVP_THROTTLE_CFG 46 +#define SLAVE_VENUS_THROTTLE_CFG 47 +#define SLAVE_VSENSE_CTRL_CFG 48 +#define SLAVE_CNOC_A2NOC 49 +#define SLAVE_SERVICE_CNOC 50 + +#define MASTER_CNOC_DC_NOC 0 +#define SLAVE_GEM_NOC_CFG 1 +#define SLAVE_LLCC_CFG 2 + +#define MASTER_AMPSS_M0 0 +#define MASTER_SYS_TCU 1 +#define MASTER_GEM_NOC_CFG 2 +#define MASTER_COMPUTE_NOC 3 +#define MASTER_MNOC_HF_MEM_NOC 4 +#define MASTER_MNOC_SF_MEM_NOC 5 +#define MASTER_GEM_NOC_PCIE_SNOC 6 +#define MASTER_SNOC_GC_MEM_NOC 7 +#define MASTER_SNOC_SF_MEM_NOC 8 +#define MASTER_GRAPHICS_3D 9 +#define SLAVE_MSS_PROC_MS_MPU_CFG 10 +#define SLAVE_GEM_NOC_SNOC 11 +#define SLAVE_LLCC 12 +#define SLAVE_SERVICE_GEM_NOC 13 + + +#define MASTER_LLCC 0 +#define SLAVE_EBI_CH0 1 + +#define MASTER_CNOC_MNOC_CFG 0 +#define MASTER_CAMNOC_HF0 1 +#define MASTER_CAMNOC_NRT 2 +#define MASTER_CAMNOC_RT 3 +#define MASTER_CAMNOC_SF 4 +#define MASTER_MDP_PORT0 5 +#define MASTER_MDP_PORT1 6 +#define MASTER_ROTATOR 7 +#define MASTER_VIDEO_P0 8 +#define MASTER_VIDEO_P1 9 +#define MASTER_VIDEO_PROC 10 +#define SLAVE_MNOC_SF_MEM_NOC 11 +#define SLAVE_MNOC_HF_MEM_NOC 12 +#define SLAVE_SERVICE_MNOC 13 + +#define MASTER_SNOC_CFG 0 +#define A1NOC_SNOC_MAS 1 +#define A2NOC_SNOC_MAS 2 +#define MASTER_GEM_NOC_SNOC 3 +#define MASTER_PIMEM 4 +#define MASTER_GIC 5 +#define SLAVE_APPSS 6 +#define SNOC_CNOC_SLV 7 +#define SLAVE_SNOC_GEM_NOC_GC 8 +#define SLAVE_SNOC_GEM_NOC_SF 9 +#define SLAVE_OCIMEM 10 +#define SLAVE_PIMEM 11 +#define SLAVE_SERVICE_SNOC 12 +#define SLAVE_QDSS_STM 13 +#define SLAVE_TCU 14 + +#endif diff --git a/include/dt-bindings/interconnect/qcom,x1e80100-rpmh.h b/include/dt-bindings/interconnect/qcom,x1e80100-rpmh.h index a38c3472698a..7d9710881149 100644 --- a/include/dt-bindings/interconnect/qcom,x1e80100-rpmh.h +++ b/include/dt-bindings/interconnect/qcom,x1e80100-rpmh.h @@ -112,11 +112,6 @@ #define SLAVE_GEM_NOC_CNOC 12 #define SLAVE_LLCC 13 #define SLAVE_MEM_NOC_PCIE_SNOC 14 -#define MASTER_MNOC_HF_MEM_NOC_DISP 15 -#define MASTER_ANOC_PCIE_GEM_NOC_DISP 16 -#define SLAVE_LLCC_DISP 17 -#define MASTER_ANOC_PCIE_GEM_NOC_PCIE 18 -#define SLAVE_LLCC_PCIE 19 #define MASTER_LPIAON_NOC 0 #define SLAVE_LPASS_GEM_NOC 1 @@ -129,10 +124,6 @@ #define MASTER_LLCC 0 #define SLAVE_EBI1 1 -#define MASTER_LLCC_DISP 2 -#define SLAVE_EBI1_DISP 3 -#define MASTER_LLCC_PCIE 4 -#define SLAVE_EBI1_PCIE 5 #define MASTER_AV1_ENC 0 #define MASTER_CAMNOC_HF 1 @@ -147,8 +138,6 @@ #define SLAVE_MNOC_HF_MEM_NOC 10 #define SLAVE_MNOC_SF_MEM_NOC 11 #define SLAVE_SERVICE_MNOC 12 -#define MASTER_MDP_DISP 13 -#define SLAVE_MNOC_HF_MEM_NOC_DISP 14 #define MASTER_CDSP_PROC 0 #define SLAVE_CDSP_MEM_NOC 1 @@ -156,18 +145,11 @@ #define MASTER_PCIE_NORTH 0 #define MASTER_PCIE_SOUTH 1 #define SLAVE_ANOC_PCIE_GEM_NOC 2 -#define MASTER_PCIE_NORTH_PCIE 3 -#define MASTER_PCIE_SOUTH_PCIE 4 -#define SLAVE_ANOC_PCIE_GEM_NOC_PCIE 5 #define MASTER_PCIE_3 0 #define MASTER_PCIE_4 1 #define MASTER_PCIE_5 2 #define SLAVE_PCIE_NORTH 3 -#define MASTER_PCIE_3_PCIE 4 -#define MASTER_PCIE_4_PCIE 5 -#define MASTER_PCIE_5_PCIE 6 -#define SLAVE_PCIE_NORTH_PCIE 7 #define MASTER_PCIE_0 0 #define MASTER_PCIE_1 1 @@ -175,12 +157,6 @@ #define MASTER_PCIE_6A 3 #define MASTER_PCIE_6B 4 #define SLAVE_PCIE_SOUTH 5 -#define MASTER_PCIE_0_PCIE 6 -#define MASTER_PCIE_1_PCIE 7 -#define MASTER_PCIE_2_PCIE 8 -#define MASTER_PCIE_6A_PCIE 9 -#define MASTER_PCIE_6B_PCIE 10 -#define SLAVE_PCIE_SOUTH_PCIE 11 #define MASTER_A1NOC_SNOC 0 #define MASTER_A2NOC_SNOC 1 diff --git a/include/dt-bindings/leds/common.h b/include/dt-bindings/leds/common.h index 9a0d33d027ff..ecea167930d9 100644 --- a/include/dt-bindings/leds/common.h +++ b/include/dt-bindings/leds/common.h @@ -100,7 +100,11 @@ #define LED_FUNCTION_TX "tx" #define LED_FUNCTION_USB "usb" #define LED_FUNCTION_WAN "wan" +#define LED_FUNCTION_WAN_ONLINE "wan-online" #define LED_FUNCTION_WLAN "wlan" +#define LED_FUNCTION_WLAN_2GHZ "wlan-2ghz" +#define LED_FUNCTION_WLAN_5GHZ "wlan-5ghz" +#define LED_FUNCTION_WLAN_6GHZ "wlan-6ghz" #define LED_FUNCTION_WPS "wps" #endif /* __DT_BINDINGS_LEDS_H */ diff --git a/include/dt-bindings/power/amlogic,c3-pwrc.h b/include/dt-bindings/power/amlogic,c3-pwrc.h index 1d98a25b08a4..61759df4b2e7 100644 --- a/include/dt-bindings/power/amlogic,c3-pwrc.h +++ b/include/dt-bindings/power/amlogic,c3-pwrc.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ /* * Copyright (c) 2023 Amlogic, Inc. * Author: hongyu chen1 <hongyu.chen1@amlogic.com> diff --git a/include/dt-bindings/power/qcom-rpmpd.h b/include/dt-bindings/power/qcom-rpmpd.h index 7f4e2983a4c5..608087fb9a3d 100644 --- a/include/dt-bindings/power/qcom-rpmpd.h +++ b/include/dt-bindings/power/qcom-rpmpd.h @@ -308,6 +308,13 @@ #define MSM8953_VDDMX 5 #define MSM8953_VDDMX_AO 6 +/* MSM8974 Power Domain Indexes */ +#define MSM8974_VDDCX 0 +#define MSM8974_VDDCX_AO 1 +#define MSM8974_VDDCX_VFC 2 +#define MSM8974_VDDGFX 3 +#define MSM8974_VDDGFX_VFC 4 + /* MSM8976 Power Domain Indexes */ #define MSM8976_VDDCX 0 #define MSM8976_VDDCX_AO 1 diff --git a/include/dt-bindings/reset/mediatek,mt7988-resets.h b/include/dt-bindings/reset/mediatek,mt7988-resets.h index 493301971367..0eb152889a89 100644 --- a/include/dt-bindings/reset/mediatek,mt7988-resets.h +++ b/include/dt-bindings/reset/mediatek,mt7988-resets.h @@ -10,4 +10,10 @@ /* ETHWARP resets */ #define MT7988_ETHWARP_RST_SWITCH 0 +/* INFRA resets */ +#define MT7988_INFRA_RST0_PEXTP_MAC_SWRST 0 +#define MT7988_INFRA_RST1_THERM_CTRL_SWRST 1 + + #endif /* _DT_BINDINGS_RESET_CONTROLLER_MT7988 */ + diff --git a/include/dt-bindings/reset/sophgo,sg2042-reset.h b/include/dt-bindings/reset/sophgo,sg2042-reset.h new file mode 100644 index 000000000000..9ab0980625c1 --- /dev/null +++ b/include/dt-bindings/reset/sophgo,sg2042-reset.h @@ -0,0 +1,87 @@ +/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */ +/* + * Copyright (C) 2023 Sophgo Technology Inc. All rights reserved. + */ + +#ifndef __DT_BINDINGS_RESET_SOPHGO_SG2042_H_ +#define __DT_BINDINGS_RESET_SOPHGO_SG2042_H_ + +#define RST_MAIN_AP 0 +#define RST_RISCV_CPU 1 +#define RST_RISCV_LOW_SPEED_LOGIC 2 +#define RST_RISCV_CMN 3 +#define RST_HSDMA 4 +#define RST_SYSDMA 5 +#define RST_EFUSE0 6 +#define RST_EFUSE1 7 +#define RST_RTC 8 +#define RST_TIMER 9 +#define RST_WDT 10 +#define RST_AHB_ROM0 11 +#define RST_AHB_ROM1 12 +#define RST_I2C0 13 +#define RST_I2C1 14 +#define RST_I2C2 15 +#define RST_I2C3 16 +#define RST_GPIO0 17 +#define RST_GPIO1 18 +#define RST_GPIO2 19 +#define RST_PWM 20 +#define RST_AXI_SRAM0 21 +#define RST_AXI_SRAM1 22 +#define RST_SF0 23 +#define RST_SF1 24 +#define RST_LPC 25 +#define RST_ETH0 26 +#define RST_EMMC 27 +#define RST_SD 28 +#define RST_UART0 29 +#define RST_UART1 30 +#define RST_UART2 31 +#define RST_UART3 32 +#define RST_SPI0 33 +#define RST_SPI1 34 +#define RST_DBG_I2C 35 +#define RST_PCIE0 36 +#define RST_PCIE1 37 +#define RST_DDR0 38 +#define RST_DDR1 39 +#define RST_DDR2 40 +#define RST_DDR3 41 +#define RST_FAU0 42 +#define RST_FAU1 43 +#define RST_FAU2 44 +#define RST_RXU0 45 +#define RST_RXU1 46 +#define RST_RXU2 47 +#define RST_RXU3 48 +#define RST_RXU4 49 +#define RST_RXU5 50 +#define RST_RXU6 51 +#define RST_RXU7 52 +#define RST_RXU8 53 +#define RST_RXU9 54 +#define RST_RXU10 55 +#define RST_RXU11 56 +#define RST_RXU12 57 +#define RST_RXU13 58 +#define RST_RXU14 59 +#define RST_RXU15 60 +#define RST_RXU16 61 +#define RST_RXU17 62 +#define RST_RXU18 63 +#define RST_RXU19 64 +#define RST_RXU20 65 +#define RST_RXU21 66 +#define RST_RXU22 67 +#define RST_RXU23 68 +#define RST_RXU24 69 +#define RST_RXU25 70 +#define RST_RXU26 71 +#define RST_RXU27 72 +#define RST_RXU28 73 +#define RST_RXU29 74 +#define RST_RXU30 75 +#define RST_RXU31 76 + +#endif /* __DT_BINDINGS_RESET_SOPHGO_SG2042_H_ */ |