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2023-12-04dt-bindings: perf: riscv,pmu: fix property dependenciesREL_DUBHE_DEC2023starfive-6.1.65-dubheConor Dooley1-1/+0
[ Upstream commit 4d276e4d3bb4a503e75086faab54f92c0a8fd368 ] Seemingly I mis-implemented the dependencies here. The OpenSBI docs only point out that the "riscv,event-to-mhpmcounters property is mandatory if riscv,event-to-mhpmevent is present". It never claims that riscv,event-to-mhpmcounters requires riscv,event-to-mhpmevent. Drop the dependency of riscv,event-to-mhpmcounters on riscv,event-to-mhpmevent. Fixes: 7e38085d9c59 ("dt-bindings: riscv: add SBI PMU event mappings") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Atish Patra <atishp@rivosinc.com> Link: https://lore.kernel.org/r/20230404-tractor-confusing-8852e552539a@spud Signed-off-by: Rob Herring <robh@kernel.org>
2023-12-04dt-bindings: riscv: add SBI PMU event mappingsConor Dooley1-0/+161
[ Upstream commit 7e38085d9c59b6d07c1986ea43d046d457dcf646 ] The SBI PMU extension requires a firmware to be aware of the event to counter/mhpmevent mappings supported by the hardware. OpenSBI may use DeviceTree to describe the PMU mappings. This binding is currently described in markdown in OpenSBI (since v1.0 in Dec 2021) & used by QEMU since v7.2.0. Import the binding for use while validating dtb dumps from QEMU and upcoming hardware (eg JH7110 SoC) that will make use of the event mapping. Link: https://github.com/riscv-software-src/opensbi/blob/master/docs/pmu_support.md Link: https://github.com/riscv-non-isa/riscv-sbi-doc/blob/master/riscv-sbi.adoc # Performance Monitoring Unit Extension Co-developed-by: Atish Patra <atishp@rivosinc.com> Signed-off-by: Atish Patra <atishp@rivosinc.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20230113205435.122712-1-conor@kernel.org Signed-off-by: Rob Herring <robh@kernel.org>
2023-12-04riscv: dts: starfive: dubhe: Move pmu DT node out of soc nodeLey Foon Tan1-41/+40
PMU hardware is in the CPU core, move the pmu DT node out of the soc node. Signed-off-by: Ley Foon Tan <leyfoon.tan@starfivetech.com>
2023-12-04riscv: dts: starfive: dubhe: Add L2 cacheLey Foon Tan1-0/+11
Add the L2 cache DT node and add the next-level-cache for CPUs. Signed-off-by: Ley Foon Tan <leyfoon.tan@starfivetech.com>
2023-12-04riscv: dts: starfive: dubhe: Add cpu-map DT nodeLey Foon Tan1-0/+12
Add cpu-map DT node. Signed-off-by: Ley Foon Tan <leyfoon.tan@starfivetech.com>
2023-12-04riscv: dts: starfive: dubhe: Update Dubhe CPU compatible stringsLey Foon Tan3-1/+4
Change to "starfive,dubhe-80" and "starfive,dubhe-90" compatible strings. Signed-off-by: Ley Foon Tan <leyfoon.tan@starfivetech.com>
2023-12-04dt-bindings: riscv: Update StarFive Dubhe-80 and Dubhe-90 compatiblesLey Foon Tan1-1/+2
Change to use starfive,dubhe-80 and starfive,dubhe-90 compatible strings. Signed-off-by: Ley Foon Tan <leyfoon.tan@starfivetech.com>
2023-12-04riscv: dts: starfive: Convert spaces to tabsLey Foon Tan2-41/+41
Fix warning from checkpatch.pl. Signed-off-by: Ley Foon Tan <leyfoon.tan@starfivetech.com>
2023-12-04perf vendor events riscv: Fix dubhe-80 json file permission errorJi Sheng Teoh1-0/+0
This patch fix file permission error reported by checkpatch.pl ("ERROR: do not set execute permissions for source files"), by removing the executable permission. Fixes: 48d98fcaffe6 ("perf vendor events riscv: Add JSON metrics for Dubhe-80 Perf") Signed-off-by: Ji Sheng Teoh <jisheng.teoh@starfivetech.com>
2023-12-04perf vendor events riscv: Fix dubhe-90 json file permission errorJi Sheng Teoh1-0/+0
This patch fix file permission error reported by checkpatch.pl ("ERROR: do not set execute permissions for source files"), by removing the executable permission. Fixes: bf1c0c20e4fa ("perf vendor events riscv: Add JSON metrics for Dubhe-90 Perf") Signed-off-by: Ji Sheng Teoh <jisheng.teoh@starfivetech.com>
2023-12-04perf vendor events riscv: Add Dubhe-80 mapfileJi Sheng Teoh2-0/+173
Add mapfile for StarFive's Dubhe-80 to support custom perf events. Signed-off-by: Ji Sheng Teoh <jisheng.teoh@starfivetech.com>
2023-12-04perf vendor events riscv: Update Dubhe-90 mapfileJi Sheng Teoh2-1/+1
Update Dubhe-90 mapfile with new MARCHID and MIMPID. Signed-off-by: Ji Sheng Teoh <jisheng.teoh@starfivetech.com>
2023-12-04riscv: dts: starfive: dubhe: Update QSPI partitionJi Sheng Teoh1-5/+22
This patch updates QSPI partition to allow MTD util to update the content inside the QSPI flash. The QSPI partition are arranged as follow: QSPI Flash content | Start Addr | End Addr | Size | -------------------------------------------------------- Boot Copier(RO) | 0x00000000 | 0x00000fff | 4KB | Boot Jump Code(RO) | 0x00001000 | 0x00001fff | 4KB | U-Boot SPL | 0x00002000 | 0x00041fff | 256KB | U-Boot FIT Image | 0x00042000 | 0x00141fff | 1MB | Linux + Rootfs | 0x00142000 | 0x07ffffff | 126MB | Signed-off-by: Ji Sheng Teoh <jisheng.teoh@starfivetech.com>
2023-12-04riscv: configs: dubhe: Enable bridge networking and TUN/TAP driverTan En De1-0/+2
So that we can create virtual network consisting of bridge and TAP interface attached to the bridge as a port. Signed-off-by: Tan En De <ende.tan@starfivetech.com>
2023-12-04riscv: dts: starfive: dubhe: Add Dubhe 80 supportLey Foon Tan3-1/+36
Add Dubhe 80 DT support. Signed-off-by: Ley Foon Tan <leyfoon.tan@starfivetech.com>
2023-12-04riscv: dts: starfive: dubhe: Move fpga common to *common.dtsiLey Foon Tan2-109/+112
Move Dubhe FPGA common DT to *common.dtsi file, in preparation for Dubhe 80. Signed-off-by: Ley Foon Tan <leyfoon.tan@starfivetech.com>
2023-12-04riscv: dts: starfive: dubhe: Update Dubhe90 cpu DT nodeLey Foon Tan2-8/+12
- Add cpu0 and cpu1 label - Update D cache and I cache settings - Update "riscv,isa", remove unused 'n'. Signed-off-by: Ley Foon Tan <leyfoon.tan@starfivetech.com>
2023-12-04riscv: dts: starfive: dubhe: Restructure Dubhe device treeLey Foon Tan5-21/+33
Restructure the Dubhe device tree in preparation for Dubhe 80 support. Rename existing Dubhe to Dubhe 90. Signed-off-by: Ley Foon Tan <leyfoon.tan@starfivetech.com>
2023-12-04riscv: dts: starfive: Enable sscofpmf extension supportGenevieve Chan1-2/+4
Add sscofpmf extension support and interrupt register. Signed-off-by: Genevieve Chan <genevieve.chan@starfivetech.com>
2023-12-04riscv: kvm: Fix compilation warning for unused kvm_riscv_vcpu_update_config()Ley Foon Tan1-0/+2
Commit 338a93e3aea9 ("arch: riscv: kvm: Temporarily comment out henvcfg-related code") has commented out calling to kvm_riscv_vcpu_update_config() function. So, comment out kvm_riscv_vcpu_update_config() function to resolve unused function warning. arch/riscv/kvm/vcpu.c:807:13: warning: 'kvm_riscv_vcpu_update_config' defined but not used [-Wunused-function] 807 | static void kvm_riscv_vcpu_update_config(const unsigned long *isa) | Fixes: 338a93e3aea9 ("arch: riscv: kvm: Temporarily comment out henvcfg-related code") Signed-off-by: Ley Foon Tan <leyfoon.tan@starfivetech.com>
2023-12-04riscv: Fix build with CONFIG_CC_OPTIMIZE_FOR_SIZE=ySamuel Holland2-18/+10
[ upstream commit 0b1d60d6dd9e2e867cc6e4277d73ea5a7ff2d4d0 ] commit 8eb060e10185 ("arch/riscv: add Zihintpause support") broke building with CONFIG_CC_OPTIMIZE_FOR_SIZE enabled (gcc 11.1.0): CC arch/riscv/kernel/vdso/vgettimeofday.o In file included from <command-line>: ./arch/riscv/include/asm/jump_label.h: In function 'cpu_relax': ././include/linux/compiler_types.h:285:33: warning: 'asm' operand 0 probably does not match constraints 285 | #define asm_volatile_goto(x...) asm goto(x) | ^~~ ./arch/riscv/include/asm/jump_label.h:41:9: note: in expansion of macro 'asm_volatile_goto' 41 | asm_volatile_goto( | ^~~~~~~~~~~~~~~~~ ././include/linux/compiler_types.h:285:33: error: impossible constraint in 'asm' 285 | #define asm_volatile_goto(x...) asm goto(x) | ^~~ ./arch/riscv/include/asm/jump_label.h:41:9: note: in expansion of macro 'asm_volatile_goto' 41 | asm_volatile_goto( | ^~~~~~~~~~~~~~~~~ make[1]: *** [scripts/Makefile.build:249: arch/riscv/kernel/vdso/vgettimeofday.o] Error 1 make: *** [arch/riscv/Makefile:128: vdso_prepare] Error 2 Having a static branch in cpu_relax() is problematic because that function is widely inlined, including in some quite complex functions like in the VDSO. A quick measurement shows this static branch is responsible by itself for around 40% of the jump table. Drop the static branch, which ends up being the same number of instructions anyway. If Zihintpause is supported, we trade the nop from the static branch for a div. If Zihintpause is unsupported, we trade the jump from the static branch for (what gets interpreted as) a nop. Fixes: 8eb060e10185 ("arch/riscv: add Zihintpause support") Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Cc: stable@vger.kernel.org Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-12-04riscv: configs: dubhe: Add SBI console supportEnDe Tan1-0/+3
2023-12-04riscv: dts: starfive: dubhe: Update PMU event mappingGenevieve Chan1-52/+26
Change PMU event mapping based on updated Dubhe Q2 2023 release Signed-off-by: Genevieve Chan <genevieve.chan@starfivetech.com>
2023-12-04perf vendor events riscv: Update JSON metrics for StarFive Dubhe PerfGenevieve Chan9-826/+172
Add common perf event support for StarFive Dubhe. Remove unsupported events for StarFive Dubhe. Signed-off-by: Genevieve Chan <genevieve.chan@starfivetech.com>
2023-12-04riscv: Update arch_sync_dma_for_device() functionLey Foon Tan1-1/+11
Handle different DMA directions. Signed-off-by: Ley Foon Tan <leyfoon.tan@starfivetech.com>
2023-12-04riscv: invalidate cache when DMA_BIDIRECTIONAL case in arch_sync_dma_for_cpu()Ley Foon Tan1-2/+0
DMA_BIDIRECTIONAL cases also use invalidate. Signed-off-by: Ley Foon Tan <leyfoon.tan@starfivetech.com>
2023-12-04net: phy: Fix genphy_config_advert to advertise PAUSE and 10M Full duplex modeGenevieve Chan1-2/+1
This patch ensure that only 10M Full Duplex and PAUSE are enabled for StarFive Dubhe FPGA Platform Signed-off-by: Genevieve Chan <genevieve.chan@starfivetech.com>
2023-12-04riscv: dts: dubhe: Add PHY register settings in marvell,reg-init nodeGenevieve Chan1-0/+5
Use marvell,reg-init node in mdio PHY to update the PHY settings for StarFive Dubhe platform. The following settings are enabled: PAUSE+ ADVERTISED SPEED 10MBPS + COPPER MODE+ AUTONEGOTIATION+ Signed-off-by: Genevieve Chan <genevieve.chan@starfivetech.com>
2023-12-04Revert "net: phy: marvell: Set autonegotiation to OFF by default upon init"Genevieve Chan1-2/+0
This reverts commit 057202b6b0f0e9265d6e374f959f715bc3232227. Signed-off-by: Genevieve Chan <genevieve.chan@starfivetech.com>
2023-12-04Revert "net: phylink: Assign link config in phylink_create()"Genevieve Chan1-4/+4
This reverts commit dbe28bc438226acf5b9523bf0a156433470e417d. Signed-off-by: Genevieve Chan <genevieve.chan@starfivetech.com>
2023-12-04riscv: dts: dubhe: Remove server ip address from bootargsGenevieve Chan1-1/+1
Removes server ip address field from bootargs ip. Signed-off-by: Genevieve Chan <genevieve.chan@starfivetech.com>
2023-12-04riscv: dts: starfive: dubhe: Update flash partition patchYang Lee1-3/+3
This patch includes flash partition changes. Signed-off-by: Yang Lee <yang.lee@starfivetech.com>
2023-12-04perf vendor events riscv: Update JSON array syntax for Starfive Dubhe PerfYang Lee8-178/+178
This patch updates pmu-events json array syntax. Signed-off-by: Yang Lee <yang.lee@starfivetech.com>
2023-12-04riscv: configs: Dubhe: Enable virtualization and kvmTan En De1-0/+2
These two configs are needed to run KVM guest. Signed-off-by: Tan En De <ende.tan@starfivetech.com>
2023-12-04riscv: dts: dubhe: Disable vectorTan En De1-2/+2
Dubhe doesn't yet support vector extension. Signed-off-by: Tan En De <ende.tan@starfivetech.com>
2023-12-04random: Cater for low CONFIG_HZ when evaluating cycle counter for jitter ↵Tan En De1-1/+1
entropy generation MAX_SAMPLES_PER_BIT is defined as HZ / 15. However, because of the use of integer division, when HZ < 15, MAX_SAMPLES_BIT_PER_BIT becomes 0. On Linux with CONFIG_HZ < 15, this causes kernel to always assume cycle counter is not suitable for generating jitter entropy. Empirically, this assumption is not true on Dubhe FPGA with CONFIG_HZ_10, because regardless of the low CONFIG_HZ, Dubhe’s cycle counter is still able to produce entropy very fast, such that stack.samples_per_bit = 1. Thus, this commit uses round-up when computing MAX_SAMPLES_PER_BIT: MAX_SAMPLES_PER_BIT = DIV_ROUND_UP(HZ, 15) instead of simply HZ / 15. This way, on Dubhe FPGA with CONFIG_HZ_10, we get MAX_SAMPLES_PER_BIT = 1, and the speed check in try_to_generate_entropy() will pass, which then allows the use of cycle counter to generate jitter entropy. With this commit, Dubhe is now able to reach “crng init done” quickly whenever entropy is needed by a program during boot (ssh-keygen used by Buildroot's sshd). Signed-off-by: Tan En De <ende.tan@starfivetech.com>
2023-12-04riscv: starfive: Add DMA non-coherent support in StarFive DubheGenevieve Chan2-0/+2
This patch adds the dma non-coherent node in device tree. Sets noncoherent_supported to true for CONFIG_SOC_STARFIVE_DUBHE Signed-off-by: Genevieve Chan <genevieve.chan@starfivetech.com>
2023-12-04riscv: configs: dubhe: Add configs for mtdYang Lee1-3/+14
This patch includes mtd configs Signed-off-by: Yang Lee <yang.lee@starfivetech.com>
2023-12-04riscv: dts: starfive: dubhe: Add flash partition patchYang Lee1-0/+25
This patch includes flash partition changes. Signed-off-by: Yang Lee <yang.lee@starfivetech.com>
2023-12-04arch: riscv: kvm: Temporarily comment out henvcfg-related codeTan En De1-1/+2
Comment out kvm_riscv_vcpu_update_config since it touches currently non-existent henvcfg CSR on Dubhe, because Dubhe is still using hypervisor ISA v0.6.1. Uncommenting is needed once Dubhe is upgraded with hypervisor ISA v1.0. Signed-off-by: Tan En De <ende.tan@starfivetech.com>
2023-12-04riscv: configs: Dubhe: Add ext4 filesystem configTan En De1-0/+1
Needed to use ext4 filesystem. Signed-off-by: Tan En De <ende.tan@starfivetech.com>
2023-12-04net: phylink: Assign link config in phylink_create()Genevieve Chan1-4/+4
This patch parse the following config to a struct phylink: * speed = 10Mbps * duplex = full * pause = RX on, TX on Signed-off-by: Genevieve Chan <genevieve.chan@starfivetech.com>
2023-12-04riscv: dts: dubhe: Set ip in boot args and enable gmacGenevieve Chan1-1/+2
Set ip at kernel bootargs with the following parameters: * Client IP Address: autoconfg using DHCP * Server IP Address: not defined * Gateway IP Address: 192.168.152.1 * Netmask: 255.255.255.0 * Network device to use: eth0 * Autoconfiguration: dhcp Enable gmac driver. Signed-off-by: Genevieve Chan <genevieve.chan@starfivetech.com>
2023-12-04net: phy: marvell: Set autonegotiation to OFF by default upon initGenevieve Chan1-0/+2
This patch set AUTONEG_DISABLE during init to disable autonegotiation by default. Signed-off-by: Genevieve Chan <genevieve.chan@starfivetech.com>
2023-12-04riscv: configs: Dubhe: Add configs for initramfs sourceGenevieve Chan1-0/+2
The Dubhe ace_20221130 bitfile does not support GMAC. This patch re-enabled booting kernel through initramfs source "rootfs.cpio" Signed-off-by: Genevieve Chan <genevieve.chan@starfivetech.com>
2023-12-04riscv: dts: dubhe: Disable GMAC and remove NFSGenevieve Chan1-2/+1
The ace_20221130 version does not have GMAC support. Disable GMAC driver and remove NFS in the bootargs. Signed-off-by: Genevieve Chan <genevieve.chan@starfivetech.com>
2023-12-04riscv: dts: dubhe: Enable NFSGenevieve Chan1-1/+1
This patch adds NFS configuration in the bootargs. The bootargs for NFS is set with the following parameters: * Client IP Address: 192.168.152.100 * Server IP Address: 192.168.153.221 * Gateway IP Address: 192.168.152.1 * Netmask: 255.255.255.0 * Network device to use: eth0 * Autoconfiguration: off * NFS root dir: /home/nfsroot Signed-off-by: Genevieve Chan <genevieve.chan@starfivetech.com>
2023-12-04riscv: dts: dubhe: Fix ethernet max-speed to 10Mb/sLey Foon Tan1-0/+11
Fix ethernet max-speed to 10Mb/s for FPGA. Signed-off-by: Ley Foon Tan <leyfoon.tan@starfivetech.com>
2023-12-04riscv: starfive: Add DMA non-coherent supportLey Foon Tan2-0/+56
Enable arch_*dma* implementation. Signed-off-by: Ley Foon Tan <leyfoon.tan@linux.starfivetech.com>
2023-12-04riscv: sbi: Add support for sbi_cache_flush and sbi_cache_invalidateLey Foon Tan2-0/+38
This patch introduces the support for GMAC drivers to perform flush and invalidate of L2 Cache: * sbi_cache_invalidate(): Invalidate L2 cache for data passed from GMAC to CPU * sbi_cache_flush(): Flush L2 cache for data passed from CPU to GMAC Signed-off-by: Genevieve Chan <genevieve.chan@starfivetech.com>
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