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2023-12-08dt-bindings: hisilicon: Merge hi3620-clock into hisilicon,sysctrl bindingRob Herring1-0/+17
The hi3620-clock binding is simple and always a child of the "hisilicon,sysctrl" node, so just add it into the hisilicon,sysctrl binding and drop the old txt binding. Signed-off-by: Rob Herring <robh@kernel.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2023-07-19dt-bindings: arm: hisilicon,cpuctrl: Merge "hisilicon,hix5hd2-clock" into ↵Rob Herring1-0/+20
parent binding The "hisilicon,hix5hd2-clock" is simple enough to just add it into its parent node binding, "hisilicon,cpuctrl". This fixes a warning that "hisilicon,hix5hd2-clock" is missing a schema. Signed-off-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20230707210700.869060-1-robh@kernel.org Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-12-16dt-bindings: drop redundant part of title (end)Krzysztof Kozlowski1-1/+1
The Devicetree bindings document does not have to say in the title that it is a "Devicetree binding", but instead just describe the hardware. Drop trailing "Devicetree bindings" in various forms (also with trailing full stop): find Documentation/devicetree/bindings/ -type f -name '*.yaml' \ -not -name 'trivial-devices.yaml' \ -exec sed -i -e 's/^title: \(.*\) [dD]evice[ -]\?[tT]ree [bB]indings\?\.\?$/title: \1/' {} \; find Documentation/devicetree/bindings/ -type f -name '*.yaml' \ -not -name 'trivial-devices.yaml' \ -exec sed -i -e 's/^title: \(.*\) [dD]evice[ -]\?[nN]ode [bB]indings\?\.\?$/title: \1/' {} \; find Documentation/devicetree/bindings/ -type f -name '*.yaml' \ -not -name 'trivial-devices.yaml' \ -exec sed -i -e 's/^title: \(.*\) [dD][tT] [bB]indings\?\.\?$/title: \1/' {} \; Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Acked-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> # IIO Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Acked-by: Ulf Hansson <ulf.hansson@linaro.org> # MMC Acked-by: Stephen Boyd <sboyd@kernel.org> # clk Acked-by: Dmitry Torokhov <dmitry.torokhov@gmail.com> # input Acked-by: Mark Brown <broonie@kernel.org> Acked-by: Hans Verkuil <hverkuil-cisco@xs4all.nl> # media Acked-by: Sebastian Reichel <sre@kernel.org> # power Link: https://lore.kernel.org/r/20221216163815.522628-5-krzysztof.kozlowski@linaro.org Signed-off-by: Rob Herring <robh@kernel.org>
2022-05-23dt-bindings: Fix properties without any typeRob Herring1-2/+3
Now that the schema tools can extract type information for all properties (in order to decode dtb files), finding properties missing any type definition is fairly trivial though not yet automated. Fix the various property schemas which are missing a type. Most of these tend to be device specific properties which don't have a vendor prefix. A vendor prefix is how we normally ensure a type is defined. Signed-off-by: Rob Herring <robh@kernel.org> Acked-by: Sam Ravnborg <sam@ravnborg.org> # for everything in .../bindings/display/ Acked-by: Mark Brown <broonie@kernel.org> Acked-by: Peter Rosin <peda@axentia.se> Acked-by: Bartosz Golaszewski <brgl@bgdev.pl> Acked-by: Sebastian Reichel <sebastian.reichel@collabora.com> Link: https://lore.kernel.org/r/20220519211411.2200720-1-robh@kernel.org
2020-10-27dt-bindings: Explicitly allow additional properties in board/SoC schemasRob Herring1-0/+3
In order to add meta-schema checks for additional/unevaluatedProperties being present, all schema need to make this explicit. As the top-level board/SoC schemas always have additional properties, add 'additionalProperties: true'. Acked-by: Krzysztof Kozlowski <krzk@kernel.org> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20201005183830.486085-4-robh@kernel.org Signed-off-by: Rob Herring <robh@kernel.org>
2020-10-12dt-bindings: arm: hisilicon: add missing properties into cpuctrl.yamlZhen Lei1-1/+26
Add properties: #address-cells, #size-cells and ranges. Due to the Hisilicon CPU controller node may contains child nodes, change the value of "additionalProperties" from "false" to "type: object". The corresponding examples are also added. Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com> Link: https://lore.kernel.org/r/20201012061225.1597-11-thunder.leizhen@huawei.com Signed-off-by: Rob Herring <robh@kernel.org>
2020-10-12dt-bindings: arm: hisilicon: add missing properties into sysctrl.yamlZhen Lei1-3/+25
Add properties: #reset-cells, #address-cells, #size-cells and ranges. Due to the Hisilicon system controller node may contains child nodes, change the value of "additionalProperties" from "false" to "type: object". The examples have also been updated. Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com> Link: https://lore.kernel.org/r/20201012061225.1597-10-thunder.leizhen@huawei.com Signed-off-by: Rob Herring <robh@kernel.org>
2020-10-06dt-bindings: arm: hisilicon: convert Hi6220 domain controller bindings to ↵Zhen Lei4-54/+68
json-schema Convert the Hisilicon Hi6220 domain controllers binding to DT schema format using json-schema. All of them are grouped into one yaml file, to help users understand differences and avoid repeated descriptions. Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com> Link: https://lore.kernel.org/r/20200930031712.2365-16-thunder.leizhen@huawei.com Signed-off-by: Rob Herring <robh@kernel.org>
2020-10-01dt-bindings: arm: hisilicon: convert LPC controller bindings to json-schemaZhen Lei2-33/+61
Convert the Hisilicon Hip06 SoCs implement a Low Pin Count (LPC) controller binding to DT schema format using json-schema. Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com> Link: https://lore.kernel.org/r/20200929141454.2312-18-thunder.leizhen@huawei.com Signed-off-by: Rob Herring <robh@kernel.org>
2020-10-01dt-bindings: arm: hisilicon: convert hisilicon,hi3798cv200-perictrl bindings ↵Zhen Lei2-21/+64
to json-schema Convert the Hisilicon Hi3798CV200 Peripheral Controller binding to DT schema format using json-schema. Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com> Link: https://lore.kernel.org/r/20200929141454.2312-17-thunder.leizhen@huawei.com Signed-off-by: Rob Herring <robh@kernel.org>
2020-10-01dt-bindings: arm: hisilicon: convert hisilicon,hip04-bootwrapper bindings to ↵Zhen Lei2-9/+34
json-schema Convert the Hisilicon Bootwrapper boot method binding to DT schema format using json-schema. The property boot-method contains two groups of physical address range information: bootwrapper and relocation. The "uint32-array" type is not suitable for it, because the field "address" and "size" may occupy one or two cells respectively. Use "minItems: 1" and "maxItems: 2" to allow it can be written in "<addr size addr size>" or "<addr size>, <addr size>" format. Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com> Link: https://lore.kernel.org/r/20200929141454.2312-15-thunder.leizhen@huawei.com Signed-off-by: Rob Herring <robh@kernel.org>
2020-10-01dt-bindings: arm: hisilicon: convert hisilicon,hip04-fabric bindings to ↵Zhen Lei2-5/+27
json-schema Convert the Hisilicon Fabric controller binding to DT schema format using json-schema. Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com> Link: https://lore.kernel.org/r/20200929141454.2312-14-thunder.leizhen@huawei.com Signed-off-by: Rob Herring <robh@kernel.org>
2020-10-01dt-bindings: arm: hisilicon: convert hisilicon,pctrl bindings to json-schemaZhen Lei2-13/+34
Convert the Hisilicon peripheral misc control register binding to DT schema format using json-schema. Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com> Link: https://lore.kernel.org/r/20200929141454.2312-13-thunder.leizhen@huawei.com Signed-off-by: Rob Herring <robh@kernel.org>
2020-10-01dt-bindings: arm: hisilicon: convert hisilicon,cpuctrl bindings to json-schemaZhen Lei2-8/+29
Convert the Hisilicon CPU controller binding to DT schema format using json-schema. Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com> Link: https://lore.kernel.org/r/20200929141454.2312-12-thunder.leizhen@huawei.com Signed-off-by: Rob Herring <robh@kernel.org>
2020-10-01dt-bindings: arm: hisilicon: convert system controller bindings to json-schemaZhen Lei5-77/+110
Convert the Hisilicon system controller and its variants binding to DT schema format using json-schema. All of them are grouped into one yaml file, to help users understand differences and avoid repeated descriptions. Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com> Link: https://lore.kernel.org/r/20200929141454.2312-11-thunder.leizhen@huawei.com Signed-off-by: Rob Herring <robh@kernel.org>
2020-10-01dt-bindings: arm: hisilicon: add binding for SD5203 SoCZhen Lei1-0/+5
Add devicetree binding for Hisilicon SD5203 SoC. Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com> Link: https://lore.kernel.org/r/20200929141454.2312-6-thunder.leizhen@huawei.com Signed-off-by: Rob Herring <robh@kernel.org>
2020-10-01dt-bindings: arm: hisilicon: convert Hisilicon board/soc bindings to json-schemaZhen Lei2-57/+62
Convert Hisilicon SoC bindings to DT schema format using json-schema. Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Rob Herring <robh@kernel.org>
2020-10-01dt-bindings: arm: hisilicon: split the dt-bindings of each controller into a ↵Zhen Lei12-194/+173
separate file Split the devicetree bindings of each Hisilicon controller from hisilicon.txt into a separate file, the file name is the compatible name attach the .txt file name extension. Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com> Link: https://lore.kernel.org/r/20200929141454.2312-4-thunder.leizhen@huawei.com Signed-off-by: Rob Herring <robh@kernel.org>
2020-10-01dt-bindings: arm: hisilicon: delete the descriptions of HiP05/HiP06 controllersZhen Lei1-68/+0
The compatible strings of Hi6220 SRAM controller, HiP05/HiP06 PCIe-SAS subsystem controller, HiP05/HiP06 PERI subsystem controller and HiP05/HiP06 DSA subsystem controller is in syscon.yaml now. Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com> Link: https://lore.kernel.org/r/20200929141454.2312-3-thunder.leizhen@huawei.com Signed-off-by: Rob Herring <robh@kernel.org>
2020-02-24docs: dt: fix several broken references due to renamesMauro Carvalho Chehab1-1/+1
Several DT references got broken due to txt->yaml conversion. Those are auto-fixed by running: scripts/documentation-file-ref-check --fix Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org> Acked-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Dan Murphy <dmurphy@ti.com> Reviewed-by: Amit Kucheria <amit.kucheria@linaro.org> Signed-off-by: Rob Herring <robh@kernel.org>
2018-09-19dt-bindings: arm: hisilicon: Add binding for HiKey970 boardManivannan Sadhasivam1-0/+4
Add devicetree binding for HiKey970 board. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2018-09-19dt-bindings: arm: hisilicon: Add binding for Hi3670 SoCManivannan Sadhasivam1-0/+4
Add devicetree binding for Hi3670 SoC. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2018-04-07Merge tag 'pci-v4.17-changes' of ↵Linus Torvalds1-0/+33
git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci Pull PCI updates from Bjorn Helgaas: - move pci_uevent_ers() out of pci.h (Michael Ellerman) - skip ASPM common clock warning if BIOS already configured it (Sinan Kaya) - fix ASPM Coverity warning about threshold_ns (Gustavo A. R. Silva) - remove last user of pci_get_bus_and_slot() and the function itself (Sinan Kaya) - add decoding for 16 GT/s link speed (Jay Fang) - add interfaces to get max link speed and width (Tal Gilboa) - add pcie_bandwidth_capable() to compute max supported link bandwidth (Tal Gilboa) - add pcie_bandwidth_available() to compute bandwidth available to device (Tal Gilboa) - add pcie_print_link_status() to log link speed and whether it's limited (Tal Gilboa) - use PCI core interfaces to report when device performance may be limited by its slot instead of doing it in each driver (Tal Gilboa) - fix possible cpqphp NULL pointer dereference (Shawn Lin) - rescan more of the hierarchy on ACPI hotplug to fix Thunderbolt/xHCI hotplug (Mika Westerberg) - add support for PCI I/O port space that's neither directly accessible via CPU in/out instructions nor directly mapped into CPU physical memory space. This is fairly intrusive and includes minor changes to interfaces used for I/O space on most platforms (Zhichang Yuan, John Garry) - add support for HiSilicon Hip06/Hip07 LPC I/O space (Zhichang Yuan, John Garry) - use PCI_EXP_DEVCTL2_COMP_TIMEOUT in rapidio/tsi721 (Bjorn Helgaas) - remove possible NULL pointer dereference in of_pci_bus_find_domain_nr() (Shawn Lin) - report quirk timings with dev_info (Bjorn Helgaas) - report quirks that take longer than 10ms (Bjorn Helgaas) - add and use Altera Vendor ID (Johannes Thumshirn) - tidy Makefiles and comments (Bjorn Helgaas) - don't set up INTx if MSI or MSI-X is enabled to align cris, frv, ia64, and mn10300 with x86 (Bjorn Helgaas) - move pcieport_if.h to drivers/pci/pcie/ to encapsulate it (Frederick Lawler) - merge pcieport_if.h into portdrv.h (Bjorn Helgaas) - move workaround for BIOS PME issue from portdrv to PCI core (Bjorn Helgaas) - completely disable portdrv with "pcie_ports=compat" (Bjorn Helgaas) - remove portdrv link order dependency (Bjorn Helgaas) - remove support for unused VC portdrv service (Bjorn Helgaas) - simplify portdrv feature permission checking (Bjorn Helgaas) - remove "pcie_hp=nomsi" parameter (use "pci=nomsi" instead) (Bjorn Helgaas) - remove unnecessary "pcie_ports=auto" parameter (Bjorn Helgaas) - use cached AER capability offset (Frederick Lawler) - don't enable DPC if BIOS hasn't granted AER control (Mika Westerberg) - rename pcie-dpc.c to dpc.c (Bjorn Helgaas) - use generic pci_mmap_resource_range() instead of powerpc and xtensa arch-specific versions (David Woodhouse) - support arbitrary PCI host bridge offsets on sparc (Yinghai Lu) - remove System and Video ROM reservations on sparc (Bjorn Helgaas) - probe for device reset support during enumeration instead of runtime (Bjorn Helgaas) - add ACS quirk for Ampere (née APM) root ports (Feng Kan) - add function 1 DMA alias quirk for Marvell 88SE9220 (Thomas Vincent-Cross) - protect device restore with device lock (Sinan Kaya) - handle failure of FLR gracefully (Sinan Kaya) - handle CRS (config retry status) after device resets (Sinan Kaya) - skip various config reads for SR-IOV VFs as an optimization (KarimAllah Ahmed) - consolidate VPD code in vpd.c (Bjorn Helgaas) - add Tegra dependency on PCI_MSI_IRQ_DOMAIN (Arnd Bergmann) - add DT support for R-Car r8a7743 (Biju Das) - fix a PCI_EJECT vs PCI_BUS_RELATIONS race condition in Hyper-V host bridge driver that causes a general protection fault (Dexuan Cui) - fix Hyper-V host bridge hang in MSI setup on 1-vCPU VMs with SR-IOV (Dexuan Cui) - fix Hyper-V host bridge hang when ejecting a VF before setting up MSI (Dexuan Cui) - make several structures static (Fengguang Wu) - increase number of MSI IRQs supported by Synopsys DesignWare bridges from 32 to 256 (Gustavo Pimentel) - implemented multiplexed IRQ domain API and remove obsolete MSI IRQ API from DesignWare drivers (Gustavo Pimentel) - add Tegra power management support (Manikanta Maddireddy) - add Tegra loadable module support (Manikanta Maddireddy) - handle 64-bit BARs correctly in endpoint support (Niklas Cassel) - support optional regulator for HiSilicon STB (Shawn Guo) - use regulator bulk API for Qualcomm apq8064 (Srinivas Kandagatla) - support power supplies for Qualcomm msm8996 (Srinivas Kandagatla) * tag 'pci-v4.17-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: (123 commits) MAINTAINERS: Add John Garry as maintainer for HiSilicon LPC driver HISI LPC: Add ACPI support ACPI / scan: Do not enumerate Indirect IO host children ACPI / scan: Rename acpi_is_serial_bus_slave() for more general use HISI LPC: Support the LPC host on Hip06/Hip07 with DT bindings of: Add missing I/O range exception for indirect-IO devices PCI: Apply the new generic I/O management on PCI IO hosts PCI: Add fwnode handler as input param of pci_register_io_range() PCI: Remove __weak tag from pci_register_io_range() MAINTAINERS: Add missing /drivers/pci/cadence directory entry fm10k: Report PCIe link properties with pcie_print_link_status() net/mlx5e: Use pcie_bandwidth_available() to compute bandwidth net/mlx5: Report PCIe link properties with pcie_print_link_status() net/mlx4_core: Report PCIe link properties with pcie_print_link_status() PCI: Add pcie_print_link_status() to log link speed and whether it's limited PCI: Add pcie_bandwidth_available() to compute bandwidth available to device misc: pci_endpoint_test: Handle 64-bit BARs properly PCI: designware-ep: Make dw_pcie_ep_reset_bar() handle 64-bit BARs properly PCI: endpoint: Make sure that BAR_5 does not have 64-bit flag set when clearing PCI: endpoint: Make epc->ops->clear_bar()/pci_epc_clear_bar() take struct *epf_bar ...
2018-04-04HISI LPC: Support the LPC host on Hip06/Hip07 with DT bindingsZhichang Yuan1-0/+33
The low-pin-count (LPC) interface of Hip06/Hip07 accesses I/O port space of peripherals. Implement the LPC host controller driver which performs the I/O operations on the underlying hardware. We don't want to touch existing drivers such as ipmi-bt, so this driver applies the indirect-IO introduced in the previous patch after registering an indirect-IO node to the indirect-IO devices list which will be searched by the I/O accessors to retrieve the host-local I/O port. The driver config is set as a bool instead of a tristate. The reason here is that, by the very nature of the driver providing a logical PIO range, it does not make sense to have this driver as a loadable module. Another more specific reason is that the Huawei D03 board which includes Hip06 SoC requires the LPC bus for UART console, so should be built in. Tested-by: dann frazier <dann.frazier@canonical.com> Signed-off-by: Zou Rongrong <zourongrong@huawei.com> Signed-off-by: Zhichang Yuan <yuanzhichang@hisilicon.com> Signed-off-by: John Garry <john.garry@huawei.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Acked-by: Rob Herring <robh@kernel.org> # dts part
2018-02-21dt-bindings: hisilicon: add doc for Hi3798CV200 peripheral controllerShawn Guo1-0/+23
It adds bindings doc for Hi3798CV200 peripheral controller. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2017-06-15dt-bindings: arm: hisilicon: add bindings for HiKey960 boardGuodong Xu1-0/+4
Add bindings for HiKey960 Board. Signed-off-by: Guodong Xu <guodong.xu@linaro.org> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2017-04-06dt-bindings: arm: hisilicon: add bindings for hi3798cv200 SoC and Poplar boardJiancheng Xue1-0/+8
Add bindings for HiSilicon hi3798cv200 SoC and Poplar Board. Signed-off-by: Jiancheng Xue <xuejiancheng@hisilicon.com> Reviewed-by: Alex Elder <elder@linaro.org> Acked-by: Peter Griffin <peter.griffin@linaro.org> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2017-01-25document: dt: add binding for Hi3660 SoCChen Feng1-0/+4
Add binding for hisilicon Hi3660 SoC and HiKey960 Board. Signed-off-by: Chen Feng <puck.chen@hisilicon.com> Acked-by: Rob Herring <robh@kernel.org> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2016-11-15Documentation: arm64: Add Hisilicon Hip07 D05 dts bindingKefeng Wang1-0/+4
This patch adds documentation for the devicetree bindings used by the DT files of Hisilicon Hip07 D05 board. Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2016-08-24dt-bindings: hisilicon: Add Hip05 and Hip06 system controller supportKefeng Wang1-11/+28
The Hip05 and Hip06 are very similar in design, use better and unified name for system controller. Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2016-06-28ARM: dt-bindings: add device tree bindings for Hi3519 sysctrlJiancheng Xue1-0/+14
Add device tree bindings for Hi3519 system controller. Signed-off-by: Jiancheng Xue <xuejiancheng@huawei.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2016-04-27Documentation: arm64: Add Hisilicon Hip06 D03 dts bindingKefeng Wang1-8/+12
This patch adds documentation for the devicetree bindings used by the DT files of Hisilicon Hip06 D03 board. Meanwhile, reorder the soc/board name alphabetically. Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2016-01-15dts: hisi: fixes no syscon fault when init mdioyankejian1-0/+16
When linux start up, we get the log below: "Hi-HNS_MDIO 803c0000.mdio: no syscon hisilicon,peri-c-subctrl mdio_bus mdio@803c0000: mdio sys ctl reg has not maped" The source code about the subctrl is dealt syscon, but dts doesn't. It cause such fault, so this patch adds the syscon info on dts files to fixes it. Signed-off-by: Kejian Yan <yankejian@huawei.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: David S. Miller <davem@davemloft.net>
2015-11-11Merge tag 'armsoc-dt' of ↵Linus Torvalds1-0/+4
git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM DT updates from Olof Johansson: "As usual, this is the massive branch we have for each release. Lots of various updates and additions of hardware descriptions on existing hardware, as well as the usual additions of new boards and SoCs. This is also the first release where we've started mixing 64- and 32-bit DT updates in one branch. (Specific details on what's actually here and new is pretty easy to tell from the diffstat, so there's little point in duplicating listing it here)" * tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (499 commits) ARM: dts: uniphier: add system-bus-controller nodes ARM64: juno: disable NOR flash node by default ARM: dts: uniphier: add outer cache controller nodes arm64: defconfig: Enable PCI generic host bridge by default arm64: Juno: Add support for the PCIe host bridge on Juno R1 Documentation: of: Document the bindings used by Juno R1 PCIe host bridge ARM: dts: uniphier: add I2C aliases for ProXstream2 boards dts/Makefile: Add build support for LS2080a QDS & RDB board DTS dts/ls2080a: Add DTS support for LS2080a QDS & RDB boards dts/ls2080a: Update Simulator DTS to add support of various peripherals dts/ls2080a: Remove text about writing to Free Software Foundation dts/ls2080a: Update DTSI to add support of various peripherals doc: DTS: Update DWC3 binding to provide reference to generic bindings doc/bindings: Update GPIO devicetree binding documentation for LS2080A Documentation/dts: Move FSL board-specific bindings out of /powerpc Documentation: DT: Add entry for FSL LS2080A QDS and RDB boards arm64: Rename FSL LS2085A SoC support code to LS2080A arm64: Use generic Layerscape SoC family naming ARM: dts: uniphier: add ProXstream2 Vodka board support ARM: dts: uniphier: add ProXstream2 Gentil board support ...
2015-11-03PCI: hisi: Add HiSilicon SoC Hip05 PCIe driverZhou Wang1-0/+17
Add PCIe host support for HiSilicon SoC Hip05, related DT binding documentation, and maintainer update. [bhelgaas: changelog, 32-bit only config write warning text] Signed-off-by: Zhou Wang <wangzhou1@hisilicon.com> Signed-off-by: Gabriele Paoloni <gabriele.paoloni@huawei.com> Signed-off-by: liudongdong <liudongdong3@huawei.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Rob Herring <robh@kernel.org> (DT binding)
2015-09-21arm64: hip05-d02: Document devicetree bindings for Hisilicon Hip05-D02 BoardDing Tianhong1-0/+4
This patch adds documentation for the devicetree bindings used by the DT files of Hisilicon Hip05-D02 development board. Signed-off-by: Ding Tianhong <dingtianhong@huawei.com> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2015-08-25dt-bindings: arm: Hi6220: add doc for SRAM controllerLeo Yan1-0/+18
Document "hisilicon,hi6220-sramctrl" for SRAM controller. Signed-off-by: Leo Yan <leo.yan@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-06-05arm64: hi6220: Document devicetree bindings for Hisilicon hi6220 SoCBintian Wang1-0/+87
This patch adds documentation for the devicetree bindings used by the DT files of Hisilicon hi6220 SoC mobile platform. Signed-off-by: Bintian Wang <bintian.wang@huawei.com> Suggested-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Haojian Zhuang <haojian.zhuang@linaro.org> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2015-01-22ARM: dts: Add hip01-ca9x2 dts fileWang Long1-0/+25
Add dts file for Hisilicon hip01 ca9x2 board Signed-off-by: Wang Long <long.wanglong@huawei.com> Signed-off-by: Wei Xu <xuwei5@hisilicon.com> [olof: Folded in smp enable-method from a different patch] Signed-off-by: Olof Johansson <olof@lixom.net>
2014-09-03document: dt: add the binding on HiP04Haojian Zhuang1-0/+23
Add Hisilicon HiP04 SoC platform & Fabric controller. Fabric controller could be used to configure snoop filter among multiple clusters. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2014-07-31ARM: hisi: enable hix5hd2 SoCHaifeng Yan1-0/+11
Enable support for the Hisilicon HiX5HD2 SoC. This HiX5HD2 SoC series support both single and dual Cortex-A9 cores. Add ARCH_HIX5HD2 to distinguish HiX5HD2 from Hi3xxx. They are different in implementation such as SMP, IPs integarted and earlycon configure. Signed-off-by: Haifeng Yan <yanhaifeng@gmail.com> Signed-off-by: Jiancheng Xue <jchxue@gmail.com> Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org> Acked-by: Wei Xu <xuwei5@hisilicon.com> Signed-off-by: Olof Johansson <olof@lixom.net>
2014-02-27clk: hisilicon: add hi3620_mmc_clksZhangfei Gao1-0/+14
Suggest by Arnd: abstract mmc tuning as clock behavior, also because different soc have different tuning method and registers. hi3620_mmc_clks is added to handle mmc clock specifically on hi3620. Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-12-18ARM: hi3xxx: add smp supportKevin Hilman1-0/+26
Enable SMP support on hi3xxx platform Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org> Tested-by: Zhang Mingjun <zhang.mingjun@linaro.org> Tested-by: Li Xin <li.xin@linaro.org> Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org> [khilman: fix checkpatch errors] Signed-off-by: Kevin Hilman <khilman@linaro.org>
2013-12-18ARM: hi3xxx: add board support with device treeHaojian Zhuang1-0/+6
Add board support with device tree for Hisilicon Hi3620 SoC platform. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org> [khilman: fix checkpatch errors] [khilman: fold in patch which selects GPIO in Kconfig] Signed-off-by: Kevin Hilman <khilman@linaro.org>
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