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2013-05-09bfin cache: dcplb map: add 16M dcplb map for BF60xSteven Miao2-7/+36
use 16M data cplb map on BF60x to avoid too much dcplb miss overhead cleanup cplb info Signed-off-by: Steven Miao <realmz6@gmail.com>
2012-07-24blackfin: cplb-nompu: fix ROM cplb size for bf609-ezkitBob Liu1-0/+8
In user xip test, there is a cplb error when ROMKERNEL try to mount romfs using 'mount -t romfs /dev/mtdblock2 /mnt', becasue the CPLB setting is not correct. Signed-off-by: Bob Liu <lliubbo@gmail.com>
2012-05-21blackfin: cplb: add support for bf60xBob Liu2-2/+8
Bf60x support big CPLB pages, this commit enable it. Signed-off-by: Bob Liu <lliubbo@gmail.com>
2011-01-10Blackfin: no-mpu: fix masking of small uncached dma regionSonic Zhang1-1/+1
When using an uncached DMA region less than 1 MiB, we try to mask off the whole last 1 MiB for it. Unfortunately, this fails as we forgot to subtract one from the calculated mask, leading to the region still be marked as cacheable. Reported-by: Andrew Rook <andrew.rook@speakerbus.co.uk> Signed-off-by: Sonic Zhang <sonic.zhang@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2010-03-09Blackfin: initial XIP supportBarry Song1-0/+9
Signed-off-by: Barry Song <barry.song@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2009-12-15Blackfin: NOMPU: skip DMA ICPLB hole when it is redundantMike Frysinger1-5/+6
Normally there is no user-reserved memory after the DMA region which means there is no user-reserved ICPLB coverage. So the DMA hole can be covered by the large hole that is always added to cover up to the async bank. We only need an explicit DMA whole when we also add an explicit mapping for the user-reserved memory. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2009-12-15Blackfin: support smaller uncached DMA chunks for memory constrained systemsBarry Song1-7/+13
When working with 8 meg systems, forcing a 1 meg DMA chunk heavily cuts into the available resources. So support smaller chunks to better cover needs for these systems. Signed-off-by: Barry Song <barry.song@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2009-10-07Blackfin: mass clean up of copyright/licensing infoRobin Getz2-31/+4
Bill Gatliff & David Brownell pointed out we were missing some copyrights, and licensing terms in some of the files in ./arch/blackfin, so this fixes things, and cleans them up. It also removes: - verbose GPL text(refer to the top level ./COPYING file) - file names (you are looking at the file) - bug url (it's in the ./MAINTAINERS file) - "or later" on GPL-2, when we did not have that right It also allows some Blackfin-specific assembly files to be under a BSD like license (for people to use them outside of Linux). Signed-off-by: Robin Getz <robin.getz@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2009-09-17Blackfin: unify cache init functionsMike Frysinger2-72/+1
The CPLB implementations (mpu/nompu) had exact copies of the cacheinit code. Even the i/d cache functions are largely the same. So unify them both in the common kernel cache code. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2009-09-17Blackfin: add ICPLB coverage for async banksBernd Schmidt1-2/+9
When doing XIP, we need to execute out of the async banks, so we need ICPLBs to allow this. Signed-off-by: Bernd Schmidt <bernds_cb1@t-online.de> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2009-09-17Blackfin: use raw_smp_processor_id() in exception codeYi Li1-1/+1
When preempt debugging is enabled, smp_processor_id() may utilize the "current" structure. This may not be safe to access under all exceptions due to it being in dynamically allocated memory. So in exception code, make sure we use raw_smp_processor_id() instead to get at the real value directly. Signed-off-by: Yi Li <yi.li@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2009-09-17Blackfin: cleanup sync handling when enabling/disabling cplbsYi Li2-31/+8
The handling of updating the [DI]MEM_CONTROL MMRs does not follow proper sync procedures as laid out in the Blackfin programming manual. So rather than audit/fix every call location, create helper functions that do the right things in order to safely update these MMRs. Then convert all call sites to use these new helper functions. While we're fixing the code, drop the workaround for anomaly 05000125 as that anomaly applies to old versions of silicon that we do not support. Signed-off-by: Yi Li <yi.li@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2009-07-16Blackfin: add CPLB entries for Core B on-chip L1 SRAM regionsGraf Yang1-6/+17
The Blackfin SMP port was missing CPLB entries for Core B on-chip L1 SRAM regions. Any code that attempted to use these would wrongly crash due to a CPLB miss. Signed-off-by: Graf Yang <graf.yang@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2009-06-13Blackfin: only handle CPLB protection violations when MPU is enabledRobin Getz1-51/+3
We don't need to handle CPLB protection violations unless we are running with the MPU on. Fix the entry code to call common trap_c, and remove the code which is never run. This allows the traps test suite to run on older boards with the MPU disabled. URL: http://blackfin.uclinux.org/gf/tracker/5129 Signed-off-by: Robin Getz <robin.getz@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2009-06-12Blackfin: add workaround for anomaly 05000287Graf Yang1-1/+8
Signed-off-by: Graf Yang <graf.yang@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2009-03-02Blackfin arch: fix bug - jump_to_zero test case failed on noMPU kernelBernd Schmidt1-0/+4
The nompu code is now derived from the mpu code, and had the same problem - no null pointer detection on ICPLBs. Signed-off-by: Bernd Schmidt <bernds_cb1@t-online.de> Cc: Mike Frysinger <vapier.adi@gmail.com> Signed-off-by: Bryan Wu <cooloney@kernel.org>
2009-02-04Blackfin arch: cplb mananger: use a do...while loop rather than a for loopMike Frysinger1-4/+8
use a do...while loop rather than a for loop to get slightly better optimization and to avoid gcc "may be used uninitialized" warnings ... we know that the [id]cplb_nr_bounds variables will never be 0, so this is OK Signed-off-by: Mike Frysinger <vapier.adi@gmail.com> Signed-off-by: Bryan Wu <cooloney@kernel.org>
2009-01-07Blackfin arch: Faster C implementation of no-MPU CPLB handlerBernd Schmidt6-1182/+410
This is a mixture ofcMichael McTernan's patch and the existing cplb-mpu code. We ditch the old cplb-nompu implementation, which is a good example of why a good algorithm in a HLL is preferrable to a bad algorithm written in assembly. Rather than try to construct a table of all posible CPLBs and search it, we just create a (smaller) table of memory regions and their attributes. Some of the data structures are now unified for both the mpu and nompu cases. A lot of needless complexity in cplbinit.c is removed. Further optimizations: * compile cplbmgr.c with a lot of -ffixed-reg options, and omit saving these registers on the stack when entering a CPLB exception. * lose cli/nop/nop/sti sequences for some workarounds - these don't * make sense in an exception context Additional code unification should be possible after this. [Mike Frysinger <vapier.adi@gmail.com>: - convert CPP if statements to C if statements - remove redundant statements - use a do...while loop rather than a for loop to get slightly better optimization and to avoid gcc "may be used uninitialized" warnings ... we know that the [id]cplb_nr_bounds variables will never be 0, so this is OK - the no-mpu code was the last user of MAX_MEM_SIZE and with that rewritten, we can punt it - add some BUG_ON() checks to make sure we dont overflow the small cplb_bounds array - add i/d cplb entries for the bootrom because there is functions/data in there we want to access - we do not need a NULL trailing entry as any time we access the bounds arrays, we use the nr_bounds variable ] Signed-off-by: Michael McTernan <mmcternan@airvana.com> Signed-off-by: Mike Frysinger <vapier.adi@gmail.com> Signed-off-by: Bernd Schmidt <bernds_cb1@t-online.de> Signed-off-by: Bryan Wu <cooloney@kernel.org>
2009-01-07Blackfin arch: smp patch cleanup from LKML reviewGraf Yang1-0/+1
1. Use inline get_l1_... functions instead of macro 2. Fix compile issue about smp barrier functions Signed-off-by: Graf Yang <graf.yang@analog.com> Signed-off-by: Bryan Wu <cooloney@kernel.org>
2009-01-07Blackfin arch: tweak the BUG_ON() check to allow for equal valuesMike Frysinger1-4/+4
Tweak the BUG_ON() check to allow for equal values since the way pos is handled ... it is always indexed and post incremented Signed-off-by: Mike Frysinger <vapier.adi@gmail.com> Signed-off-by: Bryan Wu <cooloney@kernel.org>
2008-11-18Blackfin arch: add BUG_ON() checks to make sure we dont overflow the cplb tablesMike Frysinger1-1/+10
Signed-off-by: Mike Frysinger <vapier.adi@gmail.com> Signed-off-by: Bryan Wu <cooloney@kernel.org>
2008-11-18Blackfin arch: noMMU CPLB lookup tables can be in L1 SRAMMike Frysinger1-4/+9
- unify duplicate page_size_table definitions - make sure it is placed alongside the other cplb switching code Pointed-out-by: Michael McTernan <mmcternan@airvana.com> Signed-off-by: Mike Frysinger <vapier.adi@gmail.com> Signed-off-by: Bryan Wu <cooloney@kernel.org>
2008-11-18Blackfin arch: do not include init sections in the kernel lock down as it ↵Mike Frysinger1-1/+1
gets released afterwards Signed-off-by: Mike Frysinger <vapier.adi@gmail.com> Signed-off-by: Bryan Wu <cooloney@kernel.org>
2008-11-18Blackfin arch: change return valueMike Frysinger1-12/+6
change return of close_cplbtab() and fill_cplbtab() to void since we always return 0 and nowhere do we check this Signed-off-by: Mike Frysinger <vapier.adi@gmail.com> Signed-off-by: Bryan Wu <cooloney@kernel.org>
2008-11-18Blackfin arch: remove pointless define IN_KERNELMike Frysinger1-4/+4
Signed-off-by: Mike Frysinger <vapier.adi@gmail.com> Signed-off-by: Bryan Wu <cooloney@kernel.org>
2008-11-18Blackfin arch: unify cplbinfo filesMike Frysinger2-211/+0
Merge MPU and noMPU version of CPLB info code to one common version. Signed-off-by: Mike Frysinger <vapier.adi@gmail.com> Signed-off-by: Bryan Wu <cooloney@kernel.org>
2008-11-18Blackfin arch: SMP supporting patchset: Blackfin CPLB related codeGraf Yang4-97/+85
Blackfin dual core BF561 processor can support SMP like features. https://docs.blackfin.uclinux.org/doku.php?id=linux-kernel:smp-like In this patch, we provide SMP extend to Blackfin CPLB related code Signed-off-by: Graf Yang <graf.yang@analog.com> Signed-off-by: Bryan Wu <cooloney@kernel.org>
2008-10-27Blackfin arch: fix bug - Fail to boot jffs2 kernel for BF561 with SMP patchGraf Yang1-4/+5
only if the cplb block overlapped with kernel area, this cplb need be locked Signed-off-by: Graf Yang <graf.yang@analog.com> Signed-off-by: Bryan Wu <cooloney@kernel.org>
2008-10-16Blackfin arch: move bfin_addr_dcachable() and friends into the cacheflush ↵Mike Frysinger1-0/+1
header where it belongs Signed-off-by: Mike Frysinger <vapier.adi@gmail.com> Signed-off-by: Bryan Wu <cooloney@kernel.org>
2008-10-09Blackfin arch: Make L2 SRAM cacheableSonic Zhang1-2/+2
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com> Signed-off-by: Bryan Wu <cooloney@kernel.org>
2008-10-08Blackfin arch: Modify some funtion names to more genernal onesGraf Yang1-1/+1
Signed-off-by: Graf Yang <graf.yang@analog.com> Signed-off-by: Bryan Wu <cooloney@kernel.org>
2008-08-14Blackfin arch: mark some functions as __init as they are only called from ↵Mike Frysinger1-2/+2
__init functions Signed-off-by: Mike Frysinger <vapier.adi@gmail.com> Signed-off-by: Bryan Wu <cooloney@kernel.org>
2008-08-13Blackfin arch: convert L2 defines to be the same as the L1 definesMike Frysinger1-5/+1
Signed-off-by: Mike Frysinger <vapier.adi@gmail.com> Signed-off-by: Bryan Wu <cooloney@kernel.org>
2008-07-15Blackfin arch: Fix BUG - JUMP error in kernel (relocation truncated to fit: ↵Michael Hennerich1-1/+1
R_pcrel12_jump_s) Use long jump Signed-off-by: Michael Hennerich <michael.hennerich@analog.com> Signed-off-by: Bryan Wu <cooloney@kernel.org>
2008-07-14Blackfin arch: Remove redundant kernel optionMichael Hennerich1-5/+1
use kernel command line mem and max_mem bootargs to limit availabe memory instead. Signed-off-by: Michael Hennerich <michael.hennerich@analog.com> Signed-off-by: Bryan Wu <cooloney@kernel.org>
2008-06-25Blackfin arch: fix up section mismatch warningBryan Wu1-2/+4
-- WARNING: vmlinux.o(.text+0x721a): Section mismatch in reference from the function ___fill_code_cplbtab() to the function .init.text:_fill_cplbtab() The function ___fill_code_cplbtab() references the function __init _fill_cplbtab(). This is often because ___fill_code_cplbtab lacks a __init annotation or the annotation of _fill_cplbtab is wrong. WARNING: vmlinux.o(.text+0x7238): Section mismatch in reference from the function ___fill_code_cplbtab() to the function .init.text:_fill_cplbtab() The function ___fill_code_cplbtab() references the function __init _fill_cplbtab(). This is often because ___fill_code_cplbtab lacks a __init annotation or the annotation of _fill_cplbtab is wrong. WARNING: vmlinux.o(.text+0x7250): Section mismatch in reference from the function ___fill_code_cplbtab() to the function .init.text:_fill_cplbtab() The function ___fill_code_cplbtab() references the function __init _fill_cplbtab(). This is often because ___fill_code_cplbtab lacks a __init annotation or the annotation of _fill_cplbtab is wrong. WARNING: vmlinux.o(.text+0x7264): Section mismatch in reference from the function ___fill_code_cplbtab() to the function .init.text:_fill_cplbtab() The function ___fill_code_cplbtab() references the function __init _fill_cplbtab(). This is often because ___fill_code_cplbtab lacks a __init annotation or the annotation of _fill_cplbtab is wrong. WARNING: vmlinux.o(.text+0x72a2): Section mismatch in reference from the function ___fill_data_cplbtab() to the function .init.text:_fill_cplbtab() The function ___fill_data_cplbtab() references the function __init _fill_cplbtab(). This is often because ___fill_data_cplbtab lacks a __init annotation or the annotation of _fill_cplbtab is wrong. WARNING: vmlinux.o(.text+0x72bc): Section mismatch in reference from the function ___fill_data_cplbtab() to the function .init.text:_fill_cplbtab() The function ___fill_data_cplbtab() references the function __init _fill_cplbtab(). This is often because ___fill_data_cplbtab lacks a __init annotation or the annotation of _fill_cplbtab is wrong. WARNING: vmlinux.o(.text+0x72d4): Section mismatch in reference from the function ___fill_data_cplbtab() to the function .init.text:_fill_cplbtab() The function ___fill_data_cplbtab() references the function __init _fill_cplbtab(). This is often because ___fill_data_cplbtab lacks a __init annotation or the annotation of _fill_cplbtab is wrong. WARNING: vmlinux.o(.text+0x72e8): Section mismatch in reference from the function ___fill_data_cplbtab() to the function .init.text:_fill_cplbtab() The function ___fill_data_cplbtab() references the function __init _fill_cplbtab(). This is often because ___fill_data_cplbtab lacks a __init annotation or the annotation of _fill_cplbtab is wrong. -- Signed-off-by: Bryan Wu <cooloney@kernel.org>
2008-04-24[Blackfin] arch: detect the memory available in the system on the fly by defaultMike Frysinger1-2/+8
detect the memory available in the system on the fly by default rather than forcing people to set this manually in the kconfig Signed-off-by: Mike Frysinger <vapier.adi@gmail.com> Signed-off-by: Bryan Wu <cooloney@kernel.org>
2008-04-24[Blackfin] arch: add boot messages to quickly distinguish between MPU/NOMPU ↵Mike Frysinger1-0/+2
settings Signed-off-by: Mike Frysinger <vapier.adi@gmail.com> Signed-off-by: Bryan Wu <cooloney@kernel.org>
2008-04-24[Blackfin] arch: remove duplicated prototypes for internal cplb structures ↵Mike Frysinger1-3/+1
from the global blackfin header remove duplicated prototypes for internal cplb structures from the global blackfin header as nothing else should be accessing these Signed-off-by: Mike Frysinger <vapier.adi@gmail.com> Signed-off-by: Bryan Wu <cooloney@kernel.org>
2008-04-23[Blackfin] arch: relocate MAX_SWITCH_{D,I}_CPLBS from the header to the file ↵Mike Frysinger2-11/+23
where it actually gets used. relocate MAX_SWITCH_{D,I}_CPLBS from the header to the file where it actually gets used. this way when we change CONFIG_MEM_SIZE in our kconfig, we only rebuild one or two files rather than a whole bunch that implicitly include cplb.h. this will also remove the ability to clear the swapcount on the fly, but i really dont think that functionality is important. ultimate goal is for CONFIG_MEM_SIZE to go away and calculate this value on the fly based on what u-boot programmed for us. Signed-off-by: Mike Frysinger <vapier.adi@gmail.com> Signed-off-by: Bryan Wu <cooloney@kernel.org>
2008-01-22[Blackfin] arch: Fix bug - kernel build with Debug option enabled fails to ↵Michael Hennerich1-0/+2
boot up writes to I/DMEM_CONTROL must be followed by SSYNC Signed-off-by: Michael Hennerich <michael.hennerich@analog.com> Signed-off-by: Bryan Wu <bryan.wu@analog.com>
2008-01-11[Blackfin] arch: move all code related to CPLB handling into a new ↵Bernd Schmidt6-0/+1496
subdirectory under kernel/ Signed-off-by: Bernd Schmidt <bernd.schmidt@analog.com> Signed-off-by: Bryan Wu <bryan.wu@analog.com>
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