starfive-tech/linux.git - StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)

Age	Commit message (Expand)	Author	Files	Lines
2023-12-14	mm: Introduce flush_cache_vmap_early()	Alexandre Ghiti	1	-1/+2
2023-09-01	Merge tag 'riscv-for-linus-6.6-mw1' of git://git.kernel.org/pub/scm/linux/ker...	Linus Torvalds	1	-0/+2
2023-08-30	Merge tag 'mm-stable-2023-08-28-18-26' of git://git.kernel.org/pub/scm/linux/...	Linus Torvalds	1	-10/+9
2023-08-25	riscv: implement the new page table range API	Matthew Wilcox (Oracle)	1	-10/+9
2023-08-24	riscv: allow kmalloc() caches aligned to the smallest value	Jisheng Zhang	1	-0/+2
2023-08-10	riscv: Implement flush_cache_vmap()	Alexandre Ghiti	1	-0/+4
2023-03-15	RISC-V: Add Zicboz detection and block size parsing	Andrew Jones	1	-1/+2
2022-12-10	Merge patch series "RISC-V: Ensure Zicbom has a valid block size"	Palmer Dabbelt	1	-8/+0
2022-12-02	riscv/mm: hugepage's PG_dcache_clean flag is only set in head page	Tong Tiangen	1	-0/+7
2022-10-21	RISC-V: Fix compilation without RISCV_ISA_ZICBOM	Andrew Jones	1	-8/+0
2022-10-13	Merge patch series "Some style cleanups for recent extension additions"	Palmer Dabbelt	1	-0/+2
2022-10-13	riscv: drop some idefs from CMO initialization	Heiko Stuebner	1	-0/+2
2022-09-17	RISC-V: Avoid coupling the T-Head CMOs and Zicbom	Palmer Dabbelt	1	-1/+5
2022-09-13	RISC-V: Clean up the Zicbom block size probing	Palmer Dabbelt	1	-0/+1
2022-07-29	riscv: Add support for non-coherent devices using zicbom extension	Heiko Stuebner	1	-0/+10
2020-06-08	mm: rename flush_icache_user_range to flush_icache_user_page	Christoph Hellwig	1	-1/+2
2020-06-08	riscv: use asm-generic/cacheflush.h	Christoph Hellwig	1	-59/+3
2020-03-03	riscv: Use flush_icache_mm for flush_icache_user_range	Guo Ren	1	-1/+1
2019-07-18	riscv: fix build break after macro-to-function conversion in generic cacheflu...	Paul Walmsley	1	-4/+59
2019-06-05	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 286	Thomas Gleixner	1	-9/+1
2019-05-17	riscv: move flush_icache_{all,mm} to cacheflush.c	Gary Guo	1	-1/+1
2018-06-07	riscv: use NULL instead of a plain 0	Luc Van Oostenryck	1	-1/+1
2017-11-30	RISC-V: Allow userspace to flush the instruction cache	Andrew Waterman	1	-0/+6
2017-11-30	RISC-V: Flush I$ when making a dirty page executable	Andrew Waterman	1	-4/+20
2017-09-27	RISC-V: Atomic and Locking Code	Palmer Dabbelt	1	-0/+39