index
:
starfive-tech/linux.git
JH7100_VisionFive_OH_dev
JH7110_VisionFive2_510_devel
JH7110_VisionFive2_6.1.y_devel
JH7110_VisionFive2_6.6.y_devel
JH7110_VisionFive2_devel
JH7110_VisionFive2_upstream
beaglev-5.13.y
beaglev_fedora_devel
buildroot-upstream
esmil_starlight
fedora-vic-7100_5.10.6
master
openwrt-6.1.y
rt-ethercat-release
rt-linux-release
rtthread_AMP
starfive-5.13
starfive-5.15-dubhe
starfive-6.1-dubhe
starfive-6.1.65-dubhe
starfive-6.6.10-dubhe
starfive-6.6.31-dubhe
starlight-5.14.y
visionfive
visionfive-5.13.y-devel
visionfive-5.15.y
visionfive-5.15.y-devel
visionfive-5.15.y_fedora_devel
visionfive-5.16.y
visionfive-5.17.y
visionfive-5.18.y
visionfive-5.19.y
visionfive-6.4.y
visionfive_fedora_devel
StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)
Andrey V.Kosteltsev
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path:
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/
arch
/
riscv
/
include
/
asm
/
cpufeature.h
Age
Commit message (
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Author
Files
Lines
2024-03-22
Merge tag 'riscv-for-linus-6.9-mw2' of git://git.kernel.org/pub/scm/linux/ker...
Linus Torvalds
1
-12
/
+19
2024-03-13
riscv: Set unaligned access speed at compile time
Charlie Jenkins
1
-11
/
+13
2024-03-13
riscv: Decouple emulated unaligned accesses from access speed
Charlie Jenkins
1
-1
/
+1
2024-03-13
riscv: lib: Introduce has_fast_unaligned_access()
Charlie Jenkins
1
-3
/
+8
2024-02-10
work around gcc bugs with 'asm goto' with outputs
Linus Torvalds
1
-2
/
+2
2024-01-18
Merge patch series "riscv: Add fine-tuned checksum functions"
Palmer Dabbelt
1
-0
/
+2
2024-01-18
riscv: Add static key for misaligned accesses
Charlie Jenkins
1
-0
/
+2
2023-12-13
riscv: add ISA extension parsing for scalar crypto
Evan Green
1
-1
/
+3
2023-11-09
riscv: Rearrange hwcap.h and cpufeature.h
Xiao Wang
1
-0
/
+83
2023-11-08
RISC-V: Probe misaligned access speed in parallel
Evan Green
1
-1
/
+0
2023-11-05
Merge patch series "Add support to handle misaligned accesses in S-mode"
Palmer Dabbelt
1
-0
/
+18
2023-11-01
riscv: report misaligned accesses emulation to hwprobe
Clément Léger
1
-0
/
+18
2023-09-21
RISC-V: Enable cbo.zero in usermode
Andrew Jones
1
-0
/
+1
2023-09-01
RISC-V: Probe for unaligned access speed
Evan Green
1
-0
/
+2
2023-06-19
RISC-V: Track ISA extensions per hart
Evan Green
1
-0
/
+10
2023-04-19
RISC-V: hwprobe: Support probing of misaligned access performance
Evan Green
1
-0
/
+2
2023-04-19
RISC-V: Move struct riscv_cpuinfo to new header
Evan Green
1
-0
/
+21