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starfive-tech/linux.git
JH7100_VisionFive_OH_dev
JH7110_VisionFive2_510_devel
JH7110_VisionFive2_6.1.y_devel
JH7110_VisionFive2_6.6.y_devel
JH7110_VisionFive2_devel
JH7110_VisionFive2_upstream
beaglev-5.13.y
beaglev_fedora_devel
buildroot-upstream
esmil_starlight
fedora-vic-7100_5.10.6
master
openwrt-6.1.y
rt-ethercat-release
rt-linux-release
rtthread_AMP
starfive-5.13
starfive-5.15-dubhe
starfive-6.1-dubhe
starfive-6.1.65-dubhe
starfive-6.6.10-dubhe
starfive-6.6.31-dubhe
starlight-5.14.y
visionfive
visionfive-5.13.y-devel
visionfive-5.15.y
visionfive-5.15.y-devel
visionfive-5.15.y_fedora_devel
visionfive-5.16.y
visionfive-5.17.y
visionfive-5.18.y
visionfive-5.19.y
visionfive-6.4.y
visionfive_fedora_devel
StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)
Andrey V.Kosteltsev
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path:
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arch
/
riscv
/
kernel
/
cpu.c
Age
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Author
Files
Lines
2022-10-28
RISC-V: Fix /proc/cpuinfo cpumask warning
Andrew Jones
1
-0
/
+3
2022-10-14
Merge tag 'riscv-for-linus-6.1-mw2' of git://git.kernel.org/pub/scm/linux/ker...
Linus Torvalds
1
-0
/
+51
2022-10-14
RISC-V: Add mvendorid, marchid, and mimpid to /proc/cpuinfo output
Palmer Dabbelt
1
-0
/
+51
2022-10-12
Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm
Linus Torvalds
1
-0
/
+1
2022-10-07
RISC-V: Print SSTC in canonical order
Palmer Dabbelt
1
-1
/
+1
2022-10-04
RISC-V: Add mvendorid, marchid, and mimpid to /proc/cpuinfo output
Anup Patel
1
-0
/
+51
2022-10-02
RISC-V: Probe Svinval extension form ISA string
Mayuresh Chitale
1
-0
/
+1
2022-08-12
RISC-V: Add Sstc extension support
Palmer Dabbelt
1
-0
/
+1
2022-08-12
RISC-V: Enable sstc extension parsing from DT
Atish Patra
1
-0
/
+1
2022-08-11
arch/riscv: add Zihintpause support
Dao Lu
1
-0
/
+1
2022-08-11
riscv: implement Zicbom-based CMO instructions + the t-head variant
Palmer Dabbelt
1
-0
/
+1
2022-07-29
riscv: Add support for non-coherent devices using zicbom extension
Heiko Stuebner
1
-0
/
+1
2022-07-20
riscv: cpu: Add 64bit hartid support on RV64
Sunil V L
1
-11
/
+15
2022-05-21
riscv: Don't output a bogus mmu-type on a no MMU kernel
Niklas Cassel
1
-0
/
+4
2022-05-12
riscv: add RISC-V Svpbmt extension support
Heiko Stuebner
1
-0
/
+1
2022-04-01
riscv: cpu.c: don't use kernel-doc markers for comments
Randy Dunlap
1
-2
/
+2
2022-03-31
RISC-V: Fix a comment typo in riscv_of_parent_hartid()
Atish Patra
1
-1
/
+1
2022-03-22
perf: RISC-V: Add support for SBI PMU and Sscofpmf
Palmer Dabbelt
1
-0
/
+1
2022-03-22
RISC-V: Add sscofpmf extension support
Atish Patra
1
-0
/
+1
2022-03-18
RISC-V: Provide a fraemework for RISC-V ISA extensions
Palmer Dabbelt
1
-2
/
+63
2022-03-17
RISC-V: Improve /proc/cpuinfo output for ISA extensions
Atish Patra
1
-2
/
+63
2022-02-15
riscv: mm: Set sv57 on defaultly
Qinglin Pan
1
-1
/
+3
2022-01-20
riscv: Use pgtable_l4_enabled to output mmu_type in cpuinfo
Alexandre Ghiti
1
-11
/
+12
2021-10-20
riscv: Use of_get_cpu_hwid()
Rob Herring
1
-1
/
+2
2020-06-10
RISC-V: Rename and move plic_find_hart_id() to arch directory
Anup Patel
1
-0
/
+16
2019-10-28
RISC-V: Remove unsupported isa string info print
Atish Patra
1
-42
/
+3
2019-06-05
treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 286
Thomas Gleixner
1
-9
/
+1
2019-04-30
RISC-V: Add RISC-V specific arch_match_cpu_phys_id
Atish Patra
1
-2
/
+1
2019-03-04
RISC-V: Remove NR_CPUs check during hartid search from DT
Atish Patra
1
-4
/
+0
2019-02-12
riscv: treat cpu devicetree nodes without status as enabled
Johan Hovold
1
-7
/
+3
2019-02-12
riscv: fix riscv_of_processor_hartid() comment
Johan Hovold
1
-9
/
+9
2019-02-12
riscv: add missing newlines to printk messages
Johan Hovold
1
-1
/
+1
2018-12-21
RISC-V: Fix of_node_* refcount
Atish Patra
1
-0
/
+1
2018-11-20
RISC-V: recognize S/U mode bits in print_isa
Patrick Stählin
1
-3
/
+6
2018-10-23
RISC-V: Show CPU ID and Hart ID separately in /proc/cpuinfo
Anup Patel
1
-4
/
+6
2018-10-23
RISC-V: Use Linux logical CPU number instead of hartid
Atish Patra
1
-3
/
+5
2018-10-23
RISC-V: Rename riscv_of_processor_hart to riscv_of_processor_hartid
Palmer Dabbelt
1
-2
/
+5
2018-10-23
RISC-V: Filter ISA and MMU values in cpuinfo
Palmer Dabbelt
1
-7
/
+61
2017-09-27
RISC-V: Init and Halt Code
Palmer Dabbelt
1
-0
/
+108