index
:
starfive-tech/linux.git
JH7100_VisionFive_OH_dev
JH7110_VisionFive2_510_devel
JH7110_VisionFive2_6.1.y_devel
JH7110_VisionFive2_6.6.y_devel
JH7110_VisionFive2_devel
JH7110_VisionFive2_upstream
beaglev-5.13.y
beaglev_fedora_devel
buildroot-upstream
esmil_starlight
fedora-vic-7100_5.10.6
master
openwrt-6.1.y
rt-ethercat-release
rt-linux-release
rtthread_AMP
starfive-5.13
starfive-5.15-dubhe
starfive-6.1-dubhe
starfive-6.1.65-dubhe
starfive-6.6.10-dubhe
starfive-6.6.31-dubhe
starlight-5.14.y
visionfive
visionfive-5.13.y-devel
visionfive-5.15.y
visionfive-5.15.y-devel
visionfive-5.15.y_fedora_devel
visionfive-5.16.y
visionfive-5.17.y
visionfive-5.18.y
visionfive-5.19.y
visionfive-6.4.y
visionfive_fedora_devel
StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)
Andrey V.Kosteltsev
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
arch
/
riscv
/
kernel
/
cpu_ops.c
Age
Commit message (
Expand
)
Author
Files
Lines
2024-01-05
riscv: Use the same CPU operations for all CPUs
Samuel Holland
1
-7
/
+5
2024-01-05
riscv: Remove unused members from struct cpu_operations
Samuel Holland
1
-2
/
+0
2023-04-29
RISC-V: Align SBI probe implementation with spec
Andrew Jones
1
-1
/
+1
2022-08-11
riscv: ensure cpu_ops_sbi is declared
Conor Dooley
1
-0
/
+1
2022-08-11
RISC-V: Declare cpu_ops_spinwait in <asm/cpu_ops.h>
Ben Dooks
1
-3
/
+1
2022-01-20
RISC-V: Move spinwait booting method to its own config
Atish Patra
1
-0
/
+8
2022-01-20
RISC-V: Use __cpu_up_stack/task_pointer only for spinwait method
Atish Patra
1
-16
/
+0
2022-01-20
RISC-V: Do not print the SBI version during HSM extension boot print
Atish Patra
1
-1
/
+1
2020-10-26
treewide: Convert macro and uses of __section(foo) to __section("foo")
Joe Perches
1
-2
/
+2
2020-05-05
riscv: force __cpu_up_ variables to put in data section
Zong Li
1
-2
/
+2
2020-03-31
RISC-V: Add supported for ordered booting method using HSM
Atish Patra
1
-1
/
+9
2020-03-31
RISC-V: Add cpu_ops and modify default booting method
Atish Patra
1
-0
/
+38