| Age | Commit message (Expand) | Author | Files | Lines |
|---|---|---|---|---|
| 2023-08-24 | riscv: Implement syscall wrappers | Sami Tolvanen | 1 | -2/+6 |
| 2021-10-02 | riscv/vdso: Refactor asm/vdso.h | Tong Tiangen | 1 | -1/+0 |
| 2021-04-26 | riscv: Constify sys_call_table | Jisheng Zhang | 1 | -1/+1 |
| 2019-10-28 | riscv: add missing header file includes | Paul Walmsley | 1 | -0/+1 |
| 2019-06-05 | treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 286 | Thomas Gleixner | 1 | -9/+1 |
| 2018-01-08 | RISC-V: Make __NR_riscv_flush_icache visible to userspace | Palmer Dabbelt | 1 | -1/+0 |
| 2017-11-30 | RISC-V: Allow userspace to flush the instruction cache | Andrew Waterman | 1 | -0/+2 |
| 2017-09-27 | RISC-V: User-facing API | Palmer Dabbelt | 1 | -0/+25 |
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index : starfive-tech/linux.git | |
| StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror) | Andrey V.Kosteltsev |
| summaryrefslogtreecommitdiff |