index
:
starfive-tech/linux.git
JH7100_VisionFive_OH_dev
JH7110_VisionFive2_510_devel
JH7110_VisionFive2_6.1.y_devel
JH7110_VisionFive2_6.6.y_devel
JH7110_VisionFive2_devel
JH7110_VisionFive2_upstream
beaglev-5.13.y
beaglev_fedora_devel
buildroot-upstream
esmil_starlight
fedora-vic-7100_5.10.6
master
openwrt-6.1.y
rt-ethercat-release
rt-linux-release
rtthread_AMP
starfive-5.13
starfive-5.15-dubhe
starfive-6.1-dubhe
starfive-6.1.65-dubhe
starfive-6.6.10-dubhe
starfive-6.6.31-dubhe
starlight-5.14.y
visionfive
visionfive-5.13.y-devel
visionfive-5.15.y
visionfive-5.15.y-devel
visionfive-5.15.y_fedora_devel
visionfive-5.16.y
visionfive-5.17.y
visionfive-5.18.y
visionfive-5.19.y
visionfive-6.4.y
visionfive_fedora_devel
StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)
Andrey V.Kosteltsev
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path:
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/
arch
/
x86
/
include
/
asm
/
sparsemem.h
Age
Commit message (
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Author
Files
Lines
2024-05-07
x86/numa: Fix SRAT lookup of CFMWS ranges with numa_fill_memblks()
Robert Richter
1
-2
/
+0
2023-09-13
x86/numa: Introduce numa_fill_memblks()
Alison Schofield
1
-0
/
+2
2022-10-04
x86: add missing include to sparsemem.h
Dmitry Vyukov
1
-0
/
+2
2020-11-22
mm: fix phys_to_target_node() and memory_add_physaddr_to_nid() exports
Dan Williams
1
-0
/
+10
2020-07-24
x86/mm: Drop unused MAX_PHYSADDR_BITS
Arvind Sankar
1
-5
/
+1
2018-05-19
x86/mm: Stop pretending pgtable_l5_enabled is a variable
Kirill A. Shutemov
1
-2
/
+2
2018-02-14
x86/mm: Make MAX_PHYSADDR_BITS and MAX_PHYSMEM_BITS dynamic
Kirill A. Shutemov
1
-7
/
+2
2017-11-02
License cleanup: add SPDX GPL-2.0 license identifier to files with no license
Greg Kroah-Hartman
1
-0
/
+1
2017-04-04
x86/mm: Define virtual memory map for 5-level paging
Kirill A. Shutemov
1
-2
/
+7
2009-05-06
x86: 46 bit physical address support on 64 bits
Rik van Riel
1
-1
/
+1
2008-12-16
x86, mm: limit MAXMEM on 64-bit
Ingo Molnar
1
-1
/
+1
2008-10-23
x86: Fix ASM_X86__ header guards
H. Peter Anvin
1
-3
/
+3
2008-10-23
x86, um: ... and asm-x86 move
Al Viro
1
-0
/
+34