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:
starfive-tech/linux.git
JH7100_VisionFive_OH_dev
JH7110_VisionFive2_510_devel
JH7110_VisionFive2_6.1.y_devel
JH7110_VisionFive2_6.6.y_devel
JH7110_VisionFive2_devel
JH7110_VisionFive2_upstream
beaglev-5.13.y
beaglev_fedora_devel
buildroot-upstream
esmil_starlight
fedora-vic-7100_5.10.6
master
openwrt-6.1.y
rt-ethercat-release
rt-linux-release
rtthread_AMP
starfive-5.13
starfive-5.15-dubhe
starfive-6.1-dubhe
starfive-6.1.65-dubhe
starfive-6.6.10-dubhe
starfive-6.6.31-dubhe
starlight-5.14.y
visionfive
visionfive-5.13.y-devel
visionfive-5.15.y
visionfive-5.15.y-devel
visionfive-5.15.y_fedora_devel
visionfive-5.16.y
visionfive-5.17.y
visionfive-5.18.y
visionfive-5.19.y
visionfive-6.4.y
visionfive_fedora_devel
StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)
Andrey V.Kosteltsev
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path:
root
/
drivers
/
clk
/
at91
/
clk-utmi.c
Age
Commit message (
Expand
)
Author
Files
Lines
2023-10-19
clk: at91: remove unnecessary conditions
Dan Carpenter
1
-7
/
+5
2023-06-21
clk: at91: clk-utmi: add support for parent_hw
Claudiu Beznea
1
-7
/
+17
2021-10-27
clk: at91: re-factor clocks suspend/resume
Claudiu Beznea
1
-0
/
+39
2020-07-24
clk: at91: clk-utmi: add utmi support for sama7g5
Claudiu Beznea
1
-5
/
+98
2019-05-30
treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 152
Thomas Gleixner
1
-6
/
+1
2018-10-17
clk: at91: move DT compatibility code to its own file
Alexandre Belloni
1
-43
/
+0
2018-10-17
clk: at91: allow clock registration from C code
Alexandre Belloni
1
-1
/
+1
2017-11-02
clk: at91: utmi: set the mainck rate
Ludovic Desroches
1
-14
/
+81
2016-09-15
clk: at91: Migrate to clk_hw based registration and OF APIs
Stephen Boyd
1
-9
/
+13
2016-02-17
clk: at91: remove IRQ handling and use polling
Alexandre Belloni
1
-44
/
+5
2016-02-17
clk: at91: make use of syscon/regmap internally
Boris Brezillon
1
-23
/
+30
2015-09-17
clk: at91: utmi: use pmc_read when the at91_pmc is available
Alexandre Belloni
1
-2
/
+2
2015-07-02
clk: at91: do not leak resources
David Dueck
1
-2
/
+6
2013-12-02
clk: at91: add PMC utmi clock
Boris BREZILLON
1
-0
/
+159