starfive-tech/linux.git - StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)

Age	Commit message (Expand)	Author	Files	Lines
2023-06-21	clk: at91: sama7g5: s/ep_chg_chg_id/ep_chg_id	Claudiu Beznea	1	-1/+1
2023-06-21	clk: at91: sama7g5: switch to parent_hw and parent_data	Claudiu Beznea	1	-342/+454
2023-06-21	clk: at91: clk-sam9x60-pll: add support for parent_hw	Claudiu Beznea	1	-1/+1
2023-06-21	clk: at91: clk-utmi: add support for parent_hw	Claudiu Beznea	1	-1/+1
2023-06-21	clk: at91: clk-system: add support for parent_hw	Claudiu Beznea	1	-1/+1
2023-06-21	clk: at91: clk-programmable: add support for parent_hw	Claudiu Beznea	1	-1/+1
2023-06-21	clk: at91: clk-peripheral: add support for parent_hw	Claudiu Beznea	1	-1/+1
2023-06-21	clk: at91: clk-master: add support for parent_hw	Claudiu Beznea	1	-2/+2
2023-06-21	clk: at91: clk-generated: add support for parent_hw	Claudiu Beznea	1	-1/+1
2023-06-21	clk: at91: clk-main: add support for parent_data/parent_hw	Claudiu Beznea	1	-2/+2
2023-01-09	clk: at91: mark ddr clocks as critical	Claudiu Beznea	1	-2/+2
2022-03-08	clk: at91: sama7g5: fix parents of PDMCs' GCLK	Codrin Ciubotariu	1	-4/+4
2022-01-25	clk: at91: sama7g5: Allow MCK1 to be exported and referenced in DT	Tudor Ambarus	1	-1/+7
2021-10-27	clk: at91: sama7g5: set low limit for mck0 at 32KHz	Claudiu Beznea	1	-1/+1
2021-10-27	clk: at91: sama7g5: remove prescaler part of master clock	Claudiu Beznea	1	-10/+1
2021-10-27	clk: at91: clk-master: add notifier for divider	Claudiu Beznea	1	-1/+1
2021-10-27	clk: at91: clk-sam9x60-pll: add notifier for div part of PLL	Claudiu Beznea	1	-2/+11
2021-10-27	clk: at91: sama7g5: add securam's peripheral clock	Claudiu Beznea	1	-0/+1
2021-08-29	clk: at91: sama7g5: remove all kernel-doc & kernel-doc warnings	Randy Dunlap	1	-7/+7
2021-03-14	clk: at91: Trivial typo fixes in the file sama7g5.c	Bhaskar Chowdhury	1	-3/+3
2020-12-19	clk: at91: sama7g5: register cpu clock	Claudiu Beznea	1	-7/+6
2020-12-19	clk: at91: clk-master: re-factor master clock	Claudiu Beznea	1	-2/+11
2020-12-19	clk: at91: sama7g5: do not allow cpu pll to go higher than 1GHz	Claudiu Beznea	1	-14/+47
2020-12-19	clk: at91: sama7g5: decrease lower limit for MCK0 rate	Claudiu Beznea	1	-1/+1
2020-12-19	clk: at91: sama7g5: remove mck0 from parent list of other clocks	Claudiu Beznea	1	-29/+26
2020-12-19	clk: at91: clk-sam9x60-pll: allow runtime changes for pll	Claudiu Beznea	1	-17/+50
2020-12-19	clk: at91: sama7g5: add 5th divisor for mck0 layout and characteristics	Eugen Hristev	1	-2/+2
2020-12-19	clk: at91: sama7g5: allow SYS and CPU PLLs to be exported and referenced in DT	Eugen Hristev	1	-2/+4
2020-12-19	dt-bindings: clock: at91: add sama7g5 pll defines	Eugen Hristev	1	-3/+3
2020-12-19	clk: at91: sama7g5: fix compilation error	Claudiu Beznea	1	-2/+4
2020-07-24	clk: at91: sama7g5: add clock support for sama7g5	Claudiu Beznea	1	-0/+1059