index
:
starfive-tech/linux.git
JH7100_VisionFive_OH_dev
JH7110_VisionFive2_510_devel
JH7110_VisionFive2_6.1.y_devel
JH7110_VisionFive2_6.6.y_devel
JH7110_VisionFive2_devel
JH7110_VisionFive2_upstream
beaglev-5.13.y
beaglev_fedora_devel
buildroot-upstream
esmil_starlight
fedora-vic-7100_5.10.6
master
openwrt-6.1.y
rt-ethercat-release
rt-linux-release
rtthread_AMP
starfive-5.13
starfive-5.15-dubhe
starfive-6.1-dubhe
starfive-6.1.65-dubhe
starfive-6.6.10-dubhe
starfive-6.6.31-dubhe
starlight-5.14.y
visionfive
visionfive-5.13.y-devel
visionfive-5.15.y
visionfive-5.15.y-devel
visionfive-5.15.y_fedora_devel
visionfive-5.16.y
visionfive-5.17.y
visionfive-5.18.y
visionfive-5.19.y
visionfive-6.4.y
visionfive_fedora_devel
StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)
Andrey V.Kosteltsev
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
drivers
/
clk
/
at91
Age
Commit message (
Expand
)
Author
Files
Lines
2021-03-14
clk: at91: Trivial typo fixes in the file sama7g5.c
Bhaskar Chowdhury
1
-3
/
+3
2021-02-10
clk: at91: Fix the declaration of the clocks
Tudor Ambarus
9
-28
/
+28
2020-12-20
clk: at91: sam9x60: remove atmel,osc-bypass support
Alexandre Belloni
1
-5
/
+1
2020-12-19
clk: at91: sama7g5: register cpu clock
Claudiu Beznea
1
-7
/
+6
2020-12-19
clk: at91: clk-master: re-factor master clock
Claudiu Beznea
14
-146
/
+542
2020-12-19
clk: at91: sama7g5: do not allow cpu pll to go higher than 1GHz
Claudiu Beznea
1
-14
/
+47
2020-12-19
clk: at91: sama7g5: decrease lower limit for MCK0 rate
Claudiu Beznea
1
-1
/
+1
2020-12-19
clk: at91: sama7g5: remove mck0 from parent list of other clocks
Claudiu Beznea
1
-29
/
+26
2020-12-19
clk: at91: clk-sam9x60-pll: allow runtime changes for pll
Claudiu Beznea
4
-41
/
+197
2020-12-19
clk: at91: sama7g5: add 5th divisor for mck0 layout and characteristics
Eugen Hristev
1
-2
/
+2
2020-12-19
clk: at91: clk-master: add 5th divisor for mck master
Eugen Hristev
2
-2
/
+2
2020-12-19
clk: at91: sama7g5: allow SYS and CPU PLLs to be exported and referenced in DT
Eugen Hristev
1
-2
/
+4
2020-12-19
dt-bindings: clock: at91: add sama7g5 pll defines
Eugen Hristev
1
-3
/
+3
2020-12-19
clk: at91: sama7g5: fix compilation error
Claudiu Beznea
1
-2
/
+4
2020-10-20
Merge branches 'clk-ingenic', 'clk-at91', 'clk-kconfig', 'clk-imx', 'clk-qcom...
Stephen Boyd
4
-8
/
+12
2020-10-14
clk: at91: sam9x60: support only two programmable clocks
Claudiu Beznea
1
-1
/
+1
2020-10-14
clk: at91: clk-sam9x60-pll: remove unused variable
Claudiu Beznea
1
-2
/
+1
2020-10-14
clk: at91: clk-main: update key before writing AT91_CKGR_MOR
Claudiu Beznea
1
-3
/
+8
2020-10-14
clk: at91: remove the checking of parent_name
Claudiu Beznea
1
-2
/
+2
2020-09-22
clk: at91: drop unused at91sam9g45_pcr_layout
Krzysztof Kozlowski
1
-7
/
+0
2020-07-24
clk: at91: sama7g5: add clock support for sama7g5
Claudiu Beznea
2
-0
/
+1060
2020-07-24
clk: at91: clk-utmi: add utmi support for sama7g5
Claudiu Beznea
2
-5
/
+102
2020-07-24
clk: at91: clk-sam9x60-pll: re-factor to support plls with multiple outputs
Claudiu Beznea
3
-186
/
+433
2020-07-24
clk: at91: clk-programmable: add mux_table option
Claudiu Beznea
13
-17
/
+38
2020-07-24
clk: at91: clk-peripheral: add support for changeable parent rate
Claudiu Beznea
9
-16
/
+119
2020-07-24
clk: at91: clk-master: add master clock support for SAMA7G5
Claudiu Beznea
2
-5
/
+312
2020-07-24
clk: at91: clk-generated: add mux_table option
Claudiu Beznea
5
-8
/
+16
2020-07-24
clk: at91: clk-generated: pass the id of changeable parent at registration
Claudiu Beznea
5
-35
/
+37
2020-07-24
clk: at91: replace conditional operator with double logical not
Claudiu Beznea
5
-8
/
+8
2020-07-24
clk: at91: sckc: register slow_rc with accuracy option
Claudiu Beznea
1
-2
/
+3
2020-07-24
clk: at91: sam9x60: fix main rc oscillator frequency
Claudiu Beznea
1
-1
/
+1
2020-07-24
clk: at91: sam9x60-pll: use frac when setting frequency
Claudiu Beznea
1
-4
/
+8
2020-07-24
clk: at91: sam9x60-pll: check fcore against ranges
Claudiu Beznea
2
-2
/
+12
2020-07-24
clk: at91: sam9x60-pll: use logical or for range check
Claudiu Beznea
1
-1
/
+1
2020-07-24
clk: at91: clk-sam9x60-pll: fix mul mask
Claudiu Beznea
1
-1
/
+1
2020-07-24
clk: at91: clk-generated: check best_rate against ranges
Claudiu Beznea
1
-2
/
+2
2020-07-24
clk: at91: clk-generated: continue if __clk_determine_rate() returns error
Claudiu Beznea
1
-1
/
+2
2020-07-24
clk: at91: fix possible dead lock in new drivers
Ahmad Fatoum
4
-4
/
+4
2020-05-27
clk: at91: allow setting all PMC clock parents via DT
Michał Mirosław
10
-10
/
+38
2020-05-27
clk: at91: allow setting PCKx parent via DT
Michał Mirosław
12
-13
/
+45
2020-05-27
clk: at91: optimize pmc data allocation
Michał Mirosław
12
-37
/
+20
2020-05-27
clk: at91: pmc: decrement node's refcount
Claudiu Beznea
1
-0
/
+1
2020-05-27
clk: at91: pmc: do not continue if compatible not located
Claudiu Beznea
1
-0
/
+2
2020-05-27
clk: at91: Add peripheral clock for PTC
Codrin Ciubotariu
1
-0
/
+1
2020-04-05
Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...
Linus Torvalds
7
-11
/
+913
2020-03-21
clk: at91: add at91rm9200 pmc driver
Alexandre Belloni
2
-0
/
+200
2020-02-18
clk: at91: move sam9x60's PLL register offsets to PMC header
Claudiu Beznea
1
-54
/
+37
2020-02-13
clk: at91: add at91sam9n12 pmc driver
Alexandre Belloni
2
-0
/
+239
2020-02-13
clk: at91: add sama5d3 pmc driver
Alexandre Belloni
2
-0
/
+241
2020-02-13
clk: at91: add at91sam9g45 pmc driver
Alexandre Belloni
2
-0
/
+221
[prev]
[next]