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:
starfive-tech/linux.git
JH7100_VisionFive_OH_dev
JH7110_VisionFive2_510_devel
JH7110_VisionFive2_6.1.y_devel
JH7110_VisionFive2_6.6.y_devel
JH7110_VisionFive2_devel
JH7110_VisionFive2_upstream
beaglev-5.13.y
beaglev_fedora_devel
buildroot-upstream
esmil_starlight
fedora-vic-7100_5.10.6
master
openwrt-6.1.y
rt-ethercat-release
rt-linux-release
rtthread_AMP
starfive-5.13
starfive-5.15-dubhe
starfive-6.1-dubhe
starfive-6.1.65-dubhe
starfive-6.6.10-dubhe
starfive-6.6.31-dubhe
starlight-5.14.y
visionfive
visionfive-5.13.y-devel
visionfive-5.15.y
visionfive-5.15.y-devel
visionfive-5.15.y_fedora_devel
visionfive-5.16.y
visionfive-5.17.y
visionfive-5.18.y
visionfive-5.19.y
visionfive-6.4.y
visionfive_fedora_devel
StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)
Andrey V.Kosteltsev
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path:
root
/
drivers
/
clk
/
imx
/
clk-imx8qxp.c
Age
Commit message (
Expand
)
Author
Files
Lines
2023-12-20
clk: imx: clk-imx8qxp: fix LVDS bypass, pixel and phy clocks
Alexander Stein
1
-4
/
+20
2023-10-04
clk: imx: imx8qxp: correct the enet clocks for i.MX8DXL
Shenwei Wang
1
-2
/
+9
2023-10-04
clk: imx: imx8qxp: Fix elcdif_pll clock
Robert Chiras
1
-1
/
+1
2023-07-19
clk: Explicitly include correct DT includes
Rob Herring
1
-1
/
+0
2022-01-29
clk: imx: Add imx8dxl clk driver
Jacky Bai
1
-0
/
+1
2021-12-03
clk: imx: use module_platform_driver
Miles Chen
1
-1
/
+1
2021-06-14
clk: imx: scu: add more scu clocks
Dong Aisheng
1
-2
/
+150
2021-06-14
clk: imx: scu: add enet rgmii gpr clocks
Dong Aisheng
1
-4
/
+18
2021-06-14
clk: imx8qm: add clock valid resource checking
Dong Aisheng
1
-0
/
+1
2021-06-14
clk: imx8qxp: add clock valid checking mechnism
Dong Aisheng
1
-3
/
+6
2021-06-14
clk: imx: scu: remove legacy scu clock binding support
Dong Aisheng
1
-124
/
+77
2021-01-05
clk: imx: clk-imx8qxp: Add some SCU clocks support for MIPI-LVDS subsystems
Liu Ying
1
-0
/
+10
2021-01-05
clk: imx: clk-imx8qxp: Register DC0 display clocks with imx_clk_scu2()
Liu Ying
1
-2
/
+10
2021-01-05
clk: imx: clk-imx8qxp: Add SCU clocks support for DC0 bypass clocks
Liu Ying
1
-0
/
+2
2021-01-05
clk: imx: clk-imx8qxp: Add SCU clocks support for DC0 PLL clocks
Liu Ying
1
-0
/
+2
2020-10-26
clk: imx: scu: add two cells binding support
Dong Aisheng
1
-60
/
+76
2020-08-22
clk: imx8qxp: Support building i.MX8QXP clock driver as module
Anson Huang
1
-0
/
+4
2019-02-21
clk: imx: scu: add fallback compatible string support
Aisheng Dong
1
-0
/
+1
2018-12-28
clk: imx8qxp: make the name of clock ID generic
Aisheng Dong
1
-77
/
+77
2018-12-15
clk: imx: add imx8qxp clk driver
Aisheng Dong
1
-0
/
+153