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starfive-tech/linux.git
JH7100_VisionFive_OH_dev
JH7110_VisionFive2_510_devel
JH7110_VisionFive2_6.1.y_devel
JH7110_VisionFive2_6.6.y_devel
JH7110_VisionFive2_devel
JH7110_VisionFive2_upstream
beaglev-5.13.y
beaglev_fedora_devel
buildroot-upstream
esmil_starlight
fedora-vic-7100_5.10.6
master
openwrt-6.1.y
rt-ethercat-release
rt-linux-release
rtthread_AMP
starfive-5.13
starfive-5.15-dubhe
starfive-6.1-dubhe
starfive-6.1.65-dubhe
starfive-6.6.10-dubhe
starfive-6.6.31-dubhe
starlight-5.14.y
visionfive
visionfive-5.13.y-devel
visionfive-5.15.y
visionfive-5.15.y-devel
visionfive-5.15.y_fedora_devel
visionfive-5.16.y
visionfive-5.17.y
visionfive-5.18.y
visionfive-5.19.y
visionfive-6.4.y
visionfive_fedora_devel
StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)
Andrey V.Kosteltsev
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path:
root
/
drivers
/
clk
/
mediatek
/
clk-pll.c
Age
Commit message (
Expand
)
Author
Files
Lines
2024-01-04
clk: mediatek: add pcw_chg_bit control for PLLs of MT7988
Sam Shih
1
-2
/
+3
2023-10-24
clk: mediatek: fix double free in mtk_clk_register_pllfh()
Dan Carpenter
1
-3
/
+3
2022-11-29
clk: mediatek: Export PLL operations symbols
Johnson Wang
1
-50
/
+34
2022-05-20
clk: mediatek: Switch to clk_hw provider APIs
Chen-Yu Tsai
1
-17
/
+18
2022-05-20
clk: mediatek: Replace 'struct clk' with 'struct clk_hw'
Chen-Yu Tsai
1
-12
/
+11
2022-05-19
clk: mediatek: use en_mask as a pure div_en_mask
Chun-Jie Chen
1
-8
/
+4
2022-02-17
clk: mediatek: Warn if clk IDs are duplicated
Chen-Yu Tsai
1
-0
/
+6
2022-02-17
clk: mediatek: pll: Implement error handling in register API
Chen-Yu Tsai
1
-4
/
+19
2022-02-17
clk: mediatek: pll: Clean up included headers
Chen-Yu Tsai
1
-5
/
+7
2022-02-17
clk: mediatek: pll: Implement unregister API
Chen-Yu Tsai
1
-0
/
+55
2022-02-17
clk: mediatek: pll: Split definitions into separate header file
Chen-Yu Tsai
1
-0
/
+1
2022-02-17
clk: mediatek: Use %pe to print errors
Chen-Yu Tsai
1
-2
/
+1
2021-09-15
clk: mediatek: support COMMON_CLK_MEDIATEK module build
Miles Chen
1
-0
/
+4
2021-09-15
clk: mediatek: Fix corner case of tuner_en_reg
Chun-Jie Chen
1
-1
/
+1
2021-07-27
clk: mediatek: Add configurable enable control to mtk_pll_data
Chun-Jie Chen
1
-5
/
+10
2021-07-27
clk: mediatek: Fix asymmetrical PLL enable and disable control
Chun-Jie Chen
1
-4
/
+16
2019-05-30
treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 174
Thomas Gleixner
1
-9
/
+1
2019-04-11
clk: mediatek: Allow changing PLL rate when it is off
James Liao
1
-11
/
+2
2019-04-11
clk: mediatek: Add configurable pcw_chg_reg to mtk_pll_data
Weiyi Lu
1
-6
/
+11
2019-04-11
clk: mediatek: Add configurable pcwibits and fmin to mtk_pll_data
Owen Chen
1
-4
/
+11
2019-04-11
clk: mediatek: Disable tuner_en before change PLL rate
Owen Chen
1
-14
/
+34
2017-11-02
clk: mediatek: add the option for determining PLL source clock
Chen Zhong
1
-1
/
+4
2017-11-02
clk: mediatek: Add MT2712 clock support
weiyi.lu@mediatek.com
1
-2
/
+11
2016-11-09
clk: mediatek: Add MT2701 clock support
Shunli Wang
1
-0
/
+1
2016-08-19
clk: mediatek: remove __init from clk registration functions
James Liao
1
-1
/
+1
2015-10-01
clk: mediatek: Add USB clock support in MT8173 APMIXEDSYS
James Liao
1
-6
/
+1
2015-07-28
clk: mediatek: Add MT8173 MMPLL change rate support
James Liao
1
-3
/
+15
2015-07-28
clk: mediatek: Fix calculation of PLL rate settings
James Liao
1
-2
/
+2
2015-07-28
clk: mediatek: Fix PLL registers setting flow
James Liao
1
-9
/
+12
2015-05-20
clk: mediatek: Initialize clk_init_data
Ricky Liang
1
-1
/
+1
2015-05-06
clk: mediatek: Add initial common clock support for Mediatek SoCs.
James Liao
1
-0
/
+332