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starfive-tech/linux.git
JH7100_VisionFive_OH_dev
JH7110_VisionFive2_510_devel
JH7110_VisionFive2_6.1.y_devel
JH7110_VisionFive2_6.6.y_devel
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starfive-5.13
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visionfive-5.18.y
visionfive-5.19.y
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visionfive_fedora_devel
StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)
Andrey V.Kosteltsev
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path:
root
/
drivers
/
clk
/
meson
/
axg.c
Age
Commit message (
Expand
)
Author
Files
Lines
2024-04-10
clk: meson: fix module license to GPL only
Neil Armstrong
1
-1
/
+1
2024-02-05
clk: meson: Add missing clocks to axg_clk_regmaps
Igor Prusov
1
-0
/
+2
2023-08-31
Merge branches 'clk-versa', 'clk-strdup', 'clk-amlogic', 'clk-allwinner' and ...
Stephen Boyd
1
-142
/
+143
2023-08-08
clk: meson: eeclk: move bindings include to main driver
Neil Armstrong
1
-0
/
+2
2023-08-08
clk: meson: migrate meson-eeclk out of hw_onecell_data to drop NR_CLKS
Neil Armstrong
1
-142
/
+141
2023-07-19
clk: Explicitly include correct DT includes
Rob Herring
1
-1
/
+1
2021-02-09
clk: meson: axg: Remove MIPI enable clock gate
Remi Pommarel
1
-3
/
+0
2020-11-23
clk: meson: enable building as modules
Kevin Hilman
1
-1
/
+4
2020-11-23
clk: meson: axg: add MIPI DSI Host clock
Neil Armstrong
1
-0
/
+66
2020-11-23
clk: meson: axg: add Video Clocks
Neil Armstrong
1
-0
/
+753
2019-07-29
clk: meson: clk-regmap: migrate to new parent description method
Alexandre Mergnat
1
-0
/
+3
2019-07-29
clk: meson: axg: migrate to the new parent description method
Alexandre Mergnat
1
-60
/
+144
2019-05-20
clk: meson: axg: spread spectrum is on mpll2
Jerome Brunet
1
-5
/
+5
2019-02-04
clk: meson: factorise meson64 peripheral clock controller drivers
Jerome Brunet
1
-49
/
+10
2019-02-02
clk: meson: rework and clean drivers dependencies
Jerome Brunet
1
-1
/
+4
2019-01-18
clk: meson: axg: claim clock controller input clock from DT
Jerome Brunet
1
-8
/
+19
2018-11-08
clk: meson: axg: mark fdiv2 and fdiv3 as critical
Jerome Brunet
1
-0
/
+13
2018-09-26
clk: meson-axg: pcie: drop the mpll3 clock parent
Yixun Lan
1
-2
/
+4
2018-09-26
clk: meson: clk-pll: drop hard-coded rates from pll tables
Jerome Brunet
1
-37
/
+36
2018-09-26
clk: meson: clk-pll: remove od parameters
Jerome Brunet
1
-130
/
+154
2018-09-26
clk: meson: clk-pll: drop CLK_GET_RATE_NOCACHE where unnecessary
Jerome Brunet
1
-1
/
+0
2018-09-26
clk: meson: clk-pll: add enable bit
Jerome Brunet
1
-3
/
+25
2018-07-09
clk: meson: add gen_clk
Jerome Brunet
1
-1
/
+63
2018-07-09
clk: meson-axg: add clocks required by pcie driver
Yixun Lan
1
-0
/
+145
2018-07-09
clk: meson: remove obsolete register access
Jerome Brunet
1
-35
/
+2
2018-05-21
clk: meson: axg: let mpll clocks round closest
Jerome Brunet
1
-0
/
+4
2018-03-15
clk: meson: Drop unused local variable and add static
Stephen Boyd
1
-2
/
+2
2018-03-13
clk: meson: add fdiv clock gates
Jerome Brunet
1
-10
/
+85
2018-03-13
clk: meson: add mpll pre-divider
Jerome Brunet
1
-4
/
+20
2018-03-13
clk: meson: axg: add hifi pll clock
Jerome Brunet
1
-0
/
+55
2018-03-13
clk: meson: add gp0 frac parameter for axg and gxl
Jerome Brunet
1
-1
/
+6
2018-03-13
clk: meson: remove special gp0 lock loop
Jerome Brunet
1
-1
/
+0
2018-03-13
clk: meson: poke pll CNTL last
Jerome Brunet
1
-1
/
+1
2018-03-13
clk: meson: use hhi syscon if available
Jerome Brunet
1
-13
/
+30
2018-03-13
clk: meson: split divider and gate part of mpll
Jerome Brunet
1
-28
/
+72
2018-03-13
clk: meson: migrate plls clocks to clk_regmap
Jerome Brunet
1
-105
/
+108
2018-03-13
clk: meson: migrate mplls clocks to clk_regmap
Jerome Brunet
1
-124
/
+121
2018-03-13
clk: meson: migrate muxes to clk_regmap
Jerome Brunet
1
-35
/
+25
2018-03-13
clk: meson: migrate dividers to clk_regmap
Jerome Brunet
1
-35
/
+26
2018-03-13
clk: meson: migrate gates to clk_regmap
Jerome Brunet
1
-37
/
+35
2018-03-13
clk: meson: add regmap to the clock controllers
Jerome Brunet
1
-1
/
+14
2018-03-13
clk: meson: remove obsolete comments
Jerome Brunet
1
-5
/
+0
2018-03-13
clk: meson: only one loop index is necessary in probe
Jerome Brunet
1
-4
/
+4
2018-03-13
clk: meson: use devm_of_clk_add_hw_provider
Jerome Brunet
1
-2
/
+2
2018-03-13
clk: meson: use dev pointer where possible
Jerome Brunet
1
-4
/
+4
2018-02-12
clk: meson: add axg misc bit to the mpll driver
Jerome Brunet
1
-0
/
+20
2018-02-12
clk: meson: axg: fix the od shift of the sys_pll
Yixun Lan
1
-1
/
+1
2018-02-12
clk: meson: axg: add the fractional part of the fixed_pll
Jerome Brunet
1
-0
/
+5
2018-02-12
clk: meson: remove useless pll rate params tables
Jerome Brunet
1
-94
/
+0
2018-01-11
clk: meson-axg: fix potential NULL dereference in axg_clkc_probe()
weiyongjun (A)
1
-0
/
+2
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