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starfive-tech/linux.git
JH7100_VisionFive_OH_dev
JH7110_VisionFive2_510_devel
JH7110_VisionFive2_6.1.y_devel
JH7110_VisionFive2_6.6.y_devel
JH7110_VisionFive2_devel
JH7110_VisionFive2_upstream
beaglev-5.13.y
beaglev_fedora_devel
buildroot-upstream
esmil_starlight
fedora-vic-7100_5.10.6
master
openwrt-6.1.y
rt-ethercat-release
rt-linux-release
rtthread_AMP
starfive-5.13
starfive-5.15-dubhe
starfive-6.1-dubhe
starfive-6.1.65-dubhe
starfive-6.6.10-dubhe
starfive-6.6.31-dubhe
starlight-5.14.y
visionfive
visionfive-5.13.y-devel
visionfive-5.15.y
visionfive-5.15.y-devel
visionfive-5.15.y_fedora_devel
visionfive-5.16.y
visionfive-5.17.y
visionfive-5.18.y
visionfive-5.19.y
visionfive-6.4.y
visionfive_fedora_devel
StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)
Andrey V.Kosteltsev
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path:
root
/
drivers
/
clk
/
meson
/
meson-aoclk.c
Age
Commit message (
Expand
)
Author
Files
Lines
2024-04-10
clk: meson: fix module license to GPL only
Neil Armstrong
1
-1
/
+1
2023-08-31
Merge branches 'clk-versa', 'clk-strdup', 'clk-amlogic', 'clk-allwinner' and ...
Stephen Boyd
1
-5
/
+4
2023-08-08
clk: meson: migrate meson-aoclk out of hw_onecell_data to drop NR_CLKS
Neil Armstrong
1
-5
/
+4
2023-07-19
clk: Explicitly include correct DT includes
Rob Herring
1
-1
/
+1
2022-08-20
clk: meson: Hold reference returned by of_get_parent()
Liang He
1
-1
/
+4
2020-11-23
clk: meson: enable building as modules
Kevin Hilman
1
-0
/
+4
2020-10-14
clk: meson: use semicolons rather than commas to separate statements
Julia Lawall
1
-1
/
+1
2019-07-29
clk: meson: remove ao input bypass clocks
Alexandre Mergnat
1
-37
/
+0
2019-02-02
clk: meson: rework and clean drivers dependencies
Jerome Brunet
1
-0
/
+2
2019-01-18
clk: meson: ao-clkc: claim clock controller input clocks from DT
Jerome Brunet
1
-1
/
+36
2019-01-07
clk: meson: clean-up clock registration
Jerome Brunet
1
-5
/
+10
2018-05-15
clk: meson: aoclk: refactor common code into dedicated file
Yixun Lan
1
-0
/
+81