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starfive-tech/linux.git
JH7100_VisionFive_OH_dev
JH7110_VisionFive2_510_devel
JH7110_VisionFive2_6.1.y_devel
JH7110_VisionFive2_6.6.y_devel
JH7110_VisionFive2_devel
JH7110_VisionFive2_upstream
beaglev-5.13.y
beaglev_fedora_devel
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esmil_starlight
fedora-vic-7100_5.10.6
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openwrt-6.1.y
rt-ethercat-release
rt-linux-release
rtthread_AMP
starfive-5.13
starfive-5.15-dubhe
starfive-6.1-dubhe
starfive-6.1.65-dubhe
starfive-6.6.10-dubhe
starfive-6.6.31-dubhe
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visionfive
visionfive-5.13.y-devel
visionfive-5.15.y
visionfive-5.15.y-devel
visionfive-5.15.y_fedora_devel
visionfive-5.16.y
visionfive-5.17.y
visionfive-5.18.y
visionfive-5.19.y
visionfive-6.4.y
visionfive_fedora_devel
StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)
Andrey V.Kosteltsev
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path:
root
/
drivers
/
clk
/
meson
/
meson8b.h
Age
Commit message (
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)
Author
Files
Lines
2023-08-08
clk: meson: meson8b: move bindings include to main driver
Neil Armstrong
1
-7
/
+0
2023-08-08
dt-bindings: clk: meson8b-clkc: expose all clock ids
Neil Armstrong
1
-108
/
+0
2023-08-08
clk: meson: migrate meson8b out of hw_onecell_data to drop NR_CLKS
Neil Armstrong
1
-2
/
+0
2021-09-23
clk: meson: meson8b: Initialize the HDMI PLL registers
Martin Blumenstingl
1
-1
/
+12
2021-09-23
clk: meson: meson8b: Add the vid_pll_lvds_en gate clock
Martin Blumenstingl
1
-1
/
+2
2021-09-23
clk: meson: meson8b: Export the video clocks
Martin Blumenstingl
1
-11
/
+1
2020-07-21
Merge branch 'clk-amlogic' into clk-next
Stephen Boyd
1
-1
/
+3
2020-07-11
Replace HTTP links with HTTPS ones: Common CLK framework
Alexander A. Klimov
1
-1
/
+1
2020-07-09
clk: meson: meson8b: add the vclk2_en gate clock
Martin Blumenstingl
1
-1
/
+2
2020-07-09
clk: meson: meson8b: add the vclk_en gate clock
Martin Blumenstingl
1
-1
/
+2
2020-05-02
clk: meson: meson8b: Don't rely on u-boot to init all GP_PLL registers
Martin Blumenstingl
1
-0
/
+4
2020-04-14
clk: meson8b: export the HDMI system clock
Martin Blumenstingl
1
-1
/
+0
2019-06-11
clk: meson: meson8b: add the cts_i958 clock
Martin Blumenstingl
1
-1
/
+1
2019-06-11
clk: meson: meson8b: add the cts_mclk_i958 clocks
Martin Blumenstingl
1
-1
/
+4
2019-06-11
clk: meson: meson8b: add the cts_amclk clocks
Martin Blumenstingl
1
-1
/
+4
2019-04-01
clk: meson: meson8b: add the video decoder clock trees
Martin Blumenstingl
1
-1
/
+16
2019-04-01
clk: meson: meson8b: add the VPU clock trees
Martin Blumenstingl
1
-1
/
+8
2019-04-01
clk: meson: meson8b: add support for the GP_PLL clock on Meson8m2
Martin Blumenstingl
1
-1
/
+4
2019-02-13
clk: meson: meson8b: fix the naming of the APB clocks
Martin Blumenstingl
1
-1
/
+1
2019-01-07
clk: meson: meson8b: add the GPU clock tree
Martin Blumenstingl
1
-1
/
+8
2018-12-03
clk: meson: meson8b: add the read-only video clock trees
Martin Blumenstingl
1
-2
/
+51
2018-12-03
clk: meson: meson8b: add the fractional divider for vid_pll_dco
Martin Blumenstingl
1
-0
/
+1
2018-11-23
clk: meson: meson8b: add the CPU clock post divider clocks
Martin Blumenstingl
1
-1
/
+12
2018-11-23
clk: meson: meson8b: rename cpu_div2/cpu_div3 to cpu_in_div2/cpu_in_div3
Martin Blumenstingl
1
-2
/
+2
2018-09-26
clk: meson: clk-pll: remove od parameters
Jerome Brunet
1
-1
/
+4
2018-05-18
clk: meson: use SPDX license identifiers consistently
Jerome Brunet
1
-12
/
+1
2018-05-15
clk: meson: meson8b: add support for the NAND clocks
Martin Blumenstingl
1
-1
/
+4
2018-03-13
clk: meson: add fdiv clock gates
Jerome Brunet
1
-1
/
+6
2018-03-13
clk: meson: add mpll pre-divider
Jerome Brunet
1
-1
/
+2
2018-03-13
clk: meson: rework meson8b cpu clock
Jerome Brunet
1
-1
/
+6
2018-03-13
clk: meson: split divider and gate part of mpll
Jerome Brunet
1
-1
/
+5
2017-08-04
clk: meson: meson8b: register the built-in reset controller
Martin Blumenstingl
1
-1
/
+8
2017-08-04
clk: meson8b: expose every clock in the bindings
Jerome Brunet
1
-99
/
+4
2017-06-12
clk: meson8b: export the ethernet gate clock
Martin Blumenstingl
1
-1
/
+1
2017-06-12
clk: meson8b: export the USB clocks
Martin Blumenstingl
1
-5
/
+5
2017-06-12
clk: meson8b: export the gate clock for the HW random number generator
Martin Blumenstingl
1
-1
/
+1
2017-06-12
clk: meson8b: export the SDIO clock
Martin Blumenstingl
1
-1
/
+1
2017-06-12
clk: meson8b: export the SAR ADC clocks
Martin Blumenstingl
1
-2
/
+2
2017-03-27
clk: meson8b: add the mplls clocks 0, 1 and 2
Jerome Brunet
1
-1
/
+19
2016-09-02
meson: clk: Add support for clock gates
Alexander Müller
1
-0
/
+5
2016-09-02
clk: meson: Copy meson8b CLKID defines to private header file
Alexander Müller
1
-0
/
+107
2016-09-02
meson: clk: Rename register names according to Amlogic datasheet
Alexander Müller
1
-6
/
+5
2016-09-02
meson: clk: Move register definitions to meson8b.h
Alexander Müller
1
-0
/
+40