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2023-08-31Merge branch 'clk-qcom' into clk-nextStephen Boyd34-1188/+4598
* clk-qcom: (87 commits) clk: qcom: Fix SM_GPUCC_8450 dependencies clk: qcom: smd-rpm: Set XO rate and CLK_IS_CRITICAL on PCNoC clk: qcom: smd-rpm: Add a way to define bus clocks with rate and flags clk: qcom: gcc-ipq5018: change some variable static clk: qcom: gcc-ipq4019: add missing networking resets dt-bindings: clock: qcom: ipq4019: add missing networking resets clk: qcom: gcc-msm8917: Enable GPLL0_SLEEP_CLK_SRC dt-bindings: clock: gcc-msm8917: Add definition for GPLL0_SLEEP_CLK_SRC clk: qcom: gcc-qdu1000: Update the RCGs ops clk: qcom: gcc-qdu1000: Update the SDCC clock RCG ops clk: qcom: gcc-qdu1000: Add support for GDSCs clk: qcom: gcc-qdu1000: Add gcc_ddrss_ecpri_gsi_clk support clk: qcom: gcc-qdu1000: Register gcc_gpll1_out_even clock clk: qcom: gcc-qdu1000: Fix clkref clocks handling clk: qcom: gcc-qdu1000: Fix gcc_pcie_0_pipe_clk_src clock handling dt-bindings: clock: Update GCC clocks for QDU1000 and QRU1000 SoCs clk: qcom: gcc-sm8450: Use floor ops for SDCC RCGs clk: qcom: ipq5332: drop the gcc_apss_axi_clk_src clock clk: qcom: ipq5332: drop the mem noc clocks clk: qcom: gcc-msm8998: Don't check halt bit on some branch clks ...
2023-08-31Merge branches 'clk-imx', 'clk-samsung', 'clk-annotate', 'clk-marvell' and ↵Stephen Boyd2-2/+2
'clk-lmk' into clk-next - Add __counted_by to struct clk_hw_onecell_data and struct spmi_pmic_div_clk_cc - Remove non-OF mmp clk drivers - Move number of clks from DT headers to drivers * clk-imx: clk: imx: pll14xx: dynamically configure PLL for 393216000/361267200Hz clk: imx: pll14xx: align pdiv with reference manual clk: imx: composite-8m: fix clock pauses when set_rate would be a no-op clk: imx25: make __mx25_clocks_init return void clk: imx25: print silicon revision during init dt-bindings: clocks: imx8mp: make sai4 a dummy clock clk: imx8mp: fix sai4 clock clk: imx: imx8ulp: update SPLL2 type clk: imx: pllv4: Fix SPLL2 MULT range clk: imx: imx8: add audio clock mux driver dt-bindings: clock: fsl,imx8-acm: Add audio clock mux support clk: imx: clk-imx8qxp-lpcg: Convert to devm_platform_ioremap_resource() clk: imx: clk-gpr-mux: Simplify .determine_rate() clk: imx: Add 519.75MHz frequency support for imx9 pll clk: imx93: Add PDM IPG clk dt-bindings: clock: imx93: Add PDM IPG clk * clk-samsung: dt-bindings: clock: samsung: remove define with number of clocks clk: samsung: exynoautov9: do not define number of clocks in bindings clk: samsung: exynos850: do not define number of clocks in bindings clk: samsung: exynos7885: do not define number of clocks in bindings clk: samsung: exynos5433: do not define number of clocks in bindings clk: samsung: exynos5420: do not define number of clocks in bindings clk: samsung: exynos5410: do not define number of clocks in bindings clk: samsung: exynos5260: do not define number of clocks in bindings clk: samsung: exynos5250: do not define number of clocks in bindings clk: samsung: exynos4: do not define number of clocks in bindings clk: samsung: exynos3250: do not define number of clocks in bindings * clk-annotate: clk: qcom: clk-spmi-pmic-div: Annotate struct spmi_pmic_div_clk_cc with __counted_by clk: Annotate struct clk_hw_onecell_data with __counted_by * clk-marvell: clk: pxa910: Move number of clocks to driver source clk: pxa1928: Move number of clocks to driver source clk: pxa168: Move number of clocks to driver source clk: mmp2: Move number of clocks to driver source clk: mmp: Remove old non-OF clock drivers * clk-lmk: clk: lmk04832: Support using PLL1_LD as SPI readback pin clk: lmk04832: Don't disable vco clock on probe fail clk: lmk04832: Set missing parent_names for output clocks
2023-08-30clk: qcom: Fix SM_GPUCC_8450 dependenciesNathan Chancellor1-0/+1
CONFIG_SM_GCC_8450 depends on ARM64 but it is selected by CONFIG_SM_GPUCC_8450, which can be selected on ARM, resulting in a Kconfig warning. WARNING: unmet direct dependencies detected for SM_GCC_8450 Depends on [n]: COMMON_CLK [=y] && COMMON_CLK_QCOM [=y] && (ARM64 || COMPILE_TEST [=n]) Selected by [y]: - SM_GPUCC_8450 [=y] && COMMON_CLK [=y] && COMMON_CLK_QCOM [=y] Add the same dependencies to CONFIG_SM_GPUCC_8450 to resolve the warning. Fixes: 728692d49edc ("clk: qcom: Add support for SM8450 GPUCC") Signed-off-by: Nathan Chancellor <nathan@kernel.org> Link: https://lore.kernel.org/r/20230829-fix-sm_gpucc_8550-deps-v1-1-d751f6cd35b2@kernel.org Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-08-22clk: qcom: clk-spmi-pmic-div: Annotate struct spmi_pmic_div_clk_cc with ↵Kees Cook1-1/+1
__counted_by Prepare for the coming implementation by GCC and Clang of the __counted_by attribute. Flexible array members annotated with __counted_by can have their accesses bounds-checked at run-time checking via CONFIG_UBSAN_BOUNDS (for array indexing) and CONFIG_FORTIFY_SOURCE (for strcpy/memcpy-family functions). As found with Coccinelle[1], add __counted_by for struct spmi_pmic_div_clk_cc. [1] https://github.com/kees/kernel-tools/blob/trunk/coccinelle/examples/counted_by.cocci Cc: Bjorn Andersson <andersson@kernel.org> Cc: Andy Gross <agross@kernel.org> Cc: Konrad Dybcio <konrad.dybcio@linaro.org> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@kernel.org> Cc: linux-arm-msm@vger.kernel.org Cc: linux-clk@vger.kernel.org Signed-off-by: Kees Cook <keescook@chromium.org> Link: https://lore.kernel.org/r/20230817202941.never.657-kees@kernel.org Reviewed-by: Gustavo A. R. Silva <gustavoars@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-08-22clk: Annotate struct clk_hw_onecell_data with __counted_byKees Cook1-1/+1
Prepare for the coming implementation by GCC and Clang of the __counted_by attribute. Flexible array members annotated with __counted_by can have their accesses bounds-checked at run-time checking via CONFIG_UBSAN_BOUNDS (for array indexing) and CONFIG_FORTIFY_SOURCE (for strcpy/memcpy-family functions). As found with Coccinelle[1], add __counted_by for struct clk_hw_onecell_data. Additionally, since the element count member must be set before accessing the annotated flexible array member, move its initialization earlier. [1] https://github.com/kees/kernel-tools/blob/trunk/coccinelle/examples/counted_by.cocci Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@kernel.org> Cc: Joel Stanley <joel@jms.id.au> Cc: Andrew Jeffery <andrew@aj.id.au> Cc: Taichi Sugaya <sugaya.taichi@socionext.com> Cc: Takao Orito <orito.takao@socionext.com> Cc: Qin Jian <qinjian@cqplus1.com> Cc: Andrew Lunn <andrew@lunn.ch> Cc: Gregory Clement <gregory.clement@bootlin.com> Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Cc: Andy Gross <agross@kernel.org> Cc: Bjorn Andersson <andersson@kernel.org> Cc: Konrad Dybcio <konrad.dybcio@linaro.org> Cc: Sergio Paracuellos <sergio.paracuellos@gmail.com> Cc: Matthias Brugger <matthias.bgg@gmail.com> Cc: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Cc: Maxime Ripard <mripard@kernel.org> Cc: Chen-Yu Tsai <wens@csie.org> Cc: Jernej Skrabec <jernej.skrabec@gmail.com> Cc: David Airlie <airlied@gmail.com> Cc: Daniel Vetter <daniel@ffwll.ch> Cc: Samuel Holland <samuel@sholland.org> Cc: Vinod Koul <vkoul@kernel.org> Cc: Kishon Vijay Abraham I <kishon@kernel.org> Cc: linux-clk@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-aspeed@lists.ozlabs.org Cc: linux-arm-msm@vger.kernel.org Cc: linux-mediatek@lists.infradead.org Cc: dri-devel@lists.freedesktop.org Cc: linux-sunxi@lists.linux.dev Cc: linux-phy@lists.infradead.org Signed-off-by: Kees Cook <keescook@chromium.org> Link: https://lore.kernel.org/r/20230817203019.never.795-kees@kernel.org Reviewed-by: Gustavo A. R. Silva <gustavoars@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-08-18clk: qcom: smd-rpm: Set XO rate and CLK_IS_CRITICAL on PCNoCKonrad Dybcio1-1/+1
On all supported SoCs to date, the PCNoC (a.k.a CNoC_PERIPH) clock must be always-on as long as the APSS is online and only has to run at 19.2 MHz. Define it to be as such in the ACTIVE domain. Some SoCs use that clock for bus scaling, while others just need it for reaching the hardware. This commit will hurt neither. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20230731-topic-pcnoc-v1-2-452dd36d11d7@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-08-18clk: qcom: smd-rpm: Add a way to define bus clocks with rate and flagsKonrad Dybcio1-8/+15
Some clocks, at least PCNoC (a.k.a CNoC_PERIPH) need to be always on, at least on the ACTIVE side, regardless of whether they're used for bus scaling or not. Introduce a new macro to preset non-INT_MAX rates and clk flags to make it easy and work implicitly through the CCF. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20230731-topic-pcnoc-v1-1-452dd36d11d7@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-08-18clk: qcom: gcc-ipq5018: change some variable staticYang Yingliang1-2/+2
lpass_axim_clk_src and lpass_sway_clk_src are only used in gcc-ipq5018.c now, change them to static. Fixes: e3fdbef1bab8 ("clk: qcom: Add Global Clock controller (GCC) driver for IPQ5018") Signed-off-by: Yang Yingliang <yangyingliang@huawei.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20230816080113.1222352-1-yangyingliang@huawei.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-08-15clk: qcom: gcc-ipq4019: add missing networking resetsRobert Marko1-0/+6
IPQ4019 has more networking related resets that will be required for future wired networking support, so lets add them. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Link: https://lore.kernel.org/r/20230814104119.96858-2-robert.marko@sartura.hr Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-08-14clk: qcom: gcc-msm8917: Enable GPLL0_SLEEP_CLK_SRCOtto Pflüger1-1/+2
This is the parent clock of gpll0_early, so it needs to be enabled for gpll0_early to return the correct rate. Enable GPLL0_SLEEP_CLK_SRC by adding its existing definition to the clock list. This clock also doesn't work with clk_alpha_pll_ops, use clk_branch_simple_ops instead to make it enable and disable correctly. Signed-off-by: Otto Pflüger <otto.pflueger@abscue.de> Link: https://lore.kernel.org/r/20230802170317.205112-3-otto.pflueger@abscue.de Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-08-14clk: qcom: gcc-qdu1000: Update the RCGs opsImran Shaik1-29/+29
The clock RCGs are required to be parked at safe clock source(XO) during disable as per the hardware expectation and clk_rcg2_shared_ops are the closest implementation for the same. Hence update the clock RCG ops to clk_rcg2_shared_ops. Signed-off-by: Imran Shaik <quic_imrashai@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20230803105741.2292309-9-quic_imrashai@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-08-14clk: qcom: gcc-qdu1000: Update the SDCC clock RCG opsImran Shaik1-2/+2
Update the GCC SDCC clock RCG ops to clk_rcg2_floor_ops to avoid the overclocking issues on QDU1000 and QRU1000 SoCs. Signed-off-by: Imran Shaik <quic_imrashai@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20230803105741.2292309-8-quic_imrashai@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-08-14clk: qcom: gcc-qdu1000: Add support for GDSCsImran Shaik1-0/+42
Add the GDSCs support for QDU1000 and QRU1000 SoCs. Co-developed-by: Taniya Das <quic_tdas@quicinc.com> Signed-off-by: Taniya Das <quic_tdas@quicinc.com> Signed-off-by: Imran Shaik <quic_imrashai@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20230803105741.2292309-7-quic_imrashai@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-08-14clk: qcom: gcc-qdu1000: Add gcc_ddrss_ecpri_gsi_clk supportImran Shaik1-0/+21
Add the gcc_ddrss_ecpri_gsi_clk support as per the latest hardware version of QDU1000 and QRU100 SoCs. Signed-off-by: Imran Shaik <quic_imrashai@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20230803105741.2292309-6-quic_imrashai@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-08-14clk: qcom: gcc-qdu1000: Register gcc_gpll1_out_even clockImran Shaik1-0/+1
gcc_gpll1_out_even clock is referenced as a parent, but not registered with the clock framework. Hence add support to register the same. Fixes: 1c9efb0bc040 ("clk: qcom: Add QDU1000 and QRU1000 GCC support") Signed-off-by: Imran Shaik <quic_imrashai@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20230803105741.2292309-5-quic_imrashai@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-08-14clk: qcom: gcc-qdu1000: Fix clkref clocks handlingImran Shaik1-6/+4
Update the GCC clkref clock's halt_check to BRANCH_HALT, as it's status bit is not inverted in the latest hardware version of QDU1000 and QRU1000 SoCs. While at it, fix the gcc clkref clock ops as well. Fixes: 1c9efb0bc040 ("clk: qcom: Add QDU1000 and QRU1000 GCC support") Signed-off-by: Imran Shaik <quic_imrashai@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20230803105741.2292309-4-quic_imrashai@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-08-14clk: qcom: gcc-qdu1000: Fix gcc_pcie_0_pipe_clk_src clock handlingImran Shaik1-17/+6
Fix the gcc pcie pipe clock handling as per the clk_regmap_phy_mux_ops implementation to let the clock framework automatically park the clock at XO when the clock is switched off and restore the parent when the clock is switched on. Fixes: 1c9efb0bc040 ("clk: qcom: Add QDU1000 and QRU1000 GCC support") Co-developed-by: Taniya Das <quic_tdas@quicinc.com> Signed-off-by: Taniya Das <quic_tdas@quicinc.com> Signed-off-by: Imran Shaik <quic_imrashai@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20230803105741.2292309-3-quic_imrashai@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-08-14clk: qcom: gcc-sm8450: Use floor ops for SDCC RCGsKonrad Dybcio1-2/+2
Use the floor ops to prevent warnings like this at suspend exit and boot: mmc0: Card appears overclocked; req 800000 Hz, actual 25000000 Hz Fixes: db0c944ee92b ("clk: qcom: Add clock driver for SM8450") Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Vinod Koul <vkoul@kernel.org> Link: https://lore.kernel.org/r/20230811-topic-8450_clk-v1-1-88031478d548@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-08-14clk: qcom: ipq5332: drop the gcc_apss_axi_clk_src clockKathiravan T1-72/+39
With the removal of the mem noc clocks in the commit e224dc703521 ("clk: qcom: gcc-ipq5332: drop the mem noc clocks"), we can drop the gcc_apss_axi_clk_src clock as well, since there are no clocks uses this clock as a parent. Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com> Link: https://lore.kernel.org/r/20230710102807.1189942-3-quic_kathirav@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-08-14clk: qcom: ipq5332: drop the mem noc clocksKathiravan T1-95/+0
Due to the recent design changes, all the mem noc clocks will be configured by the bootloaders and it will be access protected by the TZ firmware. So drop these clocks from the GCC driver. Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com> Link: https://lore.kernel.org/r/20230710102807.1189942-2-quic_kathirav@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-08-14clk: qcom: gcc-msm8998: Don't check halt bit on some branch clksKonrad Dybcio1-3/+3
Some branch clocks are governed externally and we're only supposed to send a request concerning their shutdown, not actually ensure it happens. Use the BRANCH_HALT_SKIP define to skip checking the halt bit. Reviewed-by: Jeffrey Hugo <quic_jhugo@quicinc.com> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20230622-topic-8998clk-v2-6-6222fbc2916b@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-08-14clk: qcom: gpucc-msm8998: Use the correct GPLL0 leg with old DTsKonrad Dybcio1-1/+1
GPUCC has its own GPLL0 legs - one for 1-1 and one for div-2 output. Add .name lookup to make sure older DTs consume the correct clock. Reviewed-by: Jeffrey Hugo <quic_jhugo@quicinc.com> Tested-by: Jeffrey Hugo <quic_jhugo@quicinc.com> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20230622-topic-8998clk-v2-5-6222fbc2916b@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-08-14clk: qcom: mmcc-msm8998: Properly consume GPLL0 inputsKonrad Dybcio1-27/+8
Up until now, the GPLL0_DIV MMSS input has been modeled as a fixed child of MMSS_GPLL0_DIV that's always-on. Properly representing the former in the GCC driver makes us unable to keep doing so. Consume MSS_GPLL0_DIV through fw_name ("gpll0_div") as well as add a fixed .name link to keep backwards compatibility. Reviewed-by: Jeffrey Hugo <quic_jhugo@quicinc.com> Tested-by: Jeffrey Hugo <quic_jhugo@quicinc.com> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20230622-topic-8998clk-v2-4-6222fbc2916b@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-08-14clk: qcom: gcc-msm8998: Control MMSS and GPUSS GPLL0 outputs properlyKonrad Dybcio1-0/+58
Up until now, we've been relying on some non-descript hardware magic to pinkypromise turn the clocks on for us. While new SoCs shine with that feature, MSM8998 can not always be fully trusted. Register the MMSS and GPUSS GPLL0 legs with the CCF to allow for manual enable voting. Reviewed-by: Jeffrey Hugo <quic_jhugo@quicinc.com> Tested-by: Jeffrey Hugo <quic_jhugo@quicinc.com> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20230622-topic-8998clk-v2-3-6222fbc2916b@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-08-11clk: qcom: Add Global Clock controller (GCC) driver for IPQ5018Sricharan Ramabadhran3-0/+3733
Add support for the global clock controller found on IPQ5018 based devices. Acked-by: Konrad Dybcio <konrad.dybcio@linaro.org> Co-developed-by: Varadarajan Narayanan <quic_varada@quicinc.com> Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com> Co-developed-by: Gokul Sriram Palanisamy <quic_gokulsri@quicinc.com> Signed-off-by: Gokul Sriram Palanisamy <quic_gokulsri@quicinc.com> Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com> Link: https://lore.kernel.org/r/1690533192-22220-3-git-send-email-quic_srichara@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-08-04clk: qcom: gcc-sm6350: Fix gcc_sdcc2_apps_clk_srcLuca Weiss1-0/+1
GPLL7 is not on by default, which causes a "gcc_sdcc2_apps_clk_src: rcg didn't update its configuration" error when booting. Set .flags = CLK_OPS_PARENT_ENABLE to fix the error. Fixes: 131abae905df ("clk: qcom: Add SM6350 GCC driver") Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20230804-sm6350-sdcc2-v1-1-3d946927d37d@fairphone.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-08-04clk: qcom: reset: Use the correct type of sleep/delay based on lengthKonrad Dybcio1-1/+2
Use the fsleep() helper that (based on the length of the delay, see: [1]) chooses the correct sleep/delay functions. [1] https://www.kernel.org/doc/Documentation/timers/timers-howto.txt Fixes: 2cb8a39b6781 ("clk: qcom: reset: Allow specifying custom reset delay") Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20230726-topic-qcom_reset-v3-1-5958facd5db2@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-08-03clk: qcom: fix some Kconfig corner casesArnd Bergmann1-0/+4
The SM_GCC_8550 symbol and others can only be built for ARM64 or when compile testing, but it gets selected by other drivers that can also be built for 32-bit ARCH_QCOM when not compile testing, which results in a Kconfig warning: WARNING: unmet direct dependencies detected for SM_GCC_8550 Depends on [n]: COMMON_CLK [=y] && COMMON_CLK_QCOM [=m] && (ARM64 || COMPILE_TEST [=n]) Selected by [m]: - SM_GPUCC_8550 [=m] && COMMON_CLK [=y] && COMMON_CLK_QCOM [=m] - SM_VIDEOCC_8550 [=m] && COMMON_CLK [=y] && COMMON_CLK_QCOM [=m] Add further 'depends on' statements to tighten this in a way that avoids the missing dependencies. Fixes: fd0b5b106fcab ("clk: qcom: Introduce SM8350 VIDEOCC") Fixes: 441fe711be384 ("clk: qcom: videocc-sm8450: Add video clock controller driver for SM8450") Fixes: f53153a37969c ("clk: qcom: videocc-sm8550: Add video clock controller driver for SM8550") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20230801105718.3658612-1-arnd@kernel.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-08-03clk: qcom: gcc-sm8250: Fix gcc_sdcc2_apps_clk_srcPatrick Whewell1-0/+1
GPLL9 is not on by default, which causes a "gcc_sdcc2_apps_clk_src: rcg didn't update its configuration" error when booting. Set .flags = CLK_OPS_PARENT_ENABLE to fix the error. Fixes: 3e5770921a88 ("clk: qcom: gcc: Add global clock controller driver for SM8250") Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by: Patrick Whewell <patrick.whewell@sightlineapplications.com> Reviewed-by: Vinod Koul <vkoul@kernel.org> Link: https://lore.kernel.org/r/20230802210359.408-1-patrick.whewell@sightlineapplications.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-08-03clk: qcom: lcc-msm8960: change pxo_parent_data to staticYang Yingliang1-1/+1
The pxo_parent_data inroduced in commit bac4675a4d1b ("clk: qcom: drop lcc-mdm9615 in favour of lcc-msm8960") is only used in lcc-msm8960.c now, change it to static. Signed-off-by: Yang Yingliang <yangyingliang@huawei.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20230803082125.521849-1-yangyingliang@huawei.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-08-01clk: qcom: gcc-sc7180: Fix up gcc_sdcc2_apps_clk_srcDavid Wronek1-0/+1
Set .flags = CLK_OPS_PARENT_ENABLE to fix "gcc_sdcc2_apps_clk_src: rcg didn't update its configuration" error. Fixes: 17269568f726 ("clk: qcom: Add Global Clock controller (GCC) driver for SC7180") Signed-off-by: David Wronek <davidwronek@gmail.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20230723190725.1619193-2-davidwronek@gmail.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-08-01clk: qcom: cbf-msm8996: Add support for MSM8996 ProYassine Oudjana1-2/+8
The CBF PLL on MSM8996 Pro has a /4 post divisor instead of /2. Handle the difference accordingly. Signed-off-by: Yassine Oudjana <y.oudjana@protonmail.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20230527093934.101335-4-y.oudjana@protonmail.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-08-01clk: qcom: gcc-mdm9615: drop the cxo clockDmitry Baryshkov1-17/+0
The gcc and lcc devices have been switched to the DT-defined cxo_board clock. Now we can drop the manually defined cxo clock. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20230512211727.3445575-9-dmitry.baryshkov@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-08-01clk: qcom: gcc-mdm9615: use parent_hws/_data instead of parent_namesDmitry Baryshkov1-82/+124
Convert the clock driver to specify parent data rather than parent names, to actually bind using 'clock-names' specified in the DTS rather than global clock names. Use parent_hws where possible to refer parent clocks directly, skipping the lookup. Note, the system names for xo clocks were changed from "cxo" to "cxo_board" to follow the example of other platforms. This switches the clocks to use DT-provided "cxo_board" clock instead of manually registered "cxo" clock and allows us to drop the cxo clock. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20230512211727.3445575-8-dmitry.baryshkov@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-08-01clk: qcom: gcc-mdm9615: use proper parent for pll0_vote clockDmitry Baryshkov1-1/+1
The pll0_vote clock definitely should have pll0 as a parent (instead of pll8). Fixes: 7792a8d6713c ("clk: mdm9615: Add support for MDM9615 Clock Controllers") Cc: stable@kernel.org Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20230512211727.3445575-7-dmitry.baryshkov@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-08-01clk: qcom: drop lcc-mdm9615 in favour of lcc-msm8960Dmitry Baryshkov4-589/+18
The two LCC drivers, msm8960 and mdm9615 are almost the same. The only difference is the platform clock: msm8960/apq8064 use pxo, while mdm9615 uses cxo. Drop the lcc-mdm9615 in favour of using lcc-msm8960 instead. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20230512211727.3445575-6-dmitry.baryshkov@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-08-01clk: qcom: gcc-mdm9615: use ARRAY_SIZE instead of specifying num_parentsDmitry Baryshkov1-21/+21
Use ARRAY_SIZE() instead of manually specifying num_parents. This makes adding/removing entries to/from parent_data easy and errorproof. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20230512211727.3445575-5-dmitry.baryshkov@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-08-01dt-bindings: clock: drop qcom,lcc-mdm9615 header fileDmitry Baryshkov1-1/+1
The header file for qcom,lcc-mdm9615 and qcom,lcc-msm8960 is the same (as well as the drivers). Drop the qcom,lcc-mdm9615.h in favour of qcom,lcc-msm8960.h Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20230512211727.3445575-3-dmitry.baryshkov@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-08-01clk: qcom: videocc-sm8350: Add SC8280XP supportKonrad Dybcio1-1/+41
SC8280XP, being a partial derivative of SM8350, shares almost the exact same videocc block. Extend the 8350 driver to support the bigger brother. The only notable changes are higher possible frequencies on some clocks and some switcheroo within the XO/sleep registers (probably due to some different board crystal configuration). Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20230703-topic-8280_videocc-v2-2-c88269806269@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-07-28clk: qcom: dispcc-sc8280xp: Use ret registers on GDSCsKonrad Dybcio1-4/+4
The DISP_CC GDSCs have not been instructed to use the ret registers. Fix that. Fixes: 4a66e76fdb6d ("clk: qcom: Add SC8280XP display clock controller") Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20230725-topic-8280_dispcc_gdsc-v1-1-236590060531@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-07-19clk: Explicitly include correct DT includesRob Herring70-72/+59
The DT of_device.h and of_platform.h date back to the separate of_platform_bus_type before it as merged into the regular platform bus. As part of that merge prepping Arm DT support 13 years ago, they "temporarily" include each other. They also include platform_device.h and of.h. As a result, there's a pretty much random mix of those include files used throughout the tree. In order to detangle these headers and replace the implicit includes with struct declarations, users need to explicitly include the correct includes. Acked-by: Dinh Nguyen <dinguyen@kernel.org> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> # samsung Acked-by: Heiko Stuebner <heiko@sntech.de> #rockchip Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Luca Ceresoli <luca.ceresoli@bootlin.com> # versaclock5 Signed-off-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20230718143156.1066339-1-robh@kernel.org Acked-by: Abel Vesa <abel.vesa@linaro.org> #imx Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-07-18clk: qcom: turingcc-qcs404: fix missing resume during probeJohan Hovold1-1/+12
Drivers that enable runtime PM must make sure that the controller is runtime resumed before accessing its registers to prevent the power domain from being disabled. Fixes: 892df0191b29 ("clk: qcom: Add QCS404 TuringCC") Cc: stable@vger.kernel.org # 5.2 Cc: Bjorn Andersson <andersson@kernel.org> Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Link: https://lore.kernel.org/r/20230718132902.21430-9-johan+linaro@kernel.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-07-18clk: qcom: mss-sc7180: fix missing resume during probeJohan Hovold1-1/+12
Drivers that enable runtime PM must make sure that the controller is runtime resumed before accessing its registers to prevent the power domain from being disabled. Fixes: 8def929c4097 ("clk: qcom: Add modem clock controller driver for SC7180") Cc: stable@vger.kernel.org # 5.7 Cc: Taniya Das <quic_tdas@quicinc.com> Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Link: https://lore.kernel.org/r/20230718132902.21430-8-johan+linaro@kernel.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-07-18clk: qcom: q6sstop-qcs404: fix missing resume during probeJohan Hovold1-2/+13
Drivers that enable runtime PM must make sure that the controller is runtime resumed before accessing its registers to prevent the power domain from being disabled. Fixes: 6cdef2738db0 ("clk: qcom: Add Q6SSTOP clock controller for QCS404") Cc: stable@vger.kernel.org # 5.5 Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Link: https://lore.kernel.org/r/20230718132902.21430-7-johan+linaro@kernel.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-07-18clk: qcom: lpasscc-sc7280: fix missing resume during probeJohan Hovold1-4/+12
Drivers that enable runtime PM must make sure that the controller is runtime resumed before accessing its registers to prevent the power domain from being disabled. Fixes: 4ab43d171181 ("clk: qcom: Add lpass clock controller driver for SC7280") Cc: stable@vger.kernel.org # 5.16 Cc: Taniya Das <quic_tdas@quicinc.com> Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Link: https://lore.kernel.org/r/20230718132902.21430-6-johan+linaro@kernel.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-07-18clk: qcom: gcc-sc8280xp: fix runtime PM imbalance on probe errorsJohan Hovold1-3/+11
Make sure to decrement the runtime PM usage count before returning in case RCG dynamic frequency switch initialisation fails. Fixes: 2a541abd9837 ("clk: qcom: gcc-sc8280xp: Add runtime PM") Cc: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Link: https://lore.kernel.org/r/20230718132902.21430-5-johan+linaro@kernel.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-07-18clk: qcom: dispcc-sm8550: fix runtime PM imbalance on probe errorsJohan Hovold1-2/+11
Make sure to decrement the runtime PM usage count before returning in case regmap initialisation fails. Fixes: 90114ca11476 ("clk: qcom: add SM8550 DISPCC driver") Cc: stable@vger.kernel.org # 6.3 Cc: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Link: https://lore.kernel.org/r/20230718132902.21430-4-johan+linaro@kernel.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-07-18clk: qcom: dispcc-sm8450: fix runtime PM imbalance on probe errorsJohan Hovold1-2/+11
Make sure to decrement the runtime PM usage count before returning in case regmap initialisation fails. Fixes: 16fb89f92ec4 ("clk: qcom: Add support for Display Clock Controller on SM8450") Cc: stable@vger.kernel.org # 6.1 Cc: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Link: https://lore.kernel.org/r/20230718132902.21430-3-johan+linaro@kernel.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-07-18clk: qcom: camcc-sc7180: fix async resume during probeJohan Hovold1-1/+1
To make sure that the controller is runtime resumed and its power domain is enabled before accessing its registers during probe, the synchronous runtime PM interface must be used. Fixes: 8d4025943e13 ("clk: qcom: camcc-sc7180: Use runtime PM ops instead of clk ones") Cc: stable@vger.kernel.org # 5.11 Cc: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Link: https://lore.kernel.org/r/20230718132902.21430-2-johan+linaro@kernel.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-07-15Merge branch '20230526-topic-smd_icc-v7-0-09c78c175546@linaro.org' into ↵Bjorn Andersson1-177/+137
clk-for-6.6 This series reshuffles things around, moving the management of SMD RPM bus clocks to the interconnect framework where they belong. This helps us solve a couple of issues: 1. We can work towards unused clk cleanup of RPMCC without worrying about it killing some NoC bus, resulting in the SoC dying. Deasserting actually unused RPM clocks (among other things) will let us achieve "true SoC-wide power collapse states", also known as VDD_LOW and VDD_MIN. 2. We no longer have to keep tons of quirky bus clock ifs in the icc driver. You either have a RPM clock and call "rpm set rate" or you have a single non-RPM clock (like AHB_CLK_SRC) or you don't have any. 3. There's less overhead - instead of going through layers and layers of the CCF, ratesetting comes down to calling max() and sending a single RPM message. ICC is very very dynamic so that's a big plus. The clocks still need to be vaguely described in the clk-smd-rpm driver, as it gives them an initial kickoff, before actually telling RPM to enable DVFS scaling. After RPM receives that command, all clocks that have not been assigned a rate are considered unused and are shut down in hardware, leading to the same issue as described in point 1. We can consider marking them __initconst in the future, but this series is very fat even without that.. Apart from that, it squashes a couple of bugs that really need fixing.. The series is merged through a topic branch to manage the dependencies between interconnect, Qualcomm clocks and Qualcomm SoC.
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