Age | Commit message (Expand) | Author | Files | Lines |
---|---|---|---|---|
2023-03-10 | clk: renesas: r8a77970: Add Z2 clock | Geert Uytterhoeven | 1 | -0/+1 |
2020-06-22 | clk: renesas: rcar-gen3: Mark RWDT clocks as critical | Ulrich Hecht | 1 | -1/+1 |
2018-12-04 | clk: renesas: r8a77970: Add CPEX clock | Geert Uytterhoeven | 1 | -0/+1 |
2018-11-05 | clk: renesas: r8a77970: Add RPC clocks | Sergei Shtylyov | 1 | -0/+4 |
2018-10-19 | Merge branch 'clk-renesas' into clk-next | Stephen Boyd | 1 | -2/+74 |
2018-09-29 | clk: renesas: Convert to SPDX identifiers | Kuninori Morimoto | 1 | -4/+1 |
2018-09-25 | clk: renesas: r8a77970: Add TPU clock | Sergei Shtylyov | 1 | -0/+1 |
2018-09-11 | clk: renesas: r8a77970: Add TMU clocks | Sergei Shtylyov | 1 | -0/+5 |
2018-09-11 | clk: renesas: r8a77970: Add CMT clocks | Sergei Shtylyov | 1 | -0/+4 |
2018-09-03 | clk: renesas: r8a77970: Add SD0H/SD0 clocks for SDHI | Sergei Shtylyov | 1 | -2/+64 |
2017-12-08 | clk: renesas: r8a77970: Add LVDS clock | Sergei Shtylyov | 1 | -0/+1 |
2017-09-19 | clk: renesas: cpg-mssr: Add R8A77970 support | Sergei Shtylyov | 1 | -0/+199 |