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starfive-tech/linux.git
JH7100_VisionFive_OH_dev
JH7110_VisionFive2_510_devel
JH7110_VisionFive2_6.1.y_devel
JH7110_VisionFive2_6.6.y_devel
JH7110_VisionFive2_devel
JH7110_VisionFive2_upstream
beaglev-5.13.y
beaglev_fedora_devel
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esmil_starlight
fedora-vic-7100_5.10.6
master
openwrt-6.1.y
rt-ethercat-release
rt-linux-release
rtthread_AMP
starfive-5.13
starfive-5.15-dubhe
starfive-6.1-dubhe
starfive-6.1.65-dubhe
starfive-6.6.10-dubhe
starfive-6.6.31-dubhe
starlight-5.14.y
visionfive
visionfive-5.13.y-devel
visionfive-5.15.y
visionfive-5.15.y-devel
visionfive-5.15.y_fedora_devel
visionfive-5.16.y
visionfive-5.17.y
visionfive-5.18.y
visionfive-5.19.y
visionfive-6.4.y
visionfive_fedora_devel
StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)
Andrey V.Kosteltsev
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path:
root
/
drivers
/
clk
/
renesas
/
r8a77990-cpg-mssr.c
Age
Commit message (
Expand
)
Author
Files
Lines
2023-08-15
clk: renesas: rcar-gen3: Add ADG clocks
Kuninori Morimoto
1
-0
/
+1
2022-04-13
clk: renesas: Move RPC core clocks
Geert Uytterhoeven
1
-4
/
+2
2022-04-11
clk: renesas: r8a77990: Add RPC clocks
Geert Uytterhoeven
1
-0
/
+9
2022-01-24
clk: renesas: r8a7799[05]: Add MLP clocks
Nikita Yushchenko
1
-0
/
+1
2021-11-19
clk: renesas: rcar-gen3: Add SDnH clock
Wolfram Sang
1
-3
/
+6
2021-03-08
clk: renesas: r8a77990: Add DAB clock
Fabrizio Castro
1
-0
/
+1
2020-12-28
clk: renesas: r8a77990: Add TMU clocks
Niklas Söderlund
1
-0
/
+5
2020-06-22
clk: renesas: rcar-gen3: Mark RWDT clocks as critical
Ulrich Hecht
1
-0
/
+1
2020-02-10
clk: renesas: rcar-gen3: Add CCREE clocks
Geert Uytterhoeven
1
-0
/
+2
2019-06-18
clk: renesas: r8a77990: Add CMM clocks
Jacopo Mondi
1
-0
/
+2
2019-04-02
clk: renesas: rcar-gen3: Rename DRIF clocks
Takeshi Kihara
1
-9
/
+9
2019-04-02
clk: renesas: rcar-gen3: Correct parent clock of Audio-DMAC
Takeshi Kihara
1
-1
/
+1
2019-04-02
clk: renesas: rcar-gen3: Correct parent clock of HS-USB
Kazuya Mizuguchi
1
-1
/
+1
2019-04-02
clk: renesas: rcar-gen3: Correct parent clock of EHCI/OHCI
Kazuya Mizuguchi
1
-1
/
+1
2019-04-02
clk: renesas: r8a77990: Add Z2 clock
Takeshi Kihara
1
-0
/
+1
2018-12-04
clk: renesas: r8a77990: Correct parent clock of DU
Takeshi Kihara
1
-2
/
+2
2018-09-25
clk: renesas: r8a77990: Fix incorrect PLL0 divider in comment
Geert Uytterhoeven
1
-2
/
+2
2018-08-31
clk: renesas: r8a77990: Add missing I2C7 clock
Geert Uytterhoeven
1
-0
/
+1
2018-08-27
clk: renesas: r8a77990: Correct RCLK handling
Geert Uytterhoeven
1
-2
/
+10
2018-05-09
clk: renesas: cpg-mssr: Add support for R-Car E3
Yoshihiro Shimoda
1
-0
/
+289