index
:
starfive-tech/linux.git
JH7100_VisionFive_OH_dev
JH7110_VisionFive2_510_devel
JH7110_VisionFive2_6.1.y_devel
JH7110_VisionFive2_6.6.y_devel
JH7110_VisionFive2_devel
JH7110_VisionFive2_upstream
beaglev-5.13.y
beaglev_fedora_devel
buildroot-upstream
esmil_starlight
fedora-vic-7100_5.10.6
master
openwrt-6.1.y
rt-ethercat-release
rt-linux-release
rtthread_AMP
starfive-5.13
starfive-5.15-dubhe
starfive-6.1-dubhe
starfive-6.1.65-dubhe
starfive-6.6.10-dubhe
starfive-6.6.31-dubhe
starlight-5.14.y
visionfive
visionfive-5.13.y-devel
visionfive-5.15.y
visionfive-5.15.y-devel
visionfive-5.15.y_fedora_devel
visionfive-5.16.y
visionfive-5.17.y
visionfive-5.18.y
visionfive-5.19.y
visionfive-6.4.y
visionfive_fedora_devel
StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)
Andrey V.Kosteltsev
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
drivers
/
clk
/
renesas
/
rcar-gen3-cpg.h
Age
Commit message (
Expand
)
Author
Files
Lines
2023-07-10
clk: renesas: rcar-gen3: Add support for ZG clock
Adam Ford
1
-0
/
+1
2022-04-11
clk: renesas: r8a77995: Add RPC clocks
Geert Uytterhoeven
1
-1
/
+4
2021-11-19
clk: renesas: rcar-gen3: Add dummy SDnH clock
Wolfram Sang
1
-0
/
+4
2020-12-10
clk: renesas: r8a774c0: Add RPC clocks
Lad Prabhakar
1
-0
/
+5
2019-05-07
Merge branches 'clk-stm32f4', 'clk-tegra', 'clk-at91', 'clk-sifive-fu540' and...
Stephen Boyd
1
-2
/
+2
2019-05-01
clk: renesas: Use the correct style for SPDX License Identifier
Nishad Kamdar
1
-2
/
+2
2019-04-02
clk: renesas: rcar-gen3: Remove CLK_TYPE_GEN3_Z2
Simon Horman
1
-1
/
+0
2019-04-02
clk: renesas: rcar-gen3: Parameterise Z and Z2 clock offset
Simon Horman
1
-2
/
+2
2019-04-02
clk: renesas: rcar-gen3: Parameterise Z and Z2 clock fixed divisor
Takeshi Kihara
1
-0
/
+4
2019-02-05
clk: renesas: rcar-gen3: Add RPC clocks
Sergei Shtylyov
1
-0
/
+4
2018-10-19
Merge branch 'clk-renesas' into clk-next
Stephen Boyd
1
-5
/
+23
2018-09-29
clk: renesas: Convert to SPDX identifiers
Kuninori Morimoto
1
-5
/
+2
2018-09-03
clk: renesas: r8a77970: Add SD0H/SD0 clocks for SDHI
Sergei Shtylyov
1
-0
/
+3
2018-08-27
clk: renesas: rcar-gen3: Add support for mode pin clock selection
Geert Uytterhoeven
1
-4
/
+9
2018-08-27
clk: renesas: rcar-gen3: Add support for RCKSEL clock selection
Geert Uytterhoeven
1
-1
/
+6
2018-08-27
clk: renesas: rcar-gen3: Add support for OSC EXTAL predivider
Geert Uytterhoeven
1
-0
/
+4
2018-02-12
clk: renesas: rcar-gen3: Add Z2 clock divider support
Takeshi Kihara
1
-0
/
+1
2018-02-12
clk: renesas: rcar-gen3: Add Z clock divider support
Takeshi Kihara
1
-0
/
+1
2017-10-20
clk: renesas: cpg-mssr: Add support to restore core clocks during resume
Geert Uytterhoeven
1
-1
/
+2
2017-08-16
clk: renesas: rcar-gen3: Add support for SCCG/Clean peripheral clocks
Geert Uytterhoeven
1
-0
/
+7
2017-08-16
clk: renesas: rcar-gen3: Add divider support for PLL1 and PLL3
Geert Uytterhoeven
1
-3
/
+5
2017-03-21
clk: renesas: rcar-gen3-cpg: Pass mode pins to rcar_gen3_cpg_init()
Geert Uytterhoeven
1
-1
/
+1
2016-11-02
clk: renesas: rcar-gen3-cpg: Remove obsolete rcar_gen3_read_mode_pins()
Geert Uytterhoeven
1
-1
/
+0
2016-06-06
clk: renesas: cpg-mssr: Extract common R-Car Gen3 support code
Geert Uytterhoeven
1
-0
/
+43