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starfive-tech/linux.git
JH7100_VisionFive_OH_dev
JH7110_VisionFive2_510_devel
JH7110_VisionFive2_6.1.y_devel
JH7110_VisionFive2_6.6.y_devel
JH7110_VisionFive2_devel
JH7110_VisionFive2_upstream
beaglev-5.13.y
beaglev_fedora_devel
buildroot-upstream
esmil_starlight
fedora-vic-7100_5.10.6
master
openwrt-6.1.y
rt-ethercat-release
rt-linux-release
rtthread_AMP
starfive-5.13
starfive-5.15-dubhe
starfive-6.1-dubhe
starfive-6.1.65-dubhe
starfive-6.6.10-dubhe
starfive-6.6.31-dubhe
starlight-5.14.y
visionfive
visionfive-5.13.y-devel
visionfive-5.15.y
visionfive-5.15.y-devel
visionfive-5.15.y_fedora_devel
visionfive-5.16.y
visionfive-5.17.y
visionfive-5.18.y
visionfive-5.19.y
visionfive-6.4.y
visionfive_fedora_devel
StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)
Andrey V.Kosteltsev
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path:
root
/
drivers
/
clk
/
renesas
/
rzg2l-cpg.h
Age
Commit message (
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Author
Files
Lines
2024-04-25
clk: renesas: rzg2l: Extend power domain support
Claudiu Beznea
1
-0
/
+67
2023-10-10
clk: renesas: Add minimal boot support for RZ/G3S SoC
Claudiu Beznea
1
-0
/
+1
2023-10-10
clk: renesas: rzg2l: Add divider clock for RZ/G3S
Claudiu Beznea
1
-0
/
+11
2023-10-10
clk: renesas: rzg2l: Refactor SD mux driver
Claudiu Beznea
1
-5
/
+11
2023-10-05
clk: renesas: rzg2l: Remove CPG_SDHI_DSEL from generic header
Claudiu Beznea
1
-4
/
+0
2023-10-05
clk: renesas: rzg2l: Add support for RZ/G3S PLL
Claudiu Beznea
1
-0
/
+3
2023-10-05
clk: renesas: rzg2l: Lock around writes to mux register
Claudiu Beznea
1
-1
/
+1
2023-09-18
clk: renesas: rzg2l: Use u32 for flag and mux_flags
Claudiu Beznea
1
-2
/
+2
2023-05-23
clk: renesas: rzg2l: Fix CPG_SIPLL5_CLK1 register write
Biju Das
1
-3
/
+0
2022-10-28
clk: renesas: rzg2l: Don't assume all CPG_MOD clocks support PM
Lad Prabhakar
1
-0
/
+4
2022-05-06
clk: renesas: Add RZ/V2M support using the rzg2l driver
Phil Edworthy
1
-0
/
+1
2022-05-05
clk: renesas: rzg2l: Add support for RZ/V2M reset monitor reg
Phil Edworthy
1
-2
/
+8
2022-05-05
clk: renesas: rzg2l: Make use of CLK_MON registers optional
Phil Edworthy
1
-0
/
+3
2022-05-05
clk: renesas: rzg2l: Set HIWORD mask for all mux and dividers
Phil Edworthy
1
-4
/
+5
2022-05-05
clk: renesas: rzg2l: Add read only versions of the clk macros
Phil Edworthy
1
-0
/
+9
2022-05-05
clk: renesas: rzg2l: Move the DEF_MUX array size calc into the macro
Phil Edworthy
1
-7
/
+9
2022-05-05
clk: renesas: rzg2l: Add DSI divider clk support
Biju Das
1
-0
/
+11
2022-05-05
clk: renesas: rzg2l: Add PLL5_4 clk mux support
Biju Das
1
-0
/
+10
2022-05-05
clk: renesas: rzg2l: Add FOUTPOSTDIV clk support
Biju Das
1
-0
/
+23
2022-04-13
clk: renesas: Add support for RZ/G2UL SoC
Biju Das
1
-0
/
+1
2022-02-10
clk: renesas: rzg2l-cpg: Add support for RZ/V2L SoC
Biju Das
1
-0
/
+1
2021-12-08
clk: renesas: r9a07g044: Add mux and divider for G clock
Biju Das
1
-0
/
+4
2021-11-19
clk: renesas: rzg2l: Add CPG_PL1_DDIV macro
Biju Das
1
-0
/
+2
2021-11-15
clk: renesas: rzg2l: Add missing kerneldoc for resets
Geert Uytterhoeven
1
-0
/
+3
2021-10-08
clk: renesas: r9a07g044: Add SDHI clock and reset entries
Biju Das
1
-0
/
+4
2021-10-08
clk: renesas: rzg2l: Add SDHI clk mux support
Biju Das
1
-0
/
+12
2021-10-08
clk: renesas: r9a07g044: Add clock and reset entries for SPI Multi I/O Bus Co...
Lad Prabhakar
1
-0
/
+3
2021-09-24
clk: renesas: rzg2l: Add support to handle coupled clocks
Biju Das
1
-1
/
+10
2021-09-24
clk: renesas: r9a07g044: Add ethernet clock sources
Biju Das
1
-0
/
+3
2021-09-24
clk: renesas: rzg2l: Add support to handle MUX clocks
Biju Das
1
-0
/
+12
2021-07-19
clk: renesas: Rename renesas-rzg2l-cpg.[ch] to rzg2l-cpg.[ch]
Geert Uytterhoeven
1
-0
/
+155