index
:
starfive-tech/linux.git
JH7100_VisionFive_OH_dev
JH7110_VisionFive2_510_devel
JH7110_VisionFive2_6.1.y_devel
JH7110_VisionFive2_6.6.y_devel
JH7110_VisionFive2_devel
JH7110_VisionFive2_upstream
beaglev-5.13.y
beaglev_fedora_devel
buildroot-upstream
esmil_starlight
fedora-vic-7100_5.10.6
master
openwrt-6.1.y
rt-ethercat-release
rt-linux-release
rtthread_AMP
starfive-5.13
starfive-5.15-dubhe
starfive-6.1-dubhe
starfive-6.1.65-dubhe
starfive-6.6.10-dubhe
starfive-6.6.31-dubhe
starlight-5.14.y
visionfive
visionfive-5.13.y-devel
visionfive-5.15.y
visionfive-5.15.y-devel
visionfive-5.15.y_fedora_devel
visionfive-5.16.y
visionfive-5.17.y
visionfive-5.18.y
visionfive-5.19.y
visionfive-6.4.y
visionfive_fedora_devel
StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)
Andrey V.Kosteltsev
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path:
root
/
drivers
/
clk
/
renesas
Age
Commit message (
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Author
Files
Lines
2023-10-05
clk: renesas: rcar-gen3: Extend SDnH divider table
Dirk Behme
1
-1
/
+14
2023-09-26
clk: renesas: r8a7795: Constify r8a7795_*_clks
Marek Vasut
1
-2
/
+2
2023-09-18
clk: renesas: r9a06g032: Name anonymous structs
Ralph Siemsen
1
-30
/
+33
2023-09-18
clk: renesas: r9a06g032: Fix kerneldoc warning
Ralph Siemsen
1
-0
/
+1
2023-09-18
clk: renesas: rzg2l: Use u32 for flag and mux_flags
Claudiu Beznea
1
-2
/
+2
2023-09-18
clk: renesas: rzg2l: Use FIELD_GET() for PLL register fields
Claudiu Beznea
1
-5
/
+5
2023-09-18
clk: renesas: rzg2l: Simplify the logic in rzg2l_mod_clock_endisable()
Claudiu Beznea
1
-3
/
+2
2023-09-18
clk: renesas: rzg2l: Use core->name for clock name
Claudiu Beznea
1
-1
/
+1
2023-09-11
clk: renesas: r9a06g032: Use for_each_compatible_node()
Yang Yingliang
1
-3
/
+2
2023-08-31
Merge branches 'clk-bindings', 'clk-starfive', 'clk-rm', 'clk-renesas' and 'c...
Stephen Boyd
17
-19
/
+73
2023-08-15
clk: renesas: rcar-gen3: Add ADG clocks
Kuninori Morimoto
9
-1
/
+9
2023-07-27
clk: renesas: r8a77965: Add 3DGE and ZG support
Geert Uytterhoeven
1
-0
/
+2
2023-07-27
clk: renesas: r8a7796: Add 3DGE and ZG support
Geert Uytterhoeven
1
-0
/
+2
2023-07-27
clk: renesas: r8a7795: Add 3DGE and ZG support
Geert Uytterhoeven
1
-0
/
+2
2023-07-27
clk: renesas: emev2: Remove obsolete clkdev registration
Geert Uytterhoeven
1
-3
/
+0
2023-07-25
clk: renesas: r9a07g043: Add MTU3a clock and reset entry
Biju Das
1
-0
/
+3
2023-07-19
clk: Explicitly include correct DT includes
Rob Herring
3
-4
/
+1
2023-07-11
clk: renesas: rzg2l: Simplify .determine_rate()
Christophe JAILLET
1
-7
/
+1
2023-07-10
clk: renesas: r9a09g011: Add CSI related clocks
Fabrizio Castro
1
-0
/
+15
2023-07-10
clk: renesas: r8a774b1: Add 3DGE and ZG support
Adam Ford
1
-0
/
+2
2023-07-10
clk: renesas: r8a774e1: Add 3DGE and ZG support
Adam Ford
1
-0
/
+2
2023-07-10
clk: renesas: r8a774a1: Add 3DGE and ZG support
Adam Ford
1
-0
/
+2
2023-07-10
clk: renesas: rcar-gen3: Add support for ZG clock
Adam Ford
2
-4
/
+32
2023-06-26
Merge branches 'clk-renesas', 'clk-determine-rate', 'clk-allwinner', 'clk-sam...
Stephen Boyd
6
-49
/
+27
2023-06-09
clk: renesas: r9a06g032: Add a determine_rate hook
Maxime Ripard
1
-0
/
+1
2023-06-05
clk: renesas: rzg2l: Convert to readl_poll_timeout_atomic()
Geert Uytterhoeven
1
-11
/
+5
2023-06-05
clk: renesas: mstp: Convert to readl_poll_timeout_atomic()
Geert Uytterhoeven
1
-11
/
+7
2023-06-05
clk: renesas: cpg-mssr: Convert to readl_poll_timeout_atomic()
Geert Uytterhoeven
1
-20
/
+11
2023-05-23
clk: renesas: rzg2l: Fix CPG_SIPLL5_CLK1 register write
Biju Das
2
-7
/
+2
2023-05-08
clk: renesas: r8a779a0: Add PWM clock
Wolfram Sang
1
-0
/
+1
2023-04-30
Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...
Linus Torvalds
7
-204
/
+591
2023-04-13
clk: renesas: remove MODULE_LICENSE in non-modules
Nick Alcock
2
-2
/
+0
2023-03-30
clk: renesas: r8a77980: Add I2C5 clock
Nikita Yushchenko
1
-0
/
+1
2023-03-16
clk: renesas: Convert to platform remove callback returning void
Uwe Kleine-König
1
-4
/
+2
2023-03-10
clk: renesas: r9a06g032: Improve clock tables
Ralph Siemsen
1
-153
/
+407
2023-03-10
clk: renesas: r9a06g032: Document structs
Ralph Siemsen
1
-1
/
+49
2023-03-10
clk: renesas: r9a06g032: Drop unused fields
Ralph Siemsen
1
-5
/
+10
2023-03-10
clk: renesas: r9a06g032: Improve readability
Ralph Siemsen
1
-41
/
+80
2023-03-10
clk: renesas: r8a77980: Add Z2 clock
Geert Uytterhoeven
1
-0
/
+1
2023-03-10
clk: renesas: r8a77970: Add Z2 clock
Geert Uytterhoeven
1
-0
/
+1
2023-03-06
clk: renesas: r8a77995: Fix VIN parent clock
Geert Uytterhoeven
1
-1
/
+1
2023-03-06
clk: renesas: r8a77980: Add VIN clocks
Niklas Söderlund
1
-0
/
+16
2023-03-06
clk: renesas: r8a779g0: Add VIN clocks
Niklas Söderlund
1
-0
/
+16
2023-03-06
clk: renesas: r8a779g0: Add ISPCS clocks
Niklas Söderlund
1
-0
/
+2
2023-03-06
clk: renesas: r8a779g0: Add CSI-2 clocks
Niklas Söderlund
1
-0
/
+3
2023-03-06
clk: renesas: r8a779g0: Add thermal clock
Geert Uytterhoeven
1
-0
/
+1
2023-03-06
clk: renesas: r8a779g0: Add Audio clocks
Kuninori Morimoto
1
-0
/
+2
2023-03-06
clk: renesas: cpg-mssr: Update MSSR register range for R-Car V4H
Takeshi Kihara
1
-4
/
+4
2023-02-10
clk: renesas: rcar-gen3: Disable R-Car H3 ES1.*
Wolfram Sang
5
-173
/
+13
2023-01-26
clk: renesas: r8a779g0: Add CAN-FD clocks
Geert Uytterhoeven
1
-0
/
+2
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