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starfive-tech/linux.git
JH7100_VisionFive_OH_dev
JH7110_VisionFive2_510_devel
JH7110_VisionFive2_6.1.y_devel
JH7110_VisionFive2_6.6.y_devel
JH7110_VisionFive2_devel
JH7110_VisionFive2_upstream
beaglev-5.13.y
beaglev_fedora_devel
buildroot-upstream
esmil_starlight
fedora-vic-7100_5.10.6
master
openwrt-6.1.y
rt-ethercat-release
rt-linux-release
rtthread_AMP
starfive-5.13
starfive-5.15-dubhe
starfive-6.1-dubhe
starfive-6.1.65-dubhe
starfive-6.6.10-dubhe
starfive-6.6.31-dubhe
starlight-5.14.y
visionfive
visionfive-5.13.y-devel
visionfive-5.15.y
visionfive-5.15.y-devel
visionfive-5.15.y_fedora_devel
visionfive-5.16.y
visionfive-5.17.y
visionfive-5.18.y
visionfive-5.19.y
visionfive-6.4.y
visionfive_fedora_devel
StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)
Andrey V.Kosteltsev
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path:
root
/
drivers
/
clk
/
rockchip
/
clk-rk3568.c
Age
Commit message (
Expand
)
Author
Files
Lines
2024-05-04
clk: rockchip: rk3568: Add PLL rate for 724 MHz
Lucas Stach
1
-0
/
+1
2024-04-10
clk: rockchip: rk3568: Add missing USB480M_PHY mux
David Jander
1
-0
/
+4
2024-01-25
clk: rockchip: rk3568: Add PLL rate for 128MHz
Chris Morgan
1
-0
/
+1
2024-01-13
Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...
Linus Torvalds
1
-0
/
+3
2023-12-05
clk: rockchip: rk3568: Mark pclk_usb as critical
Chris Morgan
1
-0
/
+1
2023-12-05
clk: rockchip: rk3568: Add PLL rate for 126.4MHz
Chris Morgan
1
-0
/
+1
2023-11-16
clk: rockchip: rk3568: Add PLL rate for 292.5MHz
Chris Morgan
1
-0
/
+1
2023-11-16
clk: rockchip: rk3568: Add PLL rate for 115.2MHz
Chris Morgan
1
-0
/
+1
2023-08-31
Merge branches 'clk-versa', 'clk-strdup', 'clk-amlogic', 'clk-allwinner' and ...
Stephen Boyd
1
-1
/
+2
2023-07-19
clk: Explicitly include correct DT includes
Rob Herring
1
-1
/
+1
2023-07-10
clk: rockchip: rk3568: Fix PLL rate setting for 78.75MHz
Alibek Omarov
1
-1
/
+1
2023-07-10
clk: rockchip: rk3568: Add PLL rate for 101MHz
Alibek Omarov
1
-0
/
+1
2022-05-03
clk: rockchip: Mark hclk_vo as critical on rk3568
Sascha Hauer
1
-0
/
+1
2022-02-24
clk/rockchip: Use of_device_get_match_data()
Minghao Chi (CGEL ZTE)
1
-4
/
+2
2022-02-08
clk: rockchip: Add CLK_SET_RATE_PARENT to the HDMI reference clock on rk3568
Sascha Hauer
1
-1
/
+1
2022-02-08
clk: rockchip: drop CLK_SET_RATE_PARENT from dclk_vop* on rk3568
Sascha Hauer
1
-3
/
+3
2022-02-08
clk: rockchip: Add more PLL rates for rk3568
Sascha Hauer
1
-0
/
+6
2021-11-03
clk: rockchip: drop module parts from rk3399 and rk3568 drivers
Heiko Stuebner
1
-4
/
+0
2021-11-03
Revert "clk: rockchip: use module_platform_driver_probe"
Heiko Stuebner
1
-1
/
+1
2021-09-21
clk: rockchip: use module_platform_driver_probe
Miles Chen
1
-1
/
+1
2021-05-24
clk: rockchip: fix rk3568 cpll clk gate bits
Peter Geis
1
-5
/
+5
2021-03-21
clk: rockchip: add clock controller for rk3568
Elaine Zhang
1
-0
/
+1725