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path: root/drivers/clk/socfpga/clk-periph.c
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2021-03-31clk: socfpga: use clk_hw_register for a5/c5Dinh Nguyen1-4/+4
As recommended by Stephen Boyd, convert the cyclone5/arria5 clock driver to use the clk_hw registration method. Suggested-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> Link: https://lore.kernel.org/r/20210302214151.1333447-1-dinguyen@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-05-30treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 157Thomas Gleixner1-11/+1
Based on 3 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation either version 2 of the license or at your option any later version this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation either version 2 of the license or at your option any later version [author] [kishon] [vijay] [abraham] [i] [kishon]@[ti] [com] this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation either version 2 of the license or at your option any later version [author] [graeme] [gregory] [gg]@[slimlogic] [co] [uk] [author] [kishon] [vijay] [abraham] [i] [kishon]@[ti] [com] [based] [on] [twl6030]_[usb] [c] [author] [hema] [hk] [hemahk]@[ti] [com] this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details extracted by the scancode license scanner the SPDX license identifier GPL-2.0-or-later has been chosen to replace the boilerplate/reference in 1105 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Reviewed-by: Richard Fontana <rfontana@redhat.com> Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190527070033.202006027@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2015-08-25clk: socfpga: Add a second parent option for the dbg_base_clkDinh Nguyen1-4/+14
The debug base clock can be bypassed from the main PLL to the OSC1 clock. The bypass register is the staysoc1(0x10) register that is in the clock manager. This patch adds the option to get the correct parent for the debug base clock. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-07-28clk: socfpga: switch to GENMASK()Andy Shevchenko1-1/+1
Convert the code to use GENMASK() helper instead of div_mask() macro. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-07-20clk: socfpga: Remove clk.h and clkdev.h includesStephen Boyd1-2/+1
Clock provider drivers generally shouldn't include clk.h because it's the consumer API. Remove the include here because this is a provider driver. The clkdev.h include isn't used either, remove it and add in slab.h to make sure things keep compiling. Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-05-15clk: socfpga: Silence sparse warningStephen Boyd1-1/+1
drivers/clk/socfpga/clk-periph.c:79:39: warning: Using plain integer as NULL pointer Cc: Dinh Nguyen <dinguyen@altera.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2014-05-12clk: socfpga: add divider registers to the main pll outputsDinh Nguyen1-3/+19
The C0(mpu_clk), C1(main_clk), and C2(dbg_base_clk) outputs from the main PLL go through a pre-divider before coming into the system. These registers were hidden for the CycloneV platform, but are now used for the ArriaV platform. This patch updates the clock driver to read the div-reg property for the socfpga-periph-clk clocks. Also moves the div_mask define to clk.h for re-use. Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
2014-02-19clk: socfpga: split clk codeSteffen Trumtrar1-0/+94
Move the different kinds of clocks into their own files. The reason is to aid readability of the code. This also goes along with the other SoC-specific clock drivers. The split introduces new structs for the three types of clocks and uses them. Other changes are not done to the code. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Dinh Nguyen <dinguyen@altera.com>