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:
starfive-tech/linux.git
JH7100_VisionFive_OH_dev
JH7110_VisionFive2_510_devel
JH7110_VisionFive2_6.1.y_devel
JH7110_VisionFive2_6.6.y_devel
JH7110_VisionFive2_devel
JH7110_VisionFive2_upstream
beaglev-5.13.y
beaglev_fedora_devel
buildroot-upstream
esmil_starlight
fedora-vic-7100_5.10.6
master
openwrt-6.1.y
rt-ethercat-release
rt-linux-release
rtthread_AMP
starfive-5.13
starfive-5.15-dubhe
starfive-6.1-dubhe
starfive-6.1.65-dubhe
starfive-6.6.10-dubhe
starfive-6.6.31-dubhe
starlight-5.14.y
visionfive
visionfive-5.13.y-devel
visionfive-5.15.y
visionfive-5.15.y-devel
visionfive-5.15.y_fedora_devel
visionfive-5.16.y
visionfive-5.17.y
visionfive-5.18.y
visionfive-5.19.y
visionfive-6.4.y
visionfive_fedora_devel
StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)
Andrey V.Kosteltsev
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path:
root
/
drivers
/
clk
/
sunxi-ng
/
ccu-sun8i-h3.c
Age
Commit message (
Expand
)
Author
Files
Lines
2024-04-16
clk: sunxi-ng: fix module autoloading
Krzysztof Kozlowski
1
-0
/
+1
2023-07-19
clk: Explicitly include correct DT includes
Rob Herring
1
-1
/
+1
2023-01-08
clk: sunxi-ng: h3/h5: Model H3 CLK_DRAM as a fixed clock
Samuel Holland
1
-5
/
+10
2022-06-07
clk: sunxi-ng: Deduplicate ccu_clks arrays
Samuel Holland
1
-110
/
+3
2021-11-23
clk: sunxi-ng: Convert early providers to platform drivers
Samuel Holland
1
-21
/
+41
2021-09-13
clk: sunxi-ng: Unregister clocks/resets when unbinding
Samuel Holland
1
-1
/
+1
2020-12-20
clk: sunxi-ng: Make sure divider tables have sentinel
Jernej Skrabec
1
-0
/
+1
2019-07-17
Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...
Linus Torvalds
1
-10
/
+19
2019-06-18
clk: sunxi-ng: h3: Use local parent references for CLK_FIXED_FACTOR
Chen-Yu Tsai
1
-10
/
+19
2019-06-05
treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 282
Thomas Gleixner
1
-9
/
+1
2019-05-15
clk: Remove io.h from clk-provider.h
Stephen Boyd
1
-0
/
+1
2018-12-04
clk: sunxi-ng: h3: Allow parent change for ve clock
Jernej Skrabec
1
-1
/
+1
2018-12-03
clk: sunxi-ng: h3/h5: Fix CSI_MCLK parent
Chen-Yu Tsai
1
-1
/
+1
2018-08-27
clk: sunxi-ng: h3/h5: Add max. rate constraint to pll-video
Jernej Skrabec
1
-12
/
+13
2018-03-02
clk: sunxi-ng: h3: h5: Allow some clocks to set parent rate
Jernej Skrabec
1
-3
/
+6
2018-03-02
clk: sunxi-ng: h3: h5: Add minimal rate for video PLL
Jernej Skrabec
1
-11
/
+12
2017-10-13
clk: sunxi-ng: sun8i: h3: Use sigma-delta modulation for audio PLL
Chen-Yu Tsai
1
-13
/
+25
2017-09-17
clk: sunxi-ng: add CLK_SET_RATE_PARENT flag to H3 GPU clock
Icenowy Zheng
1
-1
/
+1
2017-09-17
clk: sunxi-ng: add CLK_SET_RATE_UNGATE to all H3 PLLs
Icenowy Zheng
1
-9
/
+9
2017-08-24
Merge tag 'sunxi-clk-for-4.14-2' of https://git.kernel.org/pub/scm/linux/kern...
Stephen Boyd
1
-1
/
+12
2017-08-04
clk: sunxi-ng: allow set parent clock (PLL_CPUX) for CPUX clock on H3
Icenowy Zheng
1
-1
/
+1
2017-08-04
clk: sunxi-ng: h3: gate then ungate PLL CPU clk after rate change
Chen-Yu Tsai
1
-0
/
+11
2017-07-22
clk: Convert to using %pOF instead of full_name
Rob Herring
1
-2
/
+1
2017-06-07
clk: sunxi-ng: Support multiple variable pre-dividers
Chen-Yu Tsai
1
-5
/
+5
2017-03-06
clk: sunxi-ng: add Allwinner H5 CCU support for H3 CCU driver
Icenowy Zheng
1
-7
/
+320
2017-01-03
clk: sunxi-ng: fix PLL_CPUX adjusting on H3
Ondrej Jirman
1
-0
/
+10
2016-11-11
clk: sunxi-ng: sun8i-h3: Set CLK_SET_RATE_PARENT for audio module clocks
Chen-Yu Tsai
1
-5
/
+5
2016-09-14
Merge tag 'sunxi-clk-for-4.9' of https://git.kernel.org/pub/scm/linux/kernel/...
Stephen Boyd
1
-5
/
+5
2016-08-29
clk: sunxi-ng: Fix wrong reset register offsets
Jorik Jonker
1
-8
/
+8
2016-08-25
clk: sunxi-ng: mux: support fixed pre-dividers on multiple parents
Chen-Yu Tsai
1
-5
/
+5
2016-07-12
clk: sunxi-ng: h3: Fix audio clock divider offset
Maxime Ripard
1
-2
/
+2
2016-07-09
clk: sunxi-ng: Add H3 clocks
Maxime Ripard
1
-0
/
+826