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starfive-tech/linux.git
JH7100_VisionFive_OH_dev
JH7110_VisionFive2_510_devel
JH7110_VisionFive2_6.1.y_devel
JH7110_VisionFive2_6.6.y_devel
JH7110_VisionFive2_devel
JH7110_VisionFive2_upstream
beaglev-5.13.y
beaglev_fedora_devel
buildroot-upstream
esmil_starlight
fedora-vic-7100_5.10.6
master
openwrt-6.1.y
rt-ethercat-release
rt-linux-release
rtthread_AMP
starfive-5.13
starfive-5.15-dubhe
starfive-6.1-dubhe
starfive-6.1.65-dubhe
starfive-6.6.10-dubhe
starfive-6.6.31-dubhe
starlight-5.14.y
visionfive
visionfive-5.13.y-devel
visionfive-5.15.y
visionfive-5.15.y-devel
visionfive-5.15.y_fedora_devel
visionfive-5.16.y
visionfive-5.17.y
visionfive-5.18.y
visionfive-5.19.y
visionfive-6.4.y
visionfive_fedora_devel
StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)
Andrey V.Kosteltsev
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path:
root
/
drivers
/
clk
/
tegra
/
clk-divider.c
Age
Commit message (
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)
Author
Files
Lines
2020-01-10
clk: tegra: divider: Check UART's divider enable-bit state on rate's recalcul...
Dmitry Osipenko
1
-2
/
+7
2019-11-11
clk: tegra: divider: Save and restore divider rate
Sowjanya Komatineni
1
-0
/
+11
2019-05-30
treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 201
Thomas Gleixner
1
-12
/
+1
2019-04-25
clk: tegra: divider: Mark Memory Controller clock as read-only
Dmitry Osipenko
1
-1
/
+2
2018-08-15
Merge branches 'clk-imx6-ocram', 'clk-missing-put', 'clk-tegra-sdmmc-jitter',...
Stephen Boyd
1
-25
/
+5
2018-07-25
clk: tegra: Refactor fractional divider calculation
Peter De Schrijver
1
-25
/
+5
2018-07-09
clk: tegra: Mark Memory Controller clock as critical
Dmitry Osipenko
1
-2
/
+3
2015-11-16
tegra/clk-divider: fix wrong do_div() usage
Nicolas Pitre
1
-2
/
+2
2015-07-20
clk: tegra: Properly include clk.h
Stephen Boyd
1
-1
/
+0
2014-11-26
clk: tegra: Implement memory-controller clock
Thierry Reding
1
-0
/
+13
2014-02-17
clk: tegra: use max divider if divider overflows
Andrew Bresticker
1
-1
/
+1
2013-01-28
clk: tegra: add Tegra specific clocks
Prashant Gaikwad
1
-0
/
+187