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path: root/drivers/clk/tegra
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2014-02-25Merge branch 'clk-fixes' into clk-nextMike Turquette7-31/+45
2014-02-24clk: tegra: Staticize tegra_clk_periph_no_gate_opsSachin Kamat1-1/+1
tegra_clk_periph_no_gate_ops is a local symbol. Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-02-20clk: tegra124: remove gr2d and gr3d clocksPeter De Schrijver1-2/+0
Tegra124 does not have gr2d and gr3d clocks. They have been replaced by the vic03 and gpu clocks respectively. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
2014-02-20clk: tegra: Fix vic03 mux indexPeter De Schrijver1-3/+1
The vic03 mux uses a linear mapping. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
2014-02-17clk: tegra: use max divider if divider overflowsAndrew Bresticker1-1/+1
When requesting a rate less than the minimum clock rate for a divider, use the maximum divider value instead of bailing out with an error. This matches the behavior of the generic clock divider. Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
2014-02-17clk: tegra: cclk_lp has a pllx/2 dividerAndrew Bresticker1-1/+1
When pll_x is the parent of cclk_lp, PLLX_DIV2_BYPASS_LP determines whether cclk_lp output is divided by 2. Set TEGRA_DIVIDER_2 so that the clk_super driver is aware of this. Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
2014-02-17clk: tegra: fix sdmmc clks on Tegra1x4Andrew Bresticker4-8/+16
The sdmmc clocks on Tegra114 and Tegra124 are 3-bit wide muxes with 6 parents. Add support for tegra_clk_sdmmc*_8 and switch Tegra114 and Tegra124 to use these clocks instead. Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
2014-02-17clk: tegra: fix host1x clock on Tegra124Mark Zhang1-1/+1
The host1x clock on Tegra124 is a 3-bit wide mux with 6 parents. Change thte id to tegra_clk_host1x_8 so that the correct clock gets registered. Signed-off-by: Mark Zhang <markz@nvidia.com> Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
2014-02-17clk: tegra: PLLD2 fixes for hdmiDavid Ung1-8/+7
Set correct pll_d2_out0 divider and correct the p div values for pll_d2. Signed-off-by: David Ung <davidu@nvidia.com> Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
2014-02-17clk: tegra: Fix PLLD mnp tableRhyland Klein1-1/+10
PLLD was using the same mnp table as PLLP. Fix it to use its own table which is different from PLLP's. Signed-off-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
2014-02-17clk: tegra: Fix PLLP rate tableGabe Black1-5/+5
This table had settings for 216MHz, but PLLP is (and is supposed to be) configured at 408MHz. If that table is used and PLLP_BASE_OVRRIDE is not set, the kernel will panic in clk_pll_recalc_rate(). Signed-off-by: Gabe Black <gabeblack@google.com> Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
2014-02-17clk: tegra: Correct clock number for UARTEThierry Reding1-1/+1
UARTE has clock number 66. Number 65 is the right one for UARTD. Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-02-17clk: tegra: Add missing Tegra20 fuse clksPeter De Schrijver1-0/+2
Add clocks required for accessing fuses on Tegra20. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com>
2014-01-24Merge tag 'clk-for-linus-3.14-part1' of ↵Linus Torvalds2-7/+7
git://git.linaro.org/people/mike.turquette/linux Pull clk framework changes from Mike Turquette: "The first half of the clk framework pull request is made up almost entirely of new platform/driver support. There are some conversions of existing drivers to the common-clock Device Tree binding, and a few non-critical fixes to the framework. Due to an entirely unnecessary cyclical dependency with the arm-soc tree this pull request is broken into two pieces. The second piece will be sent out after arm-soc sends you the pull request that merged in core support for the HiSilicon 3620 platform. That same pull request from arm-soc depends on this pull request to merge in those HiSilicon bits without causing build failures" [ Just did the ARM SoC merges, so getting ready for the second clk tree pull request - Linus ] * tag 'clk-for-linus-3.14-part1' of git://git.linaro.org/people/mike.turquette/linux: (97 commits) devicetree: bindings: Document qcom,mmcc devicetree: bindings: Document qcom,gcc clk: qcom: Add support for MSM8660's global clock controller (GCC) clk: qcom: Add support for MSM8974's multimedia clock controller (MMCC) clk: qcom: Add support for MSM8974's global clock controller (GCC) clk: qcom: Add support for MSM8960's multimedia clock controller (MMCC) clk: qcom: Add support for MSM8960's global clock controller (GCC) clk: qcom: Add reset controller support clk: qcom: Add support for branches/gate clocks clk: qcom: Add support for root clock generators (RCGs) clk: qcom: Add support for phase locked loops (PLLs) clk: qcom: Add a regmap type clock struct clk: Add set_rate_and_parent() op reset: Silence warning in reset-controller.h clk: sirf: re-arch to make the codes support both prima2 and atlas6 clk: composite: pass mux_hw into determine_rate clk: shmobile: Fix MSTP clock array initialization clk: shmobile: Fix MSTP clock index ARM: dts: Add clock provider specific properties to max77686 node clk: max77686: Register OF clock provider ...
2013-12-20clk: tegra: Staticize tegra_clk_periph_nodiv_opsSachin Kamat1-1/+1
tegra_clk_periph_nodiv_ops is used only in this file. Make it static. Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-12-20clk: tegra: Staticize local variables in clk-pll.cSachin Kamat1-6/+6
Local variables used only in this file are made static. Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Cc: Stephen Warren <swarren@nvidia.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-12-12clk: tegra: remove bogus PCIE_XCLKStephen Warren2-13/+0
The "pcie_xclk" clock is not actually a clock at all, but rather a reset domain. Now that the custom Tegra module reset API has been removed, we can remove the definition of any "clocks" that existed solely to support it. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Acked-By: Peter De Schrijver <pdeschrijver@nvidia.com>
2013-12-12clk: tegra: remove legacy reset APIsStephen Warren3-63/+0
Now that no code uses the custom Tegra module reset API, we can remove its implementation. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Acked-By: Peter De Schrijver <pdeschrijver@nvidia.com>
2013-12-12clk: tegra: implement a reset driverStephen Warren6-6/+57
The Tegra CAR module implements both a clock and reset controller. So far, the driver exposes the clock feature via the common clock API and the reset feature using a custom API. This patch adds an implementation of the common reset framework API (include/linux/reset*.h). The legacy reset implementation will be removed once all drivers have been converted. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Acked-By: Peter De Schrijver <pdeschrijver@nvidia.com>
2013-11-28clk: tegra: fix __clk_lookup() return value checksWei Yongjun1-4/+4
In case of error, the function __clk_lookup() returns NULL pointer not ERR_PTR(). The IS_ERR() test in the return value check should be replaced with NULL test. Signed-off-by: Wei Yongjun <yongjun_wei@trendmicro.com.cn> Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
2013-11-28clk: tegra: Do not print errors for clk_round_rate()Thierry Reding1-6/+3
clk_round_rate() can be used by drivers to determine whether or not a frequency is supported by the clock. The current Tegra clock driver outputs an error message and a stacktrace when the requested rate isn't supported. That's fine for clk_set_rate(), but it's confusing when all the driver does is query whether or not a frequency is supported. Signed-off-by: Thierry Reding <treding@nvidia.com>
2013-11-26clk: tegra: Initialize DSI low-power clocksThierry Reding1-0/+2
The low-power DSI clocks are used during host-driven transactions on the DSI bus. Documentation recommends that they be children of PLLP and run at a frequency of at least 52 MHz. Signed-off-by: Thierry Reding <treding@nvidia.com>
2013-11-26clk: tegra: add FUSE clock deviceAlexandre Courbot4-1/+4
This clock is needed to ensure the FUSE registers can be accessed without freezing the system. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
2013-11-26clk: tegra: Properly setup PWM clock on Tegra30Thierry Reding1-1/+3
The clock for the PWM controller is slightly different from other peripheral clocks on Tegra30. The clock source mux field start at bit position 28 rather than 30. Signed-off-by: Thierry Reding <treding@nvidia.com>
2013-11-26clk: tegra: Initialize secondary gr3d clock on Tegra30Thierry Reding1-0/+1
There are two GPUs on Tegra30 and each of them uses a separate clock, so the secondary clock needs to be initialized in order for the gr3d module to work properly. Signed-off-by: Thierry Reding <treding@nvidia.com>
2013-11-26clk: tegra114: Initialize clocks needed for HDMIMikko Perttunen1-0/+2
Add disp1 and disp2 clocks to the clock initialization table. These clocks are required for display and HDMI support. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2013-11-26clk: tegra124: add suspend/resume function for tegra_cpu_car_opsJoseph Lo1-0/+27
Adding suspend/resume function for tegra_cpu_car_ops. We only save and restore the setting of the clock of CoreSight. Other clocks still need to be taken care by clock driver. Cc: Mike Turquette <mturquette@linaro.org> Signed-off-by: Joseph Lo <josephl@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com>
2013-11-26clk: tegra124: add wait_for_reset and disable_clock for tegra_cpu_car_opsJoseph Lo1-0/+26
Hook the functions for CPU hotplug support. After the CPU is hot unplugged, the flow controller will handle to clock gate the CPU clock. But still need to implement an empty function to avoid warning message. Cc: Mike Turquette <mturquette@linaro.org> Signed-off-by: Joseph Lo <josephl@nvidia.com>
2013-11-26clk: tegra124: Add support for Tegra124 clocksPeter De Schrijver2-0/+1371
Implement clock support for Tegra124. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
2013-11-26clk: tegra124: Add new peripheral clocksPeter De Schrijver1-0/+69
Tegra124 introduces a number of new peripheral clocks. This patch adds those to the common peripheral clock code. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
2013-11-26clk: tegra124: Add common clk IDs to clk-id.hPeter De Schrijver1-0/+22
Tegra124 introduces a number of a new clocks. Introduce the corresponding the IDs for them. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
2013-11-26clk: tegra: add TEGRA_PERIPH_NO_GATEPeter De Schrijver3-3/+22
Tegra124 has a clock which consists of a mux and a fractional divider. Add support for this. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2013-11-26clk: tegra: add locking to periph clksPeter De Schrijver2-19/+24
Tegra124 has periph clocks which share the hw register. Hence locking is required. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2013-11-26clk: tegra: Add periph regs bank XPeter De Schrijver1-0/+10
Tegra124 has an extra bank of peripheral clock registers. Add it to the generic peripheral clock code. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
2013-11-26clk: tegra: Add support for PLLSSPeter De Schrijver2-2/+126
Tegra124 introduces a new PLL type, PLLSS. Add support for it. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
2013-11-26clk: tegra: move tegra20 to common infraPeter De Schrijver1-402/+255
Move tegra20 to common tegra clock infrastructure. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
2013-11-26clk: tegra: move tegra30 to common infraPeter De Schrijver1-895/+403
Move tegra30 to common tegra clock infrastructure. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
2013-11-26clk: tegra: introduce common gen4 super clockPeter De Schrijver4-74/+155
Introduce a common function which performs super clock initialization for Tegra114 and beyond. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
2013-11-26clk: tegra: move PMC, fixed clocks to common filesPeter De Schrijver5-74/+253
Introduce new files for fixed and PMC clocks common between several Tegra SoCs and move Tegra114 to this new infrastructure. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
2013-11-26clk: tegra: move periph clocks to common filePeter De Schrijver6-581/+627
Introduce a new file for peripheral clocks common between several Tegra SoCs and move Tegra114 to this new infrastructure. Also PLLP and the PLLP_OUT clocks will be initialized here. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
2013-11-26clk: tegra: move audio clk to common filePeter De Schrijver4-208/+402
Move audio clocks and PLLA initialization to a common file so it can be used by multiple Tegra SoCs. Also a new array tegra114_clks is introduced for Tegra114 which specifies which common clocks are available on Tegra114 and what their DT IDs are. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
2013-11-26clk: tegra: add clkdev registration infraPeter De Schrijver3-159/+179
Add a common infra for registering clkdev. This allows decoupling clk registration from clkdev registration. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
2013-11-26clk: tegra: add common infra for DT clocksPeter De Schrijver2-0/+16
Introduce a common infrastructure for sharing clock initialization between SoCs. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
2013-11-26clk: tegra: add header for common tegra clock IDsPeter De Schrijver1-0/+213
Many clocks are common between several Tegra SoCs. Define an enum to list them so we can move them to separate files which can be shared between SoCs. Each SoC specific file will provide an array with the common clocks which are present on the SoC and their DT binding ID. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
2013-11-26clk: tegra: move fields to tegra_clk_pll_paramsPeter De Schrijver5-177/+175
Move some fields related to the PLL HW description to the tegra_clk_pll_params. This allows some PLL code to be moved to common files later. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
2013-11-26clk: tegra: use pll_ref as the pll_e parentPeter De Schrijver2-4/+7
Use pll_ref instead of pll_re_vco as the pll_e parent on Tegra114. Also add a 12Mhz pll_ref table entry for pll_e for Tegra114. This prevents the system from crashing at bootup because of an unsupported pll_re_vco rate. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
2013-11-26clk: tegra: move some PLLC and PLLXC init to clk-pll.cPeter De Schrijver2-93/+111
VCO min clipping, dynamic ramp setup and IDDQ init can be done in the respective PLL clk_register functions if the parent is already registered. This is done for other some PLLs already. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
2013-11-26clk: tegra: Add TEGRA_PERIPH_NO_DIV flagPeter De Schrijver2-3/+9
This flag indicates the peripheral clock does not have a divider. It will simplify the initialization tables and avoids some very similar code. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
2013-11-26clk: tegra: common periph_clk_enb_refcnt and clksPeter De Schrijver6-108/+85
This patch makes periph_clk_enb_refcnt a global array, dynamically allocated at boottime. It simplifies the macros somewhat and allows clocks common to several Tegra SoCs to be defined in a separate files. Also the clks array becomes global and dynamically allocated which allows the DT registration to be moved to a generic funcion. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
2013-11-26clk: tegra: simplify periph clock dataPeter De Schrijver7-584/+464
This patch determines the register bank for clock enable/disable and reset based on the clock ID instead of hardcoding it in the tables describing the clocks. This results in less data to be maintained in the tables, making the code easier to understand. The full benefit of the change will be realized once also other clocktypes will be table based. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
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