| Age | Commit message (Collapse) | Author | Files | Lines |
|---|
|
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
|
|
git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk fixes from Stephen Boyd:
"A set of clk fixes for the Qualcomm, Mediatek, and Allwinner drivers:
- Fix the Qualcomm Stromer Plus PLL set_rate() clk_op to explicitly
set the alpha enable bit and not set bits that don't exist
- Mark Qualcomm IPQ9574 crypto clks as voted to avoid stuck clk
warnings
- Fix the parent of some PLLs on Qualcomm sm6530 so their rate is
correct
- Fix the min/max rate clamping logic in the Allwinner driver that
got broken in v6.9
- Limit runtime PM enabling in the Mediatek driver to only
mt8183-mfgcfg so that system wide resume doesn't break on other
Mediatek SoCs"
* tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux:
clk: mediatek: mt8183: Only enable runtime PM on mt8183-mfgcfg
clk: sunxi-ng: common: Don't call hw_to_ccu_common on hw without common
clk: qcom: gcc-ipq9574: Add BRANCH_HALT_VOTED flag
clk: qcom: apss-ipq-pll: remove 'config_ctl_hi_val' from Stromer pll configs
clk: qcom: clk-alpha-pll: set ALPHA_EN bit for Stromer Plus PLLs
clk: qcom: gcc-sm6350: Fix gpll6* & gpll7 parents
|
|
https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into clk-fixes
Pull Qualcomm clk driver fixes from Bjorn Andersson:
- Correct the Stromer Plus PLL set_rate to explicitly set ALPHA_EN bit and
remove unnecessary upper parts of CONFIG_CTL values.
- Mark the recently added IPQ9574 GCC crypto clocks BRANCH_HALT_VOTED, to
address stuck clock warnings.
- Fix the GPLL6 and GPLL7 parents on SM6350 to avoid issues with these
reportedly running at ~25GHz.
* tag 'qcom-clk-fixes-for-6.10' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux:
clk: qcom: gcc-ipq9574: Add BRANCH_HALT_VOTED flag
clk: qcom: apss-ipq-pll: remove 'config_ctl_hi_val' from Stromer pll configs
clk: qcom: clk-alpha-pll: set ALPHA_EN bit for Stromer Plus PLLs
clk: qcom: gcc-sm6350: Fix gpll6* & gpll7 parents
|
|
Commit 2f7b1d8b5505 ("clk: mediatek: Do a runtime PM get on controllers
during probe") enabled runtime PM for all mediatek clock controllers,
but this introduced an issue on the resume path.
If a device resumes earlier than the clock controller and calls
clk_prepare() when runtime PM is enabled on the controller, it will end
up calling clk_pm_runtime_get(). But the subsequent
pm_runtime_resume_and_get() call will fail because the runtime PM is
temporarily disabled during suspend.
To workaround this, introduce a need_runtime_pm flag and only enable it
on mt8183-mfgcfg, which is the driver that observed deadlock previously.
Hopefully mt8183-cfgcfg won't run into the issue at the resume stage
because the GPU should have stopped rendering before the system calls
suspend.
Fixes: 2f7b1d8b5505 ("clk: mediatek: Do a runtime PM get on controllers during probe")
Signed-off-by: Pin-yen Lin <treapking@chromium.org>
Link: https://lore.kernel.org/r/20240613120357.1043342-1-treapking@chromium.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
|
|
https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-fixes
Pull one Allwinner SoC clk driver fix for 6.10
- Fix min/max rate clamping that caused a regression back in 6.9
* tag 'sunxi-clk-fixes-for-6.10' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
clk: sunxi-ng: common: Don't call hw_to_ccu_common on hw without common
|
|
In order to set the rate range of a hw sunxi_ccu_probe calls
hw_to_ccu_common() assuming all entries in desc->ccu_clks are contained
in a ccu_common struct. This assumption is incorrect and, in
consequence, causes invalid pointer de-references.
Remove the faulty call. Instead, add one more loop that iterates over
the ccu_clks and sets the rate range, if required.
Fixes: b914ec33b391 ("clk: sunxi-ng: common: Support minimum and maximum rate")
Reported-by: Robert J. Pafford <pafford.9@buckeyemail.osu.edu>
Closes: https://lore.kernel.org/lkml/DM6PR01MB58047C810DDD5D0AE397CADFF7C22@DM6PR01MB5804.prod.exchangelabs.com/
Cc: stable@vger.kernel.org
Signed-off-by: Frank Oltmanns <frank@oltmanns.dev>
Tested-by: Robert J. Pafford <pafford.9@buckeyemail.osu.edu>
Link: https://lore.kernel.org/r/20240623-sunxi-ng_fix_common_probe-v1-1-7c97e32824a1@oltmanns.dev
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
|
|
Pull ARM and clkdev fixes from Russell King:
- Fix clkdev - erroring out on long strings causes boot failures, so
don't do this. Still warn about the over-sized strings (which will
never match and thus their registration with clkdev is useless)
- Fix for ftrace with frame pointer unwinder with recent GCC changing
the way frames are stacked.
* tag 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/rmk/linux:
ARM: 9405/1: ftrace: Don't assume stack frames are contiguous in memory
clkdev: don't fail clkdev_alloc() if over-sized
|
|
|
|
Don't fail clkdev_alloc() if the strings are over-sized. In this case,
the entry will not match during lookup, so its useless. However, since
code fails if we return NULL leading to boot failure, return a dummy
entry with the connection and device IDs set to "bad".
Leave the warning so these problems can be found, and the useless
wasteful clkdev registrations removed.
Reported-by: Ron Economos <re@w6rz.net>
Reported-by: Guenter Roeck <linux@roeck-us.net>
Fixes: 8d532528ff6a ("clkdev: report over-sized strings when creating clkdev entries")
Closes: https://lore.kernel.org/linux-clk/7eda7621-0dde-4153-89e4-172e4c095d01@roeck-us.net.
Link: https://lore.kernel.org/r/28114882-f8d7-21bf-4536-a186e8d7a22a@w6rz.net
Tested-by: Ron Economos <re@w6rz.net>
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
|
|
These clkdevs were unnecessary, because systems using this driver always
look up clocks using the devicetree. And as Russell King points out[1],
since the provided device name was truncated, lookups via clkdev would
never match.
Recently, commit 8d532528ff6a ("clkdev: report over-sized strings when
creating clkdev entries") caused clkdev registration to fail due to the
truncation, and this now prevents the driver from probing. Fix the
driver by removing the clkdev registration.
Link: https://lore.kernel.org/linux-clk/ZkfYqj+OcAxd9O2t@shell.armlinux.org.uk/ [1]
Fixes: 30b8e27e3b58 ("clk: sifive: add a driver for the SiFive FU540 PRCI IP block")
Fixes: 8d532528ff6a ("clkdev: report over-sized strings when creating clkdev entries")
Reported-by: Guenter Roeck <linux@roeck-us.net>
Closes: https://lore.kernel.org/linux-clk/7eda7621-0dde-4153-89e4-172e4c095d01@roeck-us.net/
Suggested-by: Russell King <linux@armlinux.org.uk>
Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
Link: https://lore.kernel.org/r/20240528001432.1200403-1-samuel.holland@sifive.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
|
|
The crypto_ahb and crypto_axi clks are hardware voteable.
This means that the halt bit isn't reliable because some
other voter in the system, e.g. TrustZone, could be keeping
the clk enabled when the kernel turns it off from clk_disable().
Make these clks use voting mode by changing the halt check to
BRANCH_HALT_VOTED and toggle the voting bit in the voting register
instead of directly controlling the branch by writing to the branch
register. This fixes stuck clk warnings seen on ipq9574 and saves
power by actually turning the clk off.
Also changes the CRYPTO_AHB_CLK_ENA & CRYPTO_AXI_CLK_ENA
offset to 0xb004 from 0x16014.
Cc: stable@vger.kernel.org
Fixes: f6b2bd9cb29a ("clk: qcom: gcc-ipq9574: Enable crypto clocks")
Signed-off-by: Md Sadre Alam <quic_mdalam@quicinc.com>
Link: https://lore.kernel.org/r/20240509105405.1262369-1-quic_mdalam@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
|
|
Since the CONFIG_CTL register is only 32 bits wide in the Stromer
and Stromer Plus PLLs , the 'config_ctl_hi_val' values from the
IPQ5018 and IPQ5332 configurations are not used so remove those.
No functional changes.
Signed-off-by: Gabor Juhos <j4g8y7@gmail.com>
Reviewed-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
Acked-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20240509-stromer-config-ctl-v1-1-6034e17b28d5@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
|
|
The clk_alpha_pll_stromer_plus_set_rate() function does not
sets the ALPHA_EN bit in the USER_CTL register, so setting
rates which requires using alpha mode works only if the bit
gets set already prior calling the function.
Extend the function to set the ALPHA_EN bit in order to allow
using fractional rates regardless whether the bit gets set
previously or not.
Fixes: 84da48921a97 ("clk: qcom: clk-alpha-pll: introduce stromer plus ops")
Signed-off-by: Gabor Juhos <j4g8y7@gmail.com>
Link: https://lore.kernel.org/r/20240508-stromer-plus-alpha-en-v1-1-6639ce01ca5b@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
|
|
Both gpll6 and gpll7 are parented to CXO at 19.2 MHz and not to GPLL0
which runs at 600 MHz. Also gpll6_out_even should have the parent gpll6
and not gpll0.
Adjust the parents of these clocks to make Linux report the correct rate
and not absurd numbers like gpll7 at ~25 GHz or gpll6 at 24 GHz.
Corrected rates are the following:
gpll7 807999902 Hz
gpll6 768000000 Hz
gpll6_out_even 384000000 Hz
gpll0 600000000 Hz
gpll0_out_odd 200000000 Hz
gpll0_out_even 300000000 Hz
And because gpll6 is the parent of gcc_sdcc2_apps_clk_src (at 202 MHz)
that clock also reports the correct rate now and avoids this warning:
[ 5.984062] mmc0: Card appears overclocked; req 202000000 Hz, actual 6312499237 Hz
Fixes: 131abae905df ("clk: qcom: Add SM6350 GCC driver")
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Link: https://lore.kernel.org/r/20240508-sm6350-gpll-fix-v1-1-e4ea34284a6d@fairphone.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
|
|
git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk updates from Stephen Boyd:
"I'm actually surprised this time. There aren't any new Qualcomm SoC
clk drivers. And there's zero diff in the core clk framework.
Instead we have new clk drivers for STM and Sophgo, with
Samsung^WGoogle in third for the diffstat because they introduced HSI0
and HSI2 clk drivers for Google's GS101 SoC (high speed interface
things like PCIe, UFS, and MMC).
Beyond those big diffs there's the usual updates to various clk
drivers for incorrect parent descriptions or mising
MODULE_DEVICE_TABLE()s, etc. Nothing in particular stands out as super
interesting here.
New Drivers:
- STM32MP257 SoC clk driver
- Airoha EN7581 SoC clk driver
- Sophgo CV1800B, CV1812H and SG2000 SoC clk driver
- Loongson-2k0500 and Loongson-2k2000 SoC clk driver
- Add HSI0 and HSI2 clock controllers for Google GS101
- Add i.MX95 BLK CTL clock driver
Updates:
- Allocate clk_ops dynamically for SCMI clk driver
- Add support in qcom RCG and RCG2 for multiple configurations for
the same frequency
- Use above support for IPQ8074 NSS port 5 and 6 clocks to resolve
issues
- Fix the Qualcomm APSS IPQ5018 PLL to fix boot failures of some
boards
- Cleanups and fixes for Qualcomm Stromer PLLs
- Reduce max CPU frequency on Qualcomm APSS IPQ5018
- Fix Kconfig dependencies of Qualcomm SM8650 GPU and SC8280XP camera
clk drivers
- Make Qualcomm MSM8998 Venus clocks functional
- Cleanup downstream remnants related to DisplayPort across Qualcomm
SM8450, SM6350, SM8550, and SM8650
- Reuse the Huayra APSS register map on Qualcomm MSM8996 CBF PLL
- Use a specific Qualcomm QCS404 compatible for the otherwise generic
HFPLL
- Remove Qualcomm SM8150 CPUSS AHB clk as it is unused
- Remove an unused field in the Qualcomm RPM clk driver
- Add missing MODULE_DEVICE_TABLE to Qualcomm MSM8917 and MSM8953
global clock controller drivers
- Allow choice of manual or firmware-driven control over PLLs, needed
to fully implement CPU clock controllers on Exynos850
- Correct PLL clock IDs on ExynosAutov9
- Propagate certain clock rates to allow setting proper SPI clock
rates on Google GS101
- Mark certain Google GS101 clocks critical
- Convert old S3C64xx clock controller bindings to DT schema
- Add new PLL rate and missing mux on Rockchip rk3568
- Add missing reset line on Rockchip rk3588
- Removal of an unused field in struct rockchip_mmc_clock
- Amlogic s4/a1: add regmap maximum register for proper debugfs dump
- Amlogic s4: add MODULE_DEVICE_TABLE() on pll and periph controllers
- Amlogic pll driver: print clock name on lock error to help debug
- Amlogic vclk: finish dsi clock path support
- Amlogic license: fix occurence "GPL v2" as reported by checkpatch
- Add PM runtime support to i.MX8MP Audiomix
- Add DT schema for i.MX95 Display Master Block Control
- Convert to platform remove callback returning void for i.MX8MP
Audiomix
- Add SPI (MSIOF) and external interrupt (INTC-EX) clocks on Renesas
R-Car V4M
- Add interrupt controller (PLIC) clock and reset on Renesas RZ/Five
- Prepare power domain support for Renesas RZ/G2L family members, and
add actual support on Renesas RZ/G3S SoC
- Add thermal, serial (SCIF), and timer (CMT/TMU) clocks on Renesas
R-Car V4M
- Add additional constraints to Allwinner A64 PLL MIPI clock
- Fix autoloading sunxi-ng clocks when build as a module"
* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (118 commits)
clk: samsung: Don't register clkdev lookup for the fixed rate clocks
clk, reset: microchip: mpfs: fix incorrect preprocessor conditions
clk: qcom: clk-alpha-pll: fix rate setting for Stromer PLLs
clk: qcom: apss-ipq-pll: fix PLL rate for IPQ5018
clk: qcom: Fix SM_GPUCC_8650 dependencies
clk: qcom: Fix SC_CAMCC_8280XP dependencies
dt-bindings: clocks: stm32mp25: add access-controllers description
clock, reset: microchip: move all mpfs reset code to the reset subsystem
clk: samsung: gs101: drop unused HSI2 clock parent data
clk: rockchip: rk3568: Add PLL rate for 724 MHz
clk: rockchip: Remove an unused field in struct rockchip_mmc_clock
dt-bindings: clock: fixed: Define a preferred node name
clk: meson: s4: fix module autoloading
clk: samsung: gs101: mark some apm UASC and XIU clocks critical
clk: imx: imx8mp: Convert to platform remove callback returning void
clk: imx: imx8mp: Switch to RUNTIME_PM_OPS()
clk: bcm: rpi: Assign ->num before accessing ->hws
clk: bcm: dvp: Assign ->num before accessing ->hws
clk: samsung: gs101: add support for cmu_hsi2
clk: samsung: gs101: add support for cmu_hsi0
...
|
|
Pull ARM updates from Russell King:
- Updates to AMBA bus subsystem to drop .owner struct device_driver
initialisations, moving that to code instead.
- Add LPAE privileged-access-never support
- Add support for Clang CFI
- clkdev: report over-sized device or connection strings
* tag 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/rmk/linux: (36 commits)
ARM: 9398/1: Fix userspace enter on LPAE with CC_OPTIMIZE_FOR_SIZE=y
clkdev: report over-sized strings when creating clkdev entries
ARM: 9393/1: mm: Use conditionals for CFI branches
ARM: 9392/2: Support CLANG CFI
ARM: 9391/2: hw_breakpoint: Handle CFI breakpoints
ARM: 9390/2: lib: Annotate loop delay instructions for CFI
ARM: 9389/2: mm: Define prototypes for all per-processor calls
ARM: 9388/2: mm: Type-annotate all per-processor assembly routines
ARM: 9387/2: mm: Rewrite cacheflush vtables in CFI safe C
ARM: 9386/2: mm: Use symbol alias for cache functions
ARM: 9385/2: mm: Type-annotate all cache assembly routines
ARM: 9384/2: mm: Make tlbflush routines CFI safe
ARM: 9382/1: ftrace: Define ftrace_stub_graph
ARM: 9358/2: Implement PAN for LPAE by TTBR0 page table walks disablement
ARM: 9357/2: Reduce the number of #ifdef CONFIG_CPU_SW_DOMAIN_PAN
ARM: 9356/2: Move asm statements accessing TTBCR into C functions
ARM: 9355/2: Add TTBCR_* definitions to pgtable-3level-hwdef.h
ARM: 9379/1: coresight: tpda: drop owner assignment
ARM: 9378/1: coresight: etm4x: drop owner assignment
ARM: 9377/1: hwrng: nomadik: drop owner assignment
...
|
|
* clk-microchip:
clk, reset: microchip: mpfs: fix incorrect preprocessor conditions
clock, reset: microchip: move all mpfs reset code to the reset subsystem
* clk-samsung:
clk: samsung: Don't register clkdev lookup for the fixed rate clocks
clk: samsung: gs101: drop unused HSI2 clock parent data
clk: samsung: gs101: mark some apm UASC and XIU clocks critical
clk: samsung: gs101: add support for cmu_hsi2
clk: samsung: gs101: add support for cmu_hsi0
dt-bindings: clock: google,gs101-clock: add HSI2 clock management unit
dt-bindings: clock: google,gs101-clock: add HSI0 clock management unit
clk: samsung: gs101: propagate PERIC1 USI SPI clock rate
clk: samsung: gs101: propagate PERIC0 USI SPI clock rate
clk: samsung: exynosautov9: fix wrong pll clock id value
dt-bindings: clock: samsung,s3c6400-clock: convert to DT Schema
clk: samsung: exynos850: Add CMU_CPUCL0 and CMU_CPUCL1
clk: samsung: Implement manual PLL control for ARM64 SoCs
* clk-qcom: (27 commits)
clk: qcom: clk-alpha-pll: fix rate setting for Stromer PLLs
clk: qcom: apss-ipq-pll: fix PLL rate for IPQ5018
clk: qcom: Fix SM_GPUCC_8650 dependencies
clk: qcom: Fix SC_CAMCC_8280XP dependencies
clk: qcom: mmcc-msm8998: fix venus clock issue
clk: qcom: dispcc-sm8650: fix DisplayPort clocks
clk: qcom: dispcc-sm8550: fix DisplayPort clocks
clk: qcom: dispcc-sm6350: fix DisplayPort clocks
clk: qcom: dispcc-sm8450: fix DisplayPort clocks
clk: qcom: clk-cbf-8996: use HUAYRA_APSS register map for cbf_pll
clk: qcom: apss-ipq-pll: constify clk_init_data structures
clk: qcom: apss-ipq-pll: constify match data structures
clk: qcom: apss-ipq-pll: move Huayra register map to 'clk_alpha_pll_regs'
clk: qcom: apss-ipq-pll: reuse Stromer reg offsets from 'clk_alpha_pll_regs'
clk: qcom: apss-ipq-pll: use stromer ops for IPQ5018 to fix boot failure
clk: qcom: gcc-ipq8074: rework nss_port5/6 clock to multiple conf
clk: qcom: clk-rcg2: add support for rcg2 freq multi ops
clk: qcom: clk-rcg: introduce support for multiple conf for same freq
clk: qcom: hfpll: Add QCS404-specific compatible
dt-bindings: clock: qcom,hfpll: Convert to YAML
...
|
|
'clk-rockchip' into clk-next
* clk-counted:
clk: bcm: rpi: Assign ->num before accessing ->hws
clk: bcm: dvp: Assign ->num before accessing ->hws
* clk-imx:
clk: imx: imx8mp: Convert to platform remove callback returning void
clk: imx: imx8mp: Switch to RUNTIME_PM_OPS()
clk: imx: add i.MX95 BLK CTL clk driver
dt-bindings: clock: support i.MX95 Display Master CSR module
dt-bindings: clock: support i.MX95 BLK CTL module
dt-bindings: clock: add i.MX95 clock header
clk: imx: imx8mp: Add pm_runtime support for power saving
* clk-amlogic:
clk: meson: s4: fix module autoloading
clk: meson: fix module license to GPL only
clk: meson: g12a: make VCLK2 and ENCL clock path configurable by CCF
clk: meson: add vclk driver
clk: meson: pll: print out pll name when unable to lock it
clk: meson: s4: pll: determine maximum register in regmap config
clk: meson: s4: peripherals: determine maximum register in regmap config
clk: meson: a1: pll: determine maximum register in regmap config
clk: meson: a1: peripherals: determine maximum register in regmap config
* clk-binding:
dt-bindings: clock: fixed: Define a preferred node name
* clk-rockchip:
clk: rockchip: rk3568: Add PLL rate for 724 MHz
clk: rockchip: Remove an unused field in struct rockchip_mmc_clock
clk: rockchip: rk3588: Add reset line for HDMI Receiver
clk: rockchip: rk3568: Add missing USB480M_PHY mux
dt-bindings: reset: Define reset id used for HDMI Receiver
dt-bindings: clock: rockchip: add USB480M_PHY mux
|
|
clk-next
- STM32MP257 SoC clk driver
- Allocate clk_ops dynamically for SCMI clk driver
* clk-stm:
dt-bindings: clocks: stm32mp25: add access-controllers description
clk: stm32: introduce clocks for STM32MP257 platform
dt-bindings: clocks: stm32mp25: add description of all parents
clk: stm32mp13: use platform device APIs
* clk-renesas:
clk: renesas: r9a08g045: Add support for power domains
clk: renesas: rzg2l: Extend power domain support
dt-bindings: clock: renesas,rzg2l-cpg: Update #power-domain-cells = <1> for RZ/G3S
dt-bindings: clock: r9a08g045-cpg: Add power domain IDs
dt-bindings: clock: r9a07g054-cpg: Add power domain IDs
dt-bindings: clock: r9a07g044-cpg: Add power domain IDs
dt-bindings: clock: r9a07g043-cpg: Add power domain IDs
clk: renesas: shmobile: Remove unused CLK_ENABLE_ON_INIT
clk: renesas: r8a7740: Remove unused div4_clk.flags field
clk: renesas: r9a07g043: Add clock and reset entry for PLIC
clk: renesas: r8a779h0: Add INTC-EX clock
clk: renesas: r8a779h0: Add MSIOF clocks
clk: renesas: r8a779a0: Fix CANFD parent clock
clk: rs9: fix wrong default value for clock amplitude
clk: renesas: r8a779h0: Add timer clocks
clk: renesas: r8a779h0: Add SCIF clocks
clk: renesas: r9a07g044: Mark resets array as const
clk: renesas: r9a07g043: Mark mod_clks and resets arrays as const
clk: renesas: r8a779h0: Add thermal clock
dt-bindings: clock: r9a07g043-cpg: Annotate RZ/G2UL-only core clocks
* clk-scmi:
clk: scmi: Add support for get/set duty_cycle operations
clk: scmi: Add support for re-parenting restricted clocks
clk: scmi: Add support for rate change restricted clocks
clk: scmi: Add support for state control restricted clocks
clk: scmi: Allocate CLK operations dynamically
* clk-allwinner:
clk: sunxi-ng: fix module autoloading
clk: sunxi-ng: a64: Add constraints on PLL-MIPI's n/m ratio and parent rate
clk: sunxi-ng: nkm: Support constraints on m/n ratio and parent rate
|
|
'clk-loongson' into clk-next
- Airoha EN7581 SoC clk driver
- Sophgo CV1800B, CV1812H and SG2000 SoC clk driver
- Loongson-2k0500 and Loongson-2k2000 SoC clk driver
* clk-cleanup:
clk: gemini: Remove an unused field in struct clk_gemini_pci
clk: highbank: Remove an unused field in struct hb_clk
clk: ti: dpll: fix incorrect #ifdef checks
clk: nxp: Remove an unused field in struct lpc18xx_pll
* clk-airoha:
clk: en7523: Add EN7581 support
clk: en7523: Add en_clk_soc_data data structure
dt-bindings: clock: airoha: add EN7581 binding
* clk-mediatek:
clk: mediatek: mt8365-mm: fix DPI0 parent
clk: mediatek: pllfh: Don't log error for missing fhctl node
* clk-sophgo:
clk: sophgo: avoid open-coded 64-bit division
clk: sophgo: Make synthesizer struct static
clk: sophgo: Add clock support for SG2000 SoC
clk: sophgo: Add clock support for CV1810 SoC
clk: sophgo: Add clock support for CV1800 SoC
dt-bindings: clock: sophgo: Add clock controller of SG2000 series SoC
* clk-loongson:
clk: clk-loongson2: Add Loongson-2K2000 clock support
dt-bindings: clock: loongson2: Add Loongson-2K2000 compatible
clk: clk-loongson2: Add Loongson-2K0500 clock support
dt-bindings: clock: loongson2: Add Loongson-2K0500 compatible
clk: clk-loongson2: Refactor driver for adding new platforms
dt-bindings: clock: Add Loongson-2K expand clock index
|
|
|
|
Commit 4d11c62ca8d7 ("clkdev: report over-sized strings when creating
clkdev entries") revealed that clock lookup is registered for all fixed
clocks. The mentioned commit added a check if the registered name is not
too long. This fails for some clocks registered for Exynos542x SoCs family.
This lookup is a left-over from early common clock framework days, not
really needed nowadays, so remove it to avoid further issues.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org>
Tested-by: Sam Protsenko <semen.protsenko@linaro.org>
Link: https://lore.kernel.org/r/20240510065901.535124-1-m.szyprowski@samsung.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
|
|
git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull SoC driver updates from Arnd Bergmann:
"As usual, these are updates for drivers that are specific to certain
SoCs or firmware running on them.
Notable updates include
- The new STMicroelectronics STM32 "firewall" bus driver that is used
to provide a barrier between different parts of an SoC
- Lots of updates for the Qualcomm platform drivers, in particular
SCM, which gets a rewrite of its initialization code
- Firmware driver updates for Arm FF-A notification interrupts and
indirect messaging, SCMI firmware support for pin control and
vendor specific interfaces, and TEE firmware interface changes
across multiple TEE drivers
- A larger cleanup of the Mediatek CMDQ driver and some related bits
- Kconfig changes for riscv drivers to prepare for adding Kanaan k230
support
- Multiple minor updates for the TI sysc bus driver, memory
controllers, hisilicon hccs and more"
* tag 'soc-drivers-6.10' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (103 commits)
firmware: qcom: uefisecapp: Allow on sc8180x Primus and Flex 5G
soc: qcom: pmic_glink: Make client-lock non-sleeping
dt-bindings: soc: qcom,wcnss: fix bluetooth address example
soc/tegra: pmc: Add EQOS wake event for Tegra194 and Tegra234
bus: stm32_firewall: fix off by one in stm32_firewall_get_firewall()
bus: etzpc: introduce ETZPC firewall controller driver
firmware: arm_ffa: Avoid queuing work when running on the worker queue
bus: ti-sysc: Drop legacy idle quirk handling
bus: ti-sysc: Drop legacy quirk handling for smartreflex
bus: ti-sysc: Drop legacy quirk handling for uarts
bus: ti-sysc: Add a description and copyrights
bus: ti-sysc: Move check for no-reset-on-init
soc: hisilicon: kunpeng_hccs: replace MAILBOX dependency with PCC
soc: hisilicon: kunpeng_hccs: Add the check for obtaining complete port attribute
firmware: arm_ffa: Fix memory corruption in ffa_msg_send2()
bus: rifsc: introduce RIFSC firewall controller driver
of: property: fw_devlink: Add support for "access-controller"
soc: mediatek: mtk-socinfo: Correct the marketing name for MT8188GV
soc: mediatek: mtk-socinfo: Add entry for MT8395AV/ZA Genio 1200
soc: mediatek: mtk-mutex: Add support for MT8188 VPPSYS
...
|
|
Report an error when an attempt to register a clkdev entry results in a
truncated string so the problem can be easily spotted.
Reported by: Duanqiang Wen <duanqiangwen@net-swift.com>
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
|
|
The clk_alpha_pll_stromer_set_rate() function writes inproper
values into the ALPHA_VAL{,_U} registers which results in wrong
clock rates when the alpha value is used.
The broken behaviour can be seen on IPQ5018 for example, when
dynamic scaling sets the CPU frequency to 800000 KHz. In this
case the CPU cores are running only at 792031 KHz:
# cat /sys/devices/system/cpu/cpu0/cpufreq/scaling_cur_freq
800000
# cat /sys/devices/system/cpu/cpu0/cpufreq/cpuinfo_cur_freq
792031
This happens because the function ignores the fact that the alpha
value calculated by the alpha_pll_round_rate() function is only
32 bits wide which must be extended to 40 bits if it is used on
a hardware which supports 40 bits wide values.
Extend the clk_alpha_pll_stromer_set_rate() function to convert
the alpha value to 40 bits before wrinting that into the registers
in order to ensure that the hardware really uses the requested rate.
After the change the CPU frequency is correct:
# cat /sys/devices/system/cpu/cpu0/cpufreq/scaling_cur_freq
800000
# cat /sys/devices/system/cpu/cpu0/cpufreq/cpuinfo_cur_freq
800000
Cc: stable@vger.kernel.org
Fixes: e47a4f55f240 ("clk: qcom: clk-alpha-pll: Add support for Stromer PLLs")
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Gabor Juhos <j4g8y7@gmail.com>
Link: https://lore.kernel.org/r/20240328-alpha-pll-fix-stromer-set-rate-v3-1-1b79714c78bc@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
|
|
According to ipq5018.dtsi, the maximum supported rate by the
CPU is 1.008 GHz on the IPQ5018 platform, however the current
configuration of the PLL results in 1.2 GHz rate.
Change the 'L' value in the PLL configuration to limit the
rate to 1.008 GHz. The downstream kernel also uses the same
value [1]. Also add a comment to indicate the desired
frequency.
[1] https://git.codelinaro.org/clo/qsdk/oss/kernel/linux-ipq-5.4/-/blob/NHSS.QSDK.12.4/drivers/clk/qcom/apss-ipq5018.c?ref_type=heads#L151
Fixes: 50492f929486 ("clk: qcom: apss-ipq-pll: add support for IPQ5018")
Signed-off-by: Gabor Juhos <j4g8y7@gmail.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20240326-fix-ipq5018-apss-pll-rate-v1-1-82ab31c9da7e@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
|
|
CONFIG_SM_GCC_8650 depends on ARM64 but it is selected by
CONFIG_SM_GPUCC_8650, which can be selected on ARM, resulting in a
Kconfig warning.
WARNING: unmet direct dependencies detected for SM_GCC_8650
Depends on [n]: COMMON_CLK [=y] && COMMON_CLK_QCOM [=y] && (ARM64 || COMPILE_TEST [=n])
Selected by [y]:
- SM_GPUCC_8650 [=y] && COMMON_CLK [=y] && COMMON_CLK_QCOM [=y]
Add the same dependencies to CONFIG_SM_GPUCC_8650 to resolve the
warning.
Fixes: 8676fd4f3874 ("clk: qcom: add the SM8650 GPU Clock Controller driver")
Signed-off-by: Nathan Chancellor <nathan@kernel.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20240318-fix-some-qcom-kconfig-deps-v1-2-ea0773e3df5a@kernel.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
|
|
CONFIG_SC_GCC_8280XP depends on ARM64 but it is selected by
CONFIG_SC_CAMCC_8280XP, which can be selected on ARM, resulting in a
Kconfig warning.
WARNING: unmet direct dependencies detected for SC_GCC_8280XP
Depends on [n]: COMMON_CLK [=y] && COMMON_CLK_QCOM [=y] && (ARM64 || COMPILE_TEST [=n])
Selected by [y]:
- SC_CAMCC_8280XP [=y] && COMMON_CLK [=y] && COMMON_CLK_QCOM [=y]
Add the same dependencies to CONFIG_SC_CAMCC_8280XP to resolve the
warning.
Fixes: ff93872a9c61 ("clk: qcom: camcc-sc8280xp: Add sc8280xp CAMCC")
Signed-off-by: Nathan Chancellor <nathan@kernel.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20240318-fix-some-qcom-kconfig-deps-v1-1-ea0773e3df5a@kernel.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
|
|
Stephen and Philipp, while reviewing patches, said that all of the aux
device creation and the register read/write code could be moved to the
reset subsystem, leaving the clock driver with no implementations of
reset_* functions at all. Move them.
Suggested-by: Philipp Zabel <p.zabel@pengutronix.de>
Suggested-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20240424-strangle-sharpener-34755c5e6e3e@spud
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
|
|
Drop static const arrays with HSI2 clocks parent data which are not
referenced by any clock. This might cause -Werror=unused-const-variable
warnings.
Reported-by: Stephen Boyd <sboyd@kernel.org>
Closes: https://lore.kernel.org/all/8bf65df598680f0785c3d6db70acfb9a.sboyd@kernel.org/
Fixes: 093c290084a4 ("clk: samsung: gs101: add support for cmu_hsi2")
Reviewed-by: Peter Griffin <peter.griffin@linaro.org>
Link: https://lore.kernel.org/r/20240507055948.34554-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
|
|
This rate allows to provide a low-jitter 72,4 MHz pixelclock
for a custom eDP panel from the VPLL.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Link: https://lore.kernel.org/r/20240503153329.3906030-1-l.stach@pengutronix.de
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
|
In "struct rockchip_mmc_clock", the 'id' field is unused.
Remove it.
Found with cppcheck, unusedStructMember.
Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
Link: https://lore.kernel.org/r/410bc0f86c7b9f1c80f8a4e9a2a028a9a6ee1ec0.1713970085.git.christophe.jaillet@wanadoo.fr
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
|
Add MODULE_DEVICE_TABLE(), so modules could be properly autoloaded
based on the alias from of_device_id table. Clocks are considered core
components, so usually they are built-in, however these can be built and
used as modules on some generic kernel.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Link: https://lore.kernel.org/r/20240410155406.224128-1-krzk@kernel.org
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
|
|
The system hangs when any of these clocks are turned off.
With the introduction of pinctrl clock support [1], the approach taken
in this clock driver for the APM clocks to rely solely on the
clk_ignore_unused kernel command line option does not work anymore and
the system hangs during boot.
gout_apm_func is a parent clock to the clocks that are going to be
handled by the pinctrl driver [2], namely
gout_apm_apbif_gpio_alive_pclk and gout_apm_apbif_gpio_far_alive_pclk.
It also is the parent to the clocks marked as critical in this commit
here (and some others that aren't relevant for this commit)). This
means that once the pinctrl driver decides to turn off clocks, the
clock framework will subsequently turn off parent clocks of those
pinctrl clocks if they have no (apparent) user. Since gout_apm_func is
the parent, and since no drivers are hooked up to it or any of its
other children, gout_apm_func will be turned off. This will cause the
system to hang, as the clocks marked as critical in this commit stop
having an input.
We might have to add a driver for these clocks, but in the meantime
let's just ensure they stay on even if siblings are turned off.
For the avoidance of doubt: This commit doesn't mean that we can boot
without clk_ignore_unused.
Link: https://lore.kernel.org/r/20240426-samsung-pinctrl-busclock-v3-0-adb8664b8a7e@linaro.org [1]
Link: https://lore.kernel.org/r/20240429-samsung-pinctrl-busclock-dts-v1-0-5e935179f3ca@linaro.org [2]
Signed-off-by: André Draszik <andre.draszik@linaro.org>
Reviewed-by: Tudor Ambarus <tudor.ambarus@linaro.org>
Link: https://lore.kernel.org/r/20240430-gs101-apm-clocks-v1-1-b2e2335e84f5@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
|
|
The .remove() callback for a platform driver returns an int which makes
many driver authors wrongly assume it's possible to do error handling by
returning an error code. However the value returned is ignored (apart
from emitting a warning) and this typically results in resource leaks.
To improve here there is a quest to make the remove callback return
void. In the first step of this quest all drivers are converted to
.remove_new(), which already returns void. Eventually after all drivers
are converted, .remove_new() will be renamed to .remove().
Trivially convert this driver from always returning zero in the remove
callback to the void returning variant.
Fixes: 1496dd413b2e ("clk: imx: imx8mp: Add pm_runtime support for power saving")
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Reviewed-by: Abel Vesa <abel.vesa@linaro.org>
Link: https://lore.kernel.org/r/20240423071232.463201-2-u.kleine-koenig@pengutronix.de
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
|
|
Replace SET_RUNTIME_PM_OPS() with its modern alternative RUNTIME_PM_OPS().
The combined usage of pm_ptr() and RUNTIME_PM_OPS() allows the
compiler to evaluate if the suspend/resume() functions are used at
buid time or are simply dead code.
This fixes the following s390 allmodconfig build errors:
drivers/clk/imx/clk-imx8mp-audiomix.c:363:12: error:
'clk_imx8mp_audiomix_runtime_resume' defined but not used
[-Werror=unused-function]
363 | static int clk_imx8mp_audiomix_runtime_resume(struct device *dev)
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/clk/imx/clk-imx8mp-audiomix.c:356:12: error:
'clk_imx8mp_audiomix_runtime_suspend' defined but not used
[-Werror=unused-function]
356 | static int clk_imx8mp_audiomix_runtime_suspend(struct device *dev)
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
cc1: all warnings being treated as errors
Reported-by: Naresh Kamboju <naresh.kamboju@linaro.org>
Closes: https://lore.kernel.org/linux-clk/CA+G9fYuP7S+a89Ep5g5_Ad69EMwRkJ8nM+MMTzbEcP+6H2oMXQ@mail.gmail.com/T/#u
Fixes: 1496dd413b2e ("clk: imx: imx8mp: Add pm_runtime support for power saving")
Signed-off-by: Fabio Estevam <festevam@denx.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Link: https://lore.kernel.org/r/20240429214502.1363592-1-festevam@gmail.com
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
|
|
device_get_match_data() function should not be used on the device other
than the one matched to the given driver, because it always returns the
match_data of the matched driver. In case of exynos-clkout driver, the
original code matches the OF IDs on the PARENT device, so replacing it
with of_device_get_match_data() broke the driver.
This has been already pointed once in commit 2bc5febd05ab ("clk: samsung:
Revert "clk: samsung: exynos-clkout: Use of_device_get_match_data()"").
To avoid further confusion, add a comment about this special case, which
requires direct of_match_device() call to pass custom IDs array.
This partially reverts commit 409c39ec92a35e3708f5b5798c78eae78512cd71.
Cc: <stable@vger.kernel.org>
Fixes: 409c39ec92a3 ("clk: Use device_get_match_data()")
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Link: https://lore.kernel.org/r/20240425075628.838497-1-m.szyprowski@samsung.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20240430184656.357805-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
|
|
Commit f316cdff8d67 ("clk: Annotate struct clk_hw_onecell_data with
__counted_by") annotated the hws member of 'struct clk_hw_onecell_data'
with __counted_by, which informs the bounds sanitizer about the number
of elements in hws, so that it can warn when hws is accessed out of
bounds. As noted in that change, the __counted_by member must be
initialized with the number of elements before the first array access
happens, otherwise there will be a warning from each access prior to the
initialization because the number of elements is zero. This occurs in
raspberrypi_discover_clocks() due to ->num being assigned after ->hws
has been accessed:
UBSAN: array-index-out-of-bounds in drivers/clk/bcm/clk-raspberrypi.c:374:4
index 3 is out of range for type 'struct clk_hw *[] __counted_by(num)' (aka 'struct clk_hw *[]')
Move the ->num initialization to before the first access of ->hws, which
clears up the warning.
Cc: stable@vger.kernel.org
Fixes: f316cdff8d67 ("clk: Annotate struct clk_hw_onecell_data with __counted_by")
Signed-off-by: Nathan Chancellor <nathan@kernel.org>
Link: https://lore.kernel.org/r/20240425-cbl-bcm-assign-counted-by-val-before-access-v1-2-e2db3b82d5ef@kernel.org
Reviewed-by: Kees Cook <keescook@chromium.org>
Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
|
|
Commit f316cdff8d67 ("clk: Annotate struct clk_hw_onecell_data with
__counted_by") annotated the hws member of 'struct clk_hw_onecell_data'
with __counted_by, which informs the bounds sanitizer about the number
of elements in hws, so that it can warn when hws is accessed out of
bounds. As noted in that change, the __counted_by member must be
initialized with the number of elements before the first array access
happens, otherwise there will be a warning from each access prior to the
initialization because the number of elements is zero. This occurs in
clk_dvp_probe() due to ->num being assigned after ->hws has been
accessed:
UBSAN: array-index-out-of-bounds in drivers/clk/bcm/clk-bcm2711-dvp.c:59:2
index 0 is out of range for type 'struct clk_hw *[] __counted_by(num)' (aka 'struct clk_hw *[]')
Move the ->num initialization to before the first access of ->hws, which
clears up the warning.
Cc: stable@vger.kernel.org
Fixes: f316cdff8d67 ("clk: Annotate struct clk_hw_onecell_data with __counted_by")
Signed-off-by: Nathan Chancellor <nathan@kernel.org>
Link: https://lore.kernel.org/r/20240425-cbl-bcm-assign-counted-by-val-before-access-v1-1-e2db3b82d5ef@kernel.org
Reviewed-by: Kees Cook <keescook@chromium.org>
Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
|
|
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas
Pull more Renesas clk driver updates from Geert Uytterhoeven:
- Miscellaneous fixes and improvements
- Add SPI (MSIOF) and external interrupt (INTC-EX) clocks on R-Car V4M
- Add interrupt controller (PLIC) clock and reset on RZ/Five
- Prepare power domain support for RZ/G2L family members, and add
actual support on RZ/G3S SoC
* tag 'renesas-clk-for-v6.10-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
clk: renesas: r9a08g045: Add support for power domains
clk: renesas: rzg2l: Extend power domain support
dt-bindings: clock: renesas,rzg2l-cpg: Update #power-domain-cells = <1> for RZ/G3S
dt-bindings: clock: r9a08g045-cpg: Add power domain IDs
dt-bindings: clock: r9a07g054-cpg: Add power domain IDs
dt-bindings: clock: r9a07g044-cpg: Add power domain IDs
dt-bindings: clock: r9a07g043-cpg: Add power domain IDs
clk: renesas: shmobile: Remove unused CLK_ENABLE_ON_INIT
clk: renesas: r8a7740: Remove unused div4_clk.flags field
clk: renesas: r9a07g043: Add clock and reset entry for PLIC
clk: renesas: r8a779h0: Add INTC-EX clock
clk: renesas: r8a779h0: Add MSIOF clocks
clk: renesas: r8a779a0: Fix CANFD parent clock
|
|
https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-fixes
Pull Allwinner clk driver fixes from Jernej Skrabec:
- fix H6 CPU rate change via reparenting
- set A64 MIPI PLL min & max rate
* tag 'sunxi-clk-fixes-for-6.9-1' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
clk: sunxi-ng: a64: Set minimum and maximum rate for PLL-MIPI
clk: sunxi-ng: common: Support minimum and maximum rate
clk: sunxi-ng: h6: Reparent CPUX during PLL CPUX rate change
|
|
CMU_HSI2 is the clock management unit used for the hsi2 block.
HSI stands for High Speed Interface and as such it generates
clocks for PCIe, UFS and MMC card.
This patch adds support for the muxes, dividers, and gates in
cmu_hsi2.
The following clocks are marked CLK_IS_CRITICAL as disabling
them results in an immediate system hang.
CLK_GOUT_HSI2_HSI2_CMU_HSI2_PCLK
CLK_GOUT_HSI2_LHM_AXI_P_HSI2_I_CLK
The following clocks are marked CLK_IGNORE_UNUSED as they are
needed for UFS to be functional.
CLK_GOUT_HSI2_SSMT_HSI2_ACLK
CLK_GOUT_HSI2_SSMT_HSI2_PCLK
CLK_GOUT_HSI2_LHS_ACEL_D_HSI2_I_CLK
CLK_GOUT_HSI2_SYSMMU_HSI2_CLK_S2
CLK_GOUT_HSI2_XIU_D_HSI2_ACLK
CLK_GOUT_HSI2_XIU_P_HSI2_ACLK
CLK_GOUT_HSI2_GPIO_HSI2_PCLK is marked CLK_IGNORE_UNUSED until
the exynos pinctrl clock patches land then it can be removed.
Some clocks in this unit have very long names. To help with this
the clock name mangling strategy was updated to include removing
the following sub-strings.
- G4X2_DWC_PCIE_CTL_
- G4X1_DWC_PCIE_CTL_
- PCIE_SUB_CTRL_
- INST_0_
- LN05LPE_
- TM_WRAPPER_
- SF_
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
[AD: resolve merge conflicts]
Signed-off-by: André Draszik <andre.draszik@linaro.org>
Reviewed-by: André Draszik <andre.draszik@linaro.org>
Link: https://lore.kernel.org/r/20240429-hsi0-gs101-v3-3-f233be0a2455@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
|
|
CMU_HSI0 is the clock management unit for one of the high speed
interfaces, which is used (amongst others) for USB
Some notes about the clocks marked as CLK_IGNORE_UNUSED:
* CLK_GOUT_HSI0_PCLK
CLK_GOUT_HSI0_LHM_AXI_P_HSI0_I_CLK
CLK_GOUT_HSI0_XIU_P_HSI0_ACLK need to be kept running as
otherwise the system becomes unresponsive and it doesn't complete
booting.
* CLK_GOUT_HSI0_LHS_ACEL_D_HSI0_I_CLK
CLK_GOUT_HSI0_SSMT_USB_ACLK
CLK_GOUT_HSI0_SSMT_USB_PCLK
CLK_GOUT_HSI0_SYSMMU_USB_CLK_S2
CLK_GOUT_HSI0_XIU_D0_HSI0_ACLK
CLK_GOUT_HSI0_XIU_D1_HSI0_ACLK are needed for USB to come up
properly (SSMT is for (secure) memory tagging).
While at the moment we only support booting with the clk_ignore_unused
kernel command line paramenter, it's still worthwhile to explicitly
mark those clocks.
While the usual (sed) script has been used to derive the linux clock
names from the data sheet, one manual tweak was applied to fix a typo
coming from the data sheet which we don't want to carry:
hsi0_uspdpdbg_user -> hsi0_usbdpdbg_user (note usb vs usp).
Signed-off-by: André Draszik <andre.draszik@linaro.org>
Link: https://lore.kernel.org/r/20240426-hsi0-gs101-v2-4-2157da8b63e3@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
|
|
Right now, msm8998 video decoder (venus) is non-functional:
$ time mpv --hwdec=v4l2m2m-copy --vd-lavc-software-fallback=no --vo=null --no-audio --untimed --length=30 --quiet demo-480.webm
(+) Video --vid=1 (*) (vp9 854x480 29.970fps)
Audio --aid=1 --alang=eng (*) (opus 2ch 48000Hz)
[ffmpeg/video] vp9_v4l2m2m: output VIDIOC_REQBUFS failed: Connection timed out
[ffmpeg/video] vp9_v4l2m2m: no v4l2 output context's buffers
[ffmpeg/video] vp9_v4l2m2m: can't configure decoder
Could not open codec.
Software decoding fallback is disabled.
Exiting... (Quit)
Bryan O'Donoghue suggested the proper fix:
- Set required register offsets in venus GDSC structs.
- Set HW_CTRL flag.
$ time mpv --hwdec=v4l2m2m-copy --vd-lavc-software-fallback=no --vo=null --no-audio --untimed --length=30 --quiet demo-480.webm
(+) Video --vid=1 (*) (vp9 854x480 29.970fps)
Audio --aid=1 --alang=eng (*) (opus 2ch 48000Hz)
[ffmpeg/video] vp9_v4l2m2m: VIDIOC_G_FMT ioctl
[ffmpeg/video] vp9_v4l2m2m: VIDIOC_G_FMT ioctl
...
Using hardware decoding (v4l2m2m-copy).
VO: [null] 854x480 nv12
Exiting... (End of file)
real 0m3.315s
user 0m1.277s
sys 0m0.453s
NOTES:
GDSC = Globally Distributed Switch Controller
Use same code as mmcc-msm8996 with:
s/venus_gdsc/video_top_gdsc/
s/venus_core0_gdsc/video_subcore0_gdsc/
s/venus_core1_gdsc/video_subcore1_gdsc/
https://git.codelinaro.org/clo/la/kernel/msm-4.4/-/blob/caf_migration/kernel.lnx.4.4.r38-rel/include/dt-bindings/clock/msm-clocks-hwio-8996.h
https://git.codelinaro.org/clo/la/kernel/msm-4.4/-/blob/caf_migration/kernel.lnx.4.4.r38-rel/include/dt-bindings/clock/msm-clocks-hwio-8998.h
0x1024 = MMSS_VIDEO GDSCR (undocumented)
0x1028 = MMSS_VIDEO_CORE_CBCR
0x1030 = MMSS_VIDEO_AHB_CBCR
0x1034 = MMSS_VIDEO_AXI_CBCR
0x1038 = MMSS_VIDEO_MAXI_CBCR
0x1040 = MMSS_VIDEO_SUBCORE0 GDSCR (undocumented)
0x1044 = MMSS_VIDEO_SUBCORE1 GDSCR (undocumented)
0x1048 = MMSS_VIDEO_SUBCORE0_CBCR
0x104c = MMSS_VIDEO_SUBCORE1_CBCR
Fixes: d14b15b5931c2b ("clk: qcom: Add MSM8998 Multimedia Clock Controller (MMCC) driver")
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Marc Gonzalez <mgonzalez@freebox.fr>
Reviewed-by: Jeffrey Hugo <quic_jhugo@quicinc.com>
Link: https://lore.kernel.org/r/ff4e2e34-a677-4c39-8c29-83655c5512ae@freebox.fr
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
|
|
On SM8650 DisplayPort link clocks use frequency tables inherited from
the vendor kernel, it is not applicable in the upstream kernel. Drop
frequency tables and use clk_byte2_ops for those clocks.
This fixes frequency selection in the OPP core (which otherwise attempts
to use invalid 810 KHz as DP link rate), also fixing the following
message:
msm-dp-display af54000.displayport-controller: _opp_config_clk_single: failed to set clock rate: -22
Fixes: 9e939f008338 ("clk: qcom: add the SM8650 Display Clock Controller driver")
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8650-HDK
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20240424-dispcc-dp-clocks-v2-4-b44038f3fa96@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
|
|
On SM8550 DisplayPort link clocks use frequency tables inherited from
the vendor kernel, it is not applicable in the upstream kernel. Drop
frequency tables and use clk_byte2_ops for those clocks.
This fixes frequency selection in the OPP core (which otherwise attempts
to use invalid 810 KHz as DP link rate), also fixing the following
message:
msm-dp-display ae90000.displayport-controller: _opp_config_clk_single: failed to set clock rate: -22
Fixes: 90114ca11476 ("clk: qcom: add SM8550 DISPCC driver")
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-HDK
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20240424-dispcc-dp-clocks-v2-3-b44038f3fa96@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
|
|
On SM6350 DisplayPort link clocks use frequency tables inherited from
the vendor kernel, it is not applicable in the upstream kernel. Drop
frequency tables and use clk_byte2_ops for those clocks.
This fixes frequency selection in the OPP core (which otherwise attempts
to use invalid 810 KHz as DP link rate), also fixing the following
message:
msm-dp-display ae90000.displayport-controller: _opp_config_clk_single: failed to set clock rate: -22
Fixes: 837519775f1d ("clk: qcom: Add display clock controller driver for SM6350")
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Tested-by: Luca Weiss <luca.weiss@fairphone.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20240424-dispcc-dp-clocks-v2-2-b44038f3fa96@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
|
|
On SM8450 DisplayPort link clocks use frequency tables inherited from
the vendor kernel, it is not applicable in the upstream kernel. Drop
frequency tables and use clk_byte2_ops for those clocks.
This fixes frequency selection in the OPP core (which otherwise attempts
to use invalid 810 KHz as DP link rate), also fixing the following
message:
msm-dp-display ae90000.displayport-controller: _opp_config_clk_single: failed to set clock rate: -22
Fixes: 16fb89f92ec4 ("clk: qcom: Add support for Display Clock Controller on SM8450")
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20240424-dispcc-dp-clocks-v2-1-b44038f3fa96@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
|
|
The register map used for 'cbf_pll' is the same as the one defined for
the CLK_ALPHA_PLL_TYPE_HUAYRA_APSS indice in the 'clk_alpha_pll_regs'
array.
Drop the local register map and use the global one instead to reduce
code duplication.
No functional changes intended. Compile tested only.
Suggested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Gabor Juhos <j4g8y7@gmail.com>
Link: https://lore.kernel.org/r/20240328-apss-ipq-pll-cleanup-v4-5-eddbf617f0c8@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
|
|
The clk_init_data structures are never modified, so add const
qualifier to the ones where it is missing.
No functional changes.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Gabor Juhos <j4g8y7@gmail.com>
Link: https://lore.kernel.org/r/20240328-apss-ipq-pll-cleanup-v4-4-eddbf617f0c8@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
|
