index
:
starfive-tech/linux.git
JH7100_VisionFive_OH_dev
JH7110_VisionFive2_510_devel
JH7110_VisionFive2_6.1.y_devel
JH7110_VisionFive2_6.6.y_devel
JH7110_VisionFive2_devel
JH7110_VisionFive2_upstream
beaglev-5.13.y
beaglev_fedora_devel
buildroot-upstream
esmil_starlight
fedora-vic-7100_5.10.6
master
openwrt-6.1.y
rt-ethercat-release
rt-linux-release
rtthread_AMP
starfive-5.13
starfive-5.15-dubhe
starfive-6.1-dubhe
starfive-6.1.65-dubhe
starfive-6.6.10-dubhe
starfive-6.6.31-dubhe
starlight-5.14.y
visionfive
visionfive-5.13.y-devel
visionfive-5.15.y
visionfive-5.15.y-devel
visionfive-5.15.y_fedora_devel
visionfive-5.16.y
visionfive-5.17.y
visionfive-5.18.y
visionfive-5.19.y
visionfive-6.4.y
visionfive_fedora_devel
StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)
Andrey V.Kosteltsev
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
drivers
/
clocksource
/
timer-riscv.c
Age
Commit message (
Expand
)
Author
Files
Lines
2022-08-12
RISC-V: Add Sstc extension support
Palmer Dabbelt
1
-1
/
+24
2022-08-12
RISC-V: Prefer sstc extension if available
Atish Patra
1
-1
/
+24
2022-07-20
riscv: cpu: Add 64bit hartid support on RV64
Sunil V L
1
-7
/
+8
2022-05-18
clocksource/drivers/riscv: Events are stopped during CPU suspend
Samuel Holland
1
-1
/
+1
2021-10-04
RISC-V: KVM: Add timer functionality
Atish Patra
1
-0
/
+9
2020-08-20
RISC-V: Remove CLINT related code from timer and arch
Anup Patel
1
-15
/
+2
2020-06-10
clocksource/drivers/timer-riscv: Use per-CPU timer interrupt
Anup Patel
1
-3
/
+40
2020-01-05
clocksource: riscv: add notrace to riscv_sched_clock
Zong Li
1
-1
/
+1
2019-11-14
riscv: add support for MMIO access to the timer registers
Christoph Hellwig
1
-4
/
+19
2019-11-05
riscv: abstract out CSR names for supervisor vs machine mode
Christoph Hellwig
1
-4
/
+4
2019-09-05
riscv: don't use the rdtime(h) pseudo-instructions
Christoph Hellwig
1
-13
/
+4
2019-08-07
RISC-V: Remove per cpu clocksource
Atish Patra
1
-4
/
+2
2019-03-23
clocksource/drivers/riscv: Fix clocksource mask
Atish Patra
1
-3
/
+2
2019-02-23
clocksource/drivers/riscv: Add required checks during clock source init
Atish Patra
1
-3
/
+20
2018-12-19
clocksource/drivers/riscv: Change name riscv_timer to timer-riscv
Daniel Lezcano
1
-0
/
+118