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path: root/drivers/clocksource/timer-sun5i.c
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2014-04-22clocksource: sun5i: Add support for reset controllerMaxime Ripard1-0/+6
The Allwinner A31 that uses this timer has the timer IP asserted in reset. Add an optional reset property to the DT, and deassert the timer from reset if it's there. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2014-01-19clocksource: Timer-sun5i: Switch to sched_clock_register()Stephen Boyd1-2/+2
The 32-bit sched_clock() interface supports 64 bits since 3.13-rc1. Upgrade to the 64-bit function to allow us to remove the 32-bit registration interface. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: Maxime Ripard <maxime.ripard@free-electrons.com> Cc: linux-arm-kernel@lists.infradead.org Link: http://lkml.kernel.org/r/1389922686-6249-1-git-send-email-sboyd@codeaurora.org Signed-off-by: Ingo Molnar <mingo@kernel.org>
2013-12-11clocksource: Add Allwinner SoCs HS timers driverMaxime Ripard1-0/+192
Most of the Allwinner SoCs (at this time, all but the A10) also have a High Speed timers that are not using the 24MHz oscillator as a source but rather the AHB clock running much faster. The IP is slightly different between the A10s/A13 and the one used in the A20/A31, since the latter have 4 timers available, while the former have only 2 of them. [dlezcano] : Fixed conflict with b788beda "Order Kconfig options alphabetically" Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Tested-by: Emilio López <emilio@elopez.com.ar> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>