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path: root/drivers/counter/rz-mtu3-cnt.c
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2023-08-16counter: rz-mtu3-cnt: Reorder locking sequence for consistencyBiju Das1-2/+2
All functions except rz_mtu3_count_enable_write(), call pm_runtime_{get,put} inside the lock. For consistency do the same here. Reported-by: Pavel Machek <pavel@denx.de> Closes: https://lore.kernel.org/r/ZH8Fmom8vZ4DwxqA@duo.ucw.cz Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230725154611.227556-1-biju.das.jz@bp.renesas.com/ Signed-off-by: William Breathitt Gray <william.gray@linaro.org>
2023-04-26counter: rz-mtu3-cnt: Unlock on error in rz_mtu3_count_ceiling_write()Dan Carpenter1-2/+6
These error paths need to call mutex_unlock(&priv->lock) before returning. The lock is taken in rz_mtu3_lock_if_counter_is_valid(). Fixes: 25d21447d896 ("counter: Add Renesas RZ/G2L MTU3a counter driver") Signed-off-by: Dan Carpenter <dan.carpenter@linaro.org> Acked-by: William Breathitt Gray <william.gray@linaro.org> Signed-off-by: Lee Jones <lee@kernel.org> Link: https://lore.kernel.org/r/7b535d6b-6031-493a-84f6-82842089e637@kili.mountain
2023-04-26counter: Add Renesas RZ/G2L MTU3a counter driverBiju Das1-0/+902
Add RZ/G2L MTU3a counter driver. This IP supports the following phase counting modes on MTU1 and MTU2 channels 1) 16-bit phase counting modes on MTU1 and MTU2 channels. 2) 32-bit phase counting mode by cascading MTU1 and MTU2 channels. This patch adds 3 counter value channels. count0: 16-bit phase counter value channel on MTU1 count1: 16-bit phase counter value channel on MTU2 count2: 32-bit phase counter value channel by cascading MTU1 and MTU2 channels. The external input phase clock pin for the counter value channels are as follows: count0: "MTCLKA-MTCLKB" count1: "MTCLKA-MTCLKB" or "MTCLKC-MTCLKD" count2: "MTCLKA-MTCLKB" or "MTCLKC-MTCLKD" Use the sysfs variable "external_input_phase_clock_select" to select the external input phase clock pin and "cascade_counts_enable" to enable/ disable cascading of channels. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: William Breathitt Gray <william.gray@linaro.org> Acked-by: William Breathitt Gray <william.gray@linaro.org> Signed-off-by: Lee Jones <lee@kernel.org> Link: https://lore.kernel.org/r/20230330111632.169434-5-biju.das.jz@bp.renesas.com