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path: root/drivers/cxl/cxl.h
AgeCommit message (Expand)AuthorFilesLines
2024-06-26cxl/region: check interleave capabilityYao Xingtao1-0/+2
2024-06-19cxl/mem: Fix no cxl_nvd during pmem region auto-assemblingLi Ming1-2/+2
2024-05-21Merge tag 'pci-v6.10-changes' of git://git.kernel.org/pub/scm/linux/kernel/gi...Linus Torvalds1-0/+2
2024-05-08cxl: Add post-reset warning if reset results in loss of previously committed ...Dave Jiang1-0/+2
2024-05-01cxl/acpi: Cleanup __cxl_parse_cfmws()Dan Williams1-0/+5
2024-04-30cxl: Fix compile warning for cxl_security_ops externDave Jiang1-0/+2
2024-04-08cxl: Consolidate dport access_coordinate ->hb_coord and ->sw_coord into ->coordDave Jiang1-4/+2
2024-04-08cxl: Fix incorrect region perf data calculationDave Jiang1-2/+0
2024-03-12cxl/region: Add memory hotplug notifier for cxl regionDave Jiang1-0/+3
2024-03-12cxl/region: Calculate performance data for a regionDave Jiang1-0/+4
2024-03-12cxl: Split out host bridge access coordinatesDave Jiang1-0/+2
2024-03-12cxl: Split out combine_coordinates() for common shared usageDave Jiang1-0/+4
2024-03-12ACPI: HMAT / cxl: Add retrieval of generic port coordinates for both access c...Dave Jiang1-1/+1
2024-02-17cxl: Fix sysfs export of qos_class for memdevDave Jiang1-0/+2
2024-01-06Merge branch 'for-6.7/cxl' into for-6.8/cxlDan Williams1-2/+0
2024-01-06cxl: Convert find_cxl_root() to return a 'struct cxl_root *'Dave Jiang1-7/+7
2024-01-06cxl: Introduce put_cxl_root() helperDave Jiang1-0/+3
2024-01-05cxl/port: Fix missing target list lockDan Williams1-2/+0
2023-12-23cxl: Add helper function that calculate performance data for downstream portsDave Jiang1-0/+3
2023-12-23cxl: Store the access coordinates for the generic portsDave Jiang1-0/+2
2023-12-23cxl: Calculate and store PCI link latency for the downstream portsDave Jiang1-0/+4
2023-12-23cxl: Add support for _DSM Function for retrieving QTG IDDave Jiang1-0/+25
2023-12-23cxl: Add callback to parse the SSLBIS subtable from CDATDave Jiang1-0/+4
2023-12-23cxl: Add callback to parse the DSMAS subtables from CDATDave Jiang1-0/+2
2023-10-31Merge branch 'for-6.7/cxl-commited' into cxl/nextDan Williams1-0/+1
2023-10-31Merge branch 'for-6.7/cxl-qtg' into cxl/nextDan Williams1-0/+3
2023-10-28cxl: Export QTG ids from CFMWS to sysfs as qos_class attributeDave Jiang1-0/+3
2023-10-28cxl: Add cxl_decoders_committed() helperDave Jiang1-0/+1
2023-10-28cxl/core/regs: Rework cxl_map_pmu_regs() to use map->dev for devmRobert Richter1-2/+1
2023-10-28cxl/pci: Map RCH downstream AER registers for logging protocol errorsTerry Bowman1-0/+10
2023-10-28cxl/pci: Add RCH downstream port AER register discoveryRobert Richter1-0/+7
2023-10-28cxl/port: Remove Component Register base address from struct cxl_portRobert Richter1-2/+0
2023-10-28cxl/port: Rename @comp_map to @reg_map in struct cxl_register_mapRobert Richter1-4/+4
2023-10-28cxl/core/regs: Rename @dev to @host in struct cxl_register_mapRobert Richter1-2/+2
2023-06-26Merge branch 'for-6.5/cxl-rch-eh' into for-6.5/cxlDan Williams1-25/+32
2023-06-26Merge branch 'for-6.5/cxl-perf' into for-6.5/cxlDan Williams1-0/+16
2023-06-26Merge branch 'for-6.5/cxl-region-fixes' into for-6.5/cxlDan Williams1-7/+9
2023-06-26Merge branch 'for-6.5/cxl-type-2' into for-6.5/cxlDan Williams1-6/+5
2023-06-26Revert "cxl/port: Enable the HDM decoder capability for switch ports"Dan Williams1-1/+0
2023-06-26cxl/hdm: Default CXL_DEVTYPE_DEVMEM decoders to CXL_DECODER_DEVMEMDan Williams1-1/+1
2023-06-26cxl/port: Rename CXL_DECODER_{EXPANDER, ACCELERATOR} => {HOSTONLYMEM, DEVMEM}Dan Williams1-2/+2
2023-06-26cxl/regs: Clarify when a 'struct cxl_register_map' is input vs outputDan Williams1-2/+2
2023-06-25cxl/region: Flag partially torn down regions as unusableDan Williams1-0/+8
2023-06-25cxl/region: Move cache invalidation before region teardown, and before setupDan Williams1-7/+1
2023-06-25cxl/port: Store the downstream port's Component Register mappings in struct c...Robert Richter1-0/+2
2023-06-25cxl/port: Store the port's Component Register mappings in struct cxl_portRobert Richter1-0/+2
2023-06-25cxl/pci: Early setup RCH dport component registers from RCRBRobert Richter1-0/+2
2023-06-25cxl/port: Remove Component Register base address from struct cxl_dportRobert Richter1-2/+0
2023-06-25cxl/pci: Refactor component register discovery for reuseTerry Bowman1-0/+1
2023-06-25cxl/core/regs: Add @dev to cxl_register_mapRobert Richter1-4/+6
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