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starfive-tech/linux.git
JH7100_VisionFive_OH_dev
JH7110_VisionFive2_510_devel
JH7110_VisionFive2_6.1.y_devel
JH7110_VisionFive2_6.6.y_devel
JH7110_VisionFive2_devel
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fedora-vic-7100_5.10.6
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openwrt-6.1.y
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visionfive-5.18.y
visionfive-5.19.y
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visionfive_fedora_devel
StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)
Andrey V.Kosteltsev
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path:
root
/
drivers
/
cxl
Age
Commit message (
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Author
Files
Lines
2023-10-31
Merge branch 'for-6.7/cxl-rch-eh' into cxl/next
Dan Williams
10
-129
/
+406
2023-10-28
cxl: Add support for reading CXL switch CDAT table
Dave Jiang
2
-5
/
+20
2023-10-28
cxl: Add checksum verification to CDAT from CXL
Dave Jiang
1
-7
/
+23
2023-10-28
cxl: Export QTG ids from CFMWS to sysfs as qos_class attribute
Dave Jiang
3
-0
/
+17
2023-10-28
cxl: Add decoders_committed sysfs attribute to cxl_port
Dave Jiang
1
-0
/
+25
2023-10-28
cxl: Add cxl_decoders_committed() helper
Dave Jiang
5
-6
/
+15
2023-10-28
cxl/core/regs: Rework cxl_map_pmu_regs() to use map->dev for devm
Robert Richter
3
-6
/
+4
2023-10-28
cxl/core/regs: Rename phys_addr in cxl_map_component_regs()
Robert Richter
1
-3
/
+3
2023-10-28
cxl/pci: Disable root port interrupts in RCH mode
Terry Bowman
1
-0
/
+32
2023-10-28
cxl/pci: Add RCH downstream port error logging
Terry Bowman
1
-0
/
+96
2023-10-28
cxl/pci: Map RCH downstream AER registers for logging protocol errors
Terry Bowman
2
-0
/
+46
2023-10-28
cxl/pci: Update CXL error logging to use RAS register address
Terry Bowman
1
-13
/
+31
2023-10-28
PCI/AER: Refactor cper_print_aer() for use by CXL driver module
Terry Bowman
1
-0
/
+1
2023-10-28
cxl/pci: Add RCH downstream port AER register discovery
Robert Richter
5
-0
/
+61
2023-10-28
cxl/port: Remove Component Register base address from struct cxl_port
Robert Richter
2
-5
/
+1
2023-10-28
cxl/pci: Remove Component Register base address from struct cxl_dev_state
Robert Richter
2
-5
/
+0
2023-10-28
cxl/hdm: Use stored Component Register mappings to map HDM decoder capability
Robert Richter
3
-39
/
+43
2023-10-28
cxl/pci: Store the endpoint's Component Register mappings in struct cxl_dev_s...
Robert Richter
3
-4
/
+9
2023-10-28
cxl/port: Pre-initialize component register mappings
Robert Richter
1
-5
/
+7
2023-10-28
cxl/port: Rename @comp_map to @reg_map in struct cxl_register_map
Robert Richter
2
-7
/
+7
2023-10-28
cxl/port: Fix @host confusion in cxl_dport_setup_regs()
Dan Williams
1
-12
/
+31
2023-10-28
cxl/core/regs: Rename @dev to @host in struct cxl_register_map
Robert Richter
5
-20
/
+20
2023-10-28
cxl/port: Fix delete_endpoint() vs parent unregistration race
Dan Williams
1
-15
/
+19
2023-10-27
cxl/region: Fix x1 root-decoder granularity calculations
Jim Harris
1
-1
/
+8
2023-10-27
cxl/region: Fix cxl_region_rwsem lock held when returning to user space
Li Zhijian
1
-1
/
+1
2023-10-27
cxl/region: Use cxl_calc_interleave_pos() for auto-discovery
Alison Schofield
1
-112
/
+15
2023-10-27
cxl/region: Calculate a target position in a region interleave
Alison Schofield
1
-0
/
+127
2023-10-26
cxl/region: Prepare the decoder match range helper for reuse
Alison Schofield
1
-6
/
+11
2023-10-25
cxl/mbox: Remove useless cast in cxl_mem_create_range_info()
Alison Schofield
1
-2
/
+1
2023-10-25
cxl/region: Do not try to cleanup after cxl_region_setup_targets() fails
Jim Harris
1
-7
/
+7
2023-10-09
cxl/mem: Fix shutdown order
Dan Williams
1
-1
/
+1
2023-10-06
cxl/memdev: Fix sanitize vs decoder setup locking
Dan Williams
8
-49
/
+90
2023-10-06
cxl/pci: Fix sanitize notifier setup
Dan Williams
3
-42
/
+50
2023-10-06
cxl/pci: Clarify devm host for memdev relative setup
Dan Williams
3
-12
/
+13
2023-10-06
cxl/pci: Remove inconsistent usage of dev_err_probe()
Dan Williams
1
-11
/
+2
2023-10-06
cxl/pci: Remove hardirq handler for cxl_request_irq()
Dan Williams
1
-6
/
+6
2023-09-30
cxl/pci: Cleanup 'sanitize' to always poll
Dan Williams
3
-39
/
+26
2023-09-30
cxl/pci: Remove unnecessary device reference management in sanitize work
Dan Williams
1
-5
/
+0
2023-09-23
cxl/acpi: Annotate struct cxl_cxims_data with __counted_by
Kees Cook
1
-2
/
+2
2023-09-23
cxl/port: Fix cxl_test register enumeration regression
Dan Williams
1
-4
/
+9
2023-09-16
cxl/pci: Update comment
Ira Weiny
1
-1
/
+4
2023-09-16
cxl/port: Quiet warning messages from the cxl_test environment
Dan Williams
2
-2
/
+7
2023-09-15
cxl/region: Refactor granularity select in cxl_port_setup_targets()
Alison Schofield
1
-9
/
+8
2023-09-15
cxl/region: Match auto-discovered region decoders by HPA range
Alison Schofield
1
-1
/
+23
2023-09-14
cxl/mbox: Fix CEL logic for poison and security commands
Ira Weiny
1
-11
/
+12
2023-09-12
cxl/pci: Replace host_bridge->native_aer with pcie_aer_is_native()
Smita Koralahalli
1
-2
/
+1
2023-09-12
cxl/pci: Fix appropriate checking for _OSC while handling CXL RAS registers
Smita Koralahalli
1
-3
/
+3
2023-07-28
cxl/memdev: Only show sanitize sysfs files when supported
Davidlohr Bueso
3
-1
/
+78
2023-07-28
cxl/memdev: Document security state in kern-doc
Davidlohr Bueso
1
-0
/
+1
2023-07-18
cxl/acpi: Return 'rc' instead of '0' in cxl_parse_cfmws()
Breno Leitao
1
-1
/
+1
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