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path: root/drivers/gpu/drm/amd/display/dc/dcn321
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2023-11-17drm/amd/display: Refactor resource into component directoryMounika Adhuri3-2111/+1
[WHY] Move all resource files to unique folder resource. [HOW] Created resource folder in dc, moved the dcnxx_resource.c and dcnxx_resource.h files into corresponding new folders inside the resource and made appropriate changes for compilation in Makefiles. Reviewed-by: Martin Leung <martin.leung@amd.com> Acked-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Mounika Adhuri <moadhuri@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-10-27drm/amd/display: add interface to query SubVP statusAurabindo Pillai1-1/+2
[Why&How] To enable automated testing through IGT, expose an API that is accessible through debugfs to query current status of SubVP feature. Reviewed-by: Alvin Lee <alvin.lee2@amd.com> Acked-by: Roman Li <roman.li@amd.com> Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-10-27drm/amd/display: add pipe resource management callbacks to DML2Wenjing Liu1-0/+5
[why] Need DML2 to support new pipe resource management APIs. Reviewed-by: Chaitanya Dhere <chaitanya.dhere@amd.com> Acked-by: Roman Li <roman.li@amd.com> Signed-off-by: Wenjing Liu <wenjing.liu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-10-27drm/amd/display: Set the DML2 attribute to false in all DCNs older than ↵Rodrigo Siqueira1-0/+1
version 3.5 When DML2 was introduced, it targeted only new DCN versions. For controlling which ASIC should use this new version of DML, it was introduced the using_dml2 attribute. To avoid ambiguities, this commit explicitly sets using_dml2 to false in all ASICs that do not support DML2. Cc: Vitaly Prosyak <vprosyak@amd.com> Cc: Roman Li <roman.li@amd.com> Cc: Qingqing Zhuo <Qingqing.Zhuo@amd.com> Cc: Daniel Wheeler <daniel.wheeler@amd.com> Cc: Alex Deucher <Alexander.Deucher@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-10-10drm/amd/display: Refactor HWSS into component folderMounika Adhuri1-1/+1
[why] Rename hw_sequencer to hwseq. Move all hwseq files to unique folder hwss. [how] creating hwss repo in dc, and moved the dcnxx_hwseq.c and .h files into corresponding new folders inside the hwss and cleared the linkage errors by adding relative paths in the Makefile.template. Reviewed-by: Martin Leung <martin.leung@amd.com> Acked-by: Tom Chung <chiahsuan.chung@amd.com> Signed-off-by: Mounika Adhuri <moadhuri@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-10-09drm/amd/display: Introduce DML2Qingqing Zhuo1-0/+41
DC is transitioning from DML to DML2, and this commit introduces all the required changes for some of the already available ASICs and adds the required code infra to support new ASICs under DML2. DML2 is also a generated code that provides better mode verification and programming models for software/hardware, and it enables a better way to create validation tools. This version is more like a middle step to the complete transition to the DML2 version. Changes since V1: - Alex: Fix typos Changes since V2: - Update DC includes Changes since V3: - Fix 32 bit compilation issues on x86 Changes since V4: - Avoid compilation of DML2 on some not supported 32-bit architecture - Update commit message Co-developed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Co-developed-by: Roman Li <roman.li@amd.com> Signed-off-by: Roman Li <roman.li@amd.com> Signed-off-by: Qingqing Zhuo <Qingqing.Zhuo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-09-27drm/amd/display: add missing function pointer for DCN321 resourceWenjing Liu1-0/+1
[why] acquire_free_pipe_as_secondary_opp_head function pointer is not assigned. This causes ODM mode to be disabled after enabling windowed MPO ODM capability on DCN321. [how] assign the correct function to the function pointer. Reviewed-by: Dillon Varone <dillon.varone@amd.com> Acked-by: Wayne Lin <wayne.lin@amd.com> Signed-off-by: Wenjing Liu <wenjing.liu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-08-30drm/amd/display: add more pipe resource interfacesWenjing Liu1-0/+1
Redesign pipe resource interfaces in resource.h file. The new interface design addresses the issue with lack of pipe topology encapsulation and lack of pipe accessors. Reviewed-by: Jun Lei <jun.lei@amd.com> Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by: Wenjing Liu <wenjing.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-08-08drm/amd/display: rename acquire_idle_pipe_for_layer to ↵Wenjing Liu1-1/+1
acquire_free_pipe_as_sec_dpp_pipe [why] Secondary DPP pipes are used for rendering secondary layers of planes. The name "for layer" doesn't make it obvious. The function is acquiring a free pipe as secondary dpp pipe only. We rename it so it is more obvious. In a future follow up change, we want to add functions to acquire free pipe as opp head pipe or otg master pipe as well. They will have their separate allocation priority. Reviewed-by: Jun Lei <jun.lei@amd.com> Acked-by: Tom Chung <chiahsuan.chung@amd.com> Signed-off-by: Wenjing Liu <wenjing.liu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-08-08drm/amd/display: update add plane to context logic with a new algorithmWenjing Liu1-1/+1
[why] Preivous algorithm for finding an optimal idle pipe for a new plane was implemented to handle dynamic pipe allocation when MPO plane moves from one ODM slice to the other. Now pipe allocation is more static so it no longer depends on the MPO plane's position. We are simplifying our logic and remove unnecessary handling in our code. [how] Apply a new simplified version of pipe resource allocation logic to reduce unnecessary flip delay caused by swapping secondary dpp pipe to other MPC blending tree. Reviewed-by: Jun Lei <jun.lei@amd.com> Acked-by: Tom Chung <chiahsuan.chung@amd.com> Signed-off-by: Wenjing Liu <wenjing.liu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-06-23drm/amd/display: Enable dc mode clock switching for DCN32xAlvin Lee1-0/+1
- DC mode clock switch interface was previously only executed for DCN303. Enable it for DCN32x so that the interface is called correctly - Assign function pointers for DCN32x that are used in the dc mode interface - Update the dc mode interface to work generically for each ASIC - In update_clocks, make sure to consider softmax if we're in DC mode Reviewed-by: Jun Lei <jun.lei@amd.com> Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by: Alvin Lee <alvin.lee2@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-06-23drm/amd/display: Disable DC Mode Capping On DCN321Austin Zheng1-0/+1
Why: Limiting clocks to DC mode max results in some display modes to no longer be supported How: Disable the path that limits the clock values Fixes: 3b718dcaf163 ("drm/amd/display: Filter out AC mode frequencies on DC mode systems") Reviewed-by: Martin Leung <martin.leung@amd.com> Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by: Austin Zheng <austin.zheng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-06-23drm/amd/display: enable the new fast update path for supported ASICsAlvin Lee1-0/+1
The new fast update sequence is now supported on some ASICs. So, enable it by default for all applicable ASICs. Reviewed-by: Samson Tam <samson.tam@amd.com> Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by: Alvin Lee <alvin.lee2@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-06-15drm/amd/display: Limit Minimum FreeSync Refresh RateAustin Zheng1-0/+1
Why: Some EDIDs report a minimum refresh rate lower than what HW can support How: Add a check to calculate minimum supported refresh rate with current timing and use that as the minimum if a lower one is passed in Acked-by: Stylon Wang <stylon.wang@amd.com> Signed-off-by: Austin Zheng <austin.zheng@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-06-15drm/amd/display: Re-enable SubVP high refreshAlvin Lee1-1/+1
Re-enable SubVP high refresh now that it is fixed for displays with high refresh rates. Acked-by: Stylon Wang <stylon.wang@amd.com> Signed-off-by: Alvin Lee <alvin.lee2@amd.com> Reviewed-by: Saaem Rizvi <SyedSaaem.Rizvi@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-06-09drm/amd/display: remove unused definitionYang Li1-30/+0
Eliminate the following warnings: drivers/gpu/drm/amd/amdgpu/../display/dc/dcn321/dcn321_resource.c:1346:43: warning: unused variable 'res_create_maximus_funcs' drivers/gpu/drm/amd/amdgpu/../display/dc/dcn321/dcn321_resource.c:735:38: warning: unused variable 'debug_defaults_diags' Reported-by: Abaci Robot <abaci@linux.alibaba.com> Closes: https://bugzilla.openanolis.cn/show_bug.cgi?id=5296 Fixes: 25879d7b4986 ("drm/amd/display: Clean FPGA code in dc") Signed-off-by: Yang Li <yang.lee@linux.alibaba.com> Signed-off-by: Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-06-09drm/amd/display: Clean FPGA code in dcQingqing Zhuo1-9/+4
[Why] Drop dead code for Linux. [How] Remove all IS_FPGA_MAXIMUS_DC and IS_DIAG_DC Reviewed-by: Ariel Bernstein <eric.bernstein@amd.com> Acked-by: Tom Chung <chiahsuan.chung@amd.com> Signed-off-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-06-09drm/amd/display: Update vactive margin and max vblank for fpo + vactiveAlvin Lee1-0/+2
[Description] - Some 1920x1080@60hz displays have VBLANK time > 600us which we still want to accept for FPO + Vactive configs based on testing - Increase max VBLANK time to 1000us to allow these configs for FPO + Vactive - Increase minimum vactive switch margin for FPO + Vactive to 200us - Based on testing, 1920x1080@120hz can have a switch margin of ~160us which requires significantly longer FPO stretch margin (5ms) which we don't want to accept for now - Also move margins into debug option Reviewed-by: Jun Lei <jun.lei@amd.com> Reviewed-by: Nevenko Stupar <nevenko.stupar@amd.com> Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Alvin Lee <alvin.lee2@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-06-09drm/amd/display: filter out invalid bits in pipe_fusesSamson Tam1-1/+9
[Why] Reading pipe_fuses from register may have invalid bits set, which may affect the num_pipes erroneously. [How] Add read_pipes_fuses() call and filter bits based on expected number of pipes. Reviewed-by: Alvin Lee <Alvin.Lee2@amd.com> Acked-by: Alan Liu <HaoPing.Liu@amd.com> Signed-off-by: Samson Tam <Samson.Tam@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-04-25drm/amd/display: Enable SubVP for high refresh rate displaysAlvin Lee1-0/+1
[Description] - Add debug option to enable SubVP for high refresh rate displays - For now limit the enabled modes based on a table in debug options - Currently disabled by default Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-04-21drm/amd/display: 3-plane MPO enablement for DCN321Krunoslav Kovac1-3/+3
Enable 3-planes MPO for DCN321 by reporting max_slave_planes in DC caps for each ASIC. Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-04-18drm/amd/display: Enable FPO + VactiveAlvin Lee1-1/+1
[Description] - Enable FPO + Vactive Reviewed-by: George Shen <George.Shen@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-04-12drm/amd/display: On clock init, maintain DISPCLK freqAlvin Lee1-0/+1
[Description] - On init if a display is connected, we need to maintain the DISPCLK frequency - Even though DPG_EN=1, the display still requires the correct timing or it could cause audio corruption (if DISPCLK freq is reduced) - Read the current DISPCLK freq and request the same value to ensure the timing is valid and unchanged - However, add option to do a full pipe power down (including link) which will also avoid audio related issues - Disabled for the time being on dcn32 Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-04-12drm/amd/display: Add FPO + VActive supportAlvin Lee1-0/+2
[Description] - When determining FPO support, include FPO + VActive support - Support FPO + VActive if one display meets regular requirements for FPO and the second display is able to switch in VACTIVE with a given amount of margin Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-03-31drm/amd/display: Enable FPO optimizationAlvin Lee1-1/+1
[Description] Enable optimization for preferring FPO if it achieves a lower voltage level Reviewed-by: George Shen <George.Shen@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-03-31drm/amd/display: Enable FPO for configs that could reduce vlevelAlvin Lee1-0/+1
[Description] - On high refresh rate DRR displays that support VBLANK naturally, UCLK could be idling at DPM1 instead of DPM0 since it doesn't use FPO - To achieve DPM0, enable FPO on these configs even though it can support P-State without FPO - Default disable for now, have debug option to enable Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-03-14drm/amd/display: convert link.h functions to function pointer styleWenjing Liu1-3/+6
[Why & How] All dc subcomponents should call another dc component via function pointers stored in a component structure. This is part of dc coding convention since the beginning. The reason behind this is to improve encapsulation and polymorphism. The function contract is extracted into a single link service structure defined in link.h header file and implemented only in link_factory.c instead of spreading across multiple files in link component file structure. Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Wenjing Liu <wenjing.liu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-03-08drm/amd/display: remove legacy fields of dc_plane_cap structDavid Tadokoro1-2/+0
The fields blends_with_above and blends_with_below of struct dc_plane_cap (defined in dc/dc.h) are boolean and set to true by default. All instances of a dc_plane_cap maintain the default values of both. Also, there is only one if statement that checks those fields and there would be the same effect if it was deleted (assuming that those fields are always going to be true). For this reason, considering both fields as legacy ones, this commit removes them and the aforementioned if statement. Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: David Tadokoro <davidbtadokoro@usp.br> Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-02-28drm/amd/display: DAL to program DISPCLK WDIVIDER if PMFW doesn'tAlvin Lee1-0/+1
[Why & How] - If for any reason PMFW fails to set the expected (or valid) DISPCLK WDIVIDER, then DAL will program DENTIST DISPCLK WDIVIDER to correct for this issue Reviewed-by: Samson Tam <Samson.Tam@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-01-31drm/amd/display: fix MALL size hardcoded for DCN321Samson Tam1-1/+0
[Why] MALL size available can vary for different SKUs MALL size was still hardcoded for DCN321 [How] Remove hardcoding MALL size for DCN321 Reviewed-by: Alvin Lee <Alvin.Lee2@amd.com> Acked-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Samson Tam <Samson.Tam@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-01-24drm/amd/display: merge dc_link_dp into dc_linkWenjing Liu1-1/+0
[why] Temporarly merge dc_link_dp functions into dc_link for the purpose of removing dc_link_dp files. This is a transitional change for later commits where we will further refactor dc_link file. Reviewed-by: George Shen <George.Shen@amd.com> Acked-by: Alan Liu <HaoPing.Liu@amd.com> Signed-off-by: Wenjing Liu <wenjing.liu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-01-24drm/amd/display: adjust MALL size available for DCN32 and DCN321Samson Tam1-1/+8
[Why] MALL size available can vary for different SKUs. Use num_chans read from VBIOS to determine the available MALL size we can use [How] Define max_chans for DCN32 and DCN321. If num_chans is max_chans, then return max_chans as we can access the entire MALL space. Otherwise, define avail_chans as the number of available channels we are allowed instead. Return corresponding number of channels back and use this to calculate available MALL size. Reviewed-by: Nevenko Stupar <Nevenko.Stupar@amd.com> Acked-by: Alan Liu <HaoPing.Liu@amd.com> Signed-off-by: Samson Tam <Samson.Tam@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-01-13drm/amd/display: refactor ddc logic from dc_link_ddc to link_ddcWenjing Liu2-4/+3
[why] 1. Move dd_link_ddc functions to link_ddc. 2. Move link ddc functions declaration exposed in dc to link.h 3. Move link ddc functions declaration exposed in dm to dc_link.h 4. Remove i2caux_interface.h file Tested-by: Daniel Wheeler <Daniel.Wheeler@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Wenjing Liu <wenjing.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-12-15drm/amd/display: Add debug bit to disable unbounded requestingDillon Varone1-0/+1
[Description] Add debug bit to disable unbounded requesting. Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Jasdeep Dhillon <jdhillon@amd.com> Signed-off-by: Dillon Varone <Dillon.Varone@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-12-06drm/amd/display: Remove DTB DTO on CLK updateChris Park1-1/+1
[Why] DTB DTO is programmed more correctly during link enable. Programming them on CLK update which may arrive frequently and sporadically per flip throws off DTB DTO. [How] Remove DTB DTO programming on clock update. Reviewed-by: Alvin Lee <Alvin.Lee2@amd.com> Acked-by: Jasdeep Dhillon <jdhillon@amd.com> Signed-off-by: Chris Park <Chris.Park@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-11-29drm/amd/display: Retain phantom pipes when min transition into subvp (#7358)Alvin Lee1-0/+2
[Description] - When entering into a SubVP config that requires a minimal transition we need to retain phantom pipes and also restore the mall config - This is because the min transition will remove phantom pipes from the context (shallow copy) and not restore it's original state - This is just a workaround, and needs a proper fix Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Jasdeep Dhillon <jdhillon@amd.com> Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-11-23drm/amd/display: Retain phantom plane/stream if validation failsAlvin Lee1-0/+1
[Description] - If we fail validation, we should retain the phantom stream/planes - Full updates assume that phantom pipes will be fully removed, but if validation fails we keep the phantom pipes - Therefore we have to retain the plane/stream if validation fails (since the refcount is decremented before validation, and the expectation is that it's fully freed when the old dc_state is released) Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Brian Chang <Brian.Chang@amd.com> Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-11-23drm/amd/display: Limit HW cursor size of >= 4kAlvin Lee1-1/+1
[Description] - For SubVP, we cannot support HW cursor if it's greater than 64 x 64 x 4 bytes in size - However, on certain config changes (i.e. pixel format) we can exit SubVP (then change to HW cursor) then re-enter SubVP without changing back to SW cursor because there is no SetCursorAttributes call - To workaround this issue, limit the HW cursor size to be less than 64 x 64 x 4 bytes whenever the stream is >= 4K - Also ensure this W/A only affects DCN that supports SubVP Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Brian Chang <Brian.Chang@amd.com> Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-11-23drm/amd/display: Add margin on DRR vblank start for subvpAlvin Lee1-0/+1
[Description] - Add margin for HUBP "jitter" for SubVp + DRR case - Also do a min transition even if MPO is added on a non SubVP pipe (i.e. added on DRR pipe for SubVP + DRR) Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Brian Chang <Brian.Chang@amd.com> Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-11-15drm/amd/display: rework macros for DWB register accessAurabindo Pillai1-2/+3
[Why] A hack was used to access DWB register due to difference in the register naming convention which was not compatible with existing SR/SRI* macros. The additional macro needed were added to dwb ip specific header file (dcnxx_dwb.h) instead of soc resource file (dcnxx_resource.c). Due to this pattern, BASE macro had to be redefined in dcnxx_dwb.h, which in turn needed us to undefine them in the resource file. [How] Add a separate macro for DWB access to the resource files that need it instead of defining them in DWB ip header file. This will enable us to reuse the BASE macro defined in the resource file. Reviewed-by: Roman Li <Roman.Li@amd.com> Acked-by: Tom Chung <chiahsuan.chung@amd.com> Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-11-10drm/amd/display: Have risk for memory exhaustionLongJun Tang1-0/+1
In dcn*_clock_source_create when dcn*_clk_src_construct fails allocated clk_src needs release. A local attack could use this to cause memory exhaustion. Signed-off-by: LongJun Tang <tanglongjun@kylinos.cn> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-11-10drm/amd/display: Add margin for max vblank time for SubVP + DRRAlvin Lee1-0/+1
[Description] - Incorporate FW delays as port of max VTOTAL calculated for SubVP + DRR cases (since it is part of the microschedule). - Also add margin for the max VTOTAL possible for SubVP + DRR cases. - Due to rounding errors in FW (integer arithmetic), the microschedule calculation can get pushed to the next frame (incorrectly) in cases where we use the max VTOTAL possible to complete the MCLK switch. - When the rounding error occurs, we are only off by 1-2 lines, use 40us margin which is working consistently. Reviewed-by: Jun Lei <Jun.Lei@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Alan Liu <HaoPing.Liu@amd.com> Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-11-10drm/amd/display: Enforce minimum prefetch time for low memclk on DCN32Dillon Varone1-0/+1
[WHY?] Data return times when using lowest memclk can be <= 60us, which can cause underflow on high bandwidth displays with a workload. [HOW?] Enforce a minimum prefetch time during validation for low memclk modes. Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Alan Liu <HaoPing.Liu@amd.com> Signed-off-by: Dillon Varone <Dillon.Varone@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-10-06drm/amd/display: clean up one inconsistent indentingYang Li1-1/+1
clean up one inconsistent indenting Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=2238 Reported-by: Abaci Robot <abaci@linux.alibaba.com> Signed-off-by: Yang Li <yang.lee@linux.alibaba.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-10-06drm/amd/display: Update DCN321 hook that deals with pipe aquireRodrigo Siqueira1-1/+1
DCN provides a hook to check if we can have a new pipe allocation based on some DC constraints. If the current configuration supports the new pipe request, DC updates its context; otherwise, it will keep the same configuration. This behavior is similar across multiple ASICs, and for this reason, we reused DCN20 on DCN321. However, this DCN32x has some peculiarities which require its function to avoid weird pipe split issues. This commit update this issue by using dcn32_acquire_idle_pipe_for_head_pipe_in_layer instead of dcn20_acquire_idle_pipe_for_layer. Reviewed-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-10-06drm/amd/display: Drop unused code for DCN32/321Rodrigo Siqueira2-3/+0
Under DCN32/321 we identified some code paths that DC never executes. This commit removes those unused codes to avoid distractions when debugging issues. Reviewed-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-09-29drm/amd/display: Fix various dynamic ODM transitions on DCN32Dillon Varone1-0/+3
[Why&How] Several transitions were fixed that will allow Dynamic ODM and MPO transitions to be supported on DCN32. 1) Due to resource limitations, in certain scenarios that require an MPO plane to be split, the features cannot be combined with the current policy. This is due to unsafe transitions being required (OPP instance per MPCC being switched on active pipe is not supported by DCN), to support the split plane with ODM active as it moves across the viewport. Dynamic ODM will now be disabled when MPO is required. 2) When exiting MPO and re-entering ODM, DC assigns an inactive pipe for the next ODM pipe, which under previous power gating policy would result in programming a gated DSC HW block. New policy dynamically gates/un-gates DSC blocks when Dynamic ODM is active to support transitions on DCN32 only. 3) Entry and exit from 3 plane MPO and Dynamic ODM requires a minimal transition so that all pipes which require their MPCC OPP instance to be changed have a full frame to be disabled before reprogramming. To solve this, the Dynamic ODM policy now utilizes minimal state transitions when entering or exiting 3 plane scenarios. 4) Various fixes to DCN32 pipe merge/split algorithm to support Dynamic ODM and MPO transitions. In summary, this commit fixes various transitions to support ODM->MPO and MPO->ODM. Reviewed-by: Martin Leung <Martin.Leung@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Jasdeep Dhillon <jdhillon@amd.com> Signed-off-by: Dillon Varone <Dillon.Varone@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-09-19drm/amd/display: Add debug option for allocating extra way for cursorAlvin Lee1-0/+1
[Why and How] - Add a debug option for allocating extra way for cursor - Remove usage of cache_cursor_addr since it's not gaurenteed to be populated - Include cursor size in MALL calculation if it exceeds the DCN cursor buffer size (and don't need extra way for cursor) Reviewed-by: Aurabindo Pillai <Aurabindo.Pillai@amd.com> Acked-by: Wayne Lin <wayne.lin@amd.com> Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-09-19drm/amd/display: Remove some unused definitions from DCN32/321Aurabindo Pillai1-25/+0
[Why&How] After reg offset initialization was switched to runtime rather than compile time, some of the defintions are not needed anymore and can be removed. Acked-by: Wayne Lin <wayne.lin@amd.com> Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-09-19drm/amd/display: clean up some inconsistent indentingsYang Li1-13/+13
clean up some inconsistent indentings Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=2180 Reported-by: Abaci Robot <abaci@linux.alibaba.com> Signed-off-by: Yang Li <yang.lee@linux.alibaba.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
generated by cgit v1.2.3 (git 2.39.0) at 2024-08-27 16:09:50 +0300