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path: root/drivers/gpu/drm/amd/include/asic_reg/dcn
AgeCommit message (Expand)AuthorFilesLines
2024-04-27drm/amd/display: Add some missing HDMI registers for DCN3xRodrigo Siqueira4-0/+23
2024-04-10drm/amd/display: Add missing registersRodrigo Siqueira6-0/+136
2024-04-10drm/amd/display: Add some missing debug registersRodrigo Siqueira7-0/+81
2024-03-20drm/amd/display: Add missing registers and offsetRodrigo Siqueira2-1/+52
2024-03-04drm/amd: add register headers for DCN351Hamza Mahfooz2-0/+68723
2024-01-29drm/amd/include: Add missing registers/mask for DCN316 and 350Rodrigo Siqueira4-0/+103
2023-11-17drm/amd/display: Enable DCN clock gating for DCN35Daniel Miess1-0/+8
2023-08-30drm/amd/display: Add dcn35 register header filesQingqing Zhuo2-0/+68667
2023-08-16drm/amd/display: Add some missing register definitionsAurabindo Pillai4-1/+18
2022-11-23drm/amdgpu: add missing license to some filesAlex Deucher2-0/+2
2022-07-14drm/amdgpu: Add reg headers for DCN314Roman Li2-0/+77077
2022-07-13drm/amdgpu: fix file permissions on some filesAlex Deucher2-0/+0
2022-07-05drm/amd/display: Add missing registers for ACPRodrigo Siqueira5-0/+10
2022-06-22drm/amd/display: add missing reg defs for DCN3x HUBBUBAurabindo Pillai4-0/+11
2022-06-03drm/amd: add register headers for DCN32/321Aurabindo Pillai4-0/+308702
2022-05-26drm/amd/display: Add HDMI_ACP_SEND registerAlan Liu4-2/+8
2022-02-18drm/amd/include: add DCN 3.1.5 registersQingqing Zhuo2-0/+77252
2022-02-17drm/amd/include: Add register headers for DCN 3.1.6Leo Li2-0/+78399
2022-02-08drm/amdgpu: move dpcs_3_0_3 headers from dcn to dpcsAlex Deucher2-1396/+0
2022-02-08drm/amdgpu: move dpcs_3_0_0 headers from dcn to dpcsAlex Deucher2-4152/+0
2022-02-08drm/amdgpu: add missing license to dpcs_3_0_0 headersAlex Deucher2-0/+14
2021-10-20drm/amd/display: Disable hdmistream and hdmichar clocksJake Wang2-0/+10
2021-09-30drm/amdgpu: add cyan_skillfish asic header filesZhan Liu2-0/+28284
2021-07-08drm/amd/display: DMUB Outbound Interrupt Process-X86Chun-Liang Chang1-0/+4
2021-06-16drm/amd/display: Add interface to get Calibrated Avg Level from FIFOWesley Chalmers2-0/+4
2021-06-04drm/amdgpu: add yellow carp asic header files (v3)Aaron Liu2-0/+75830
2021-05-20drm/amd/display: Edit license info for beige goby DC filesAurabindo Pillai4-37/+18
2021-05-20drm/amd/display: Add register definitions for Beige GobyAurabindo Pillai4-0/+45172
2021-03-05drm/amd/amdgpu: Add missing BASE_IDX to dcn registerTom St Denis1-1/+1
2020-11-10drm/amdgpu: Add and use seperate reg headers for dcn302Bhawanpreet Lakha2-0/+78535
2020-10-05drm/amdgpu: add vangogh asic header files (v2)Huang Rui2-0/+66628
2020-08-24drm/amd/display: remove unintended executable modeLukas Bulwahn4-0/+0
2020-08-17drm/amd/display: Add DSC_DBG_EN shift/mask for dcn3Bhawanpreet Lakha1-0/+22
2020-06-03drm/amd/display: Add dcn30 Headers (v2)Jerry (Fangzhi) Zuo4-0/+92947
2020-01-16drm/amd/include: Add OCSC registersRodrigo Siqueira4-2/+24
2019-12-19drm/amdgpu: move dpcs headers to dpcs includesRoman Li2-3995/+0
2019-10-17drm/amd/display: Add DP_DPHY_INTERNAL_CTR regsBhawanpreet Lakha1-0/+10
2019-08-29drm/amd/display: Add Renoir registers (v3)Bhawanpreet Lakha4-0/+74495
2019-06-22drm/amd/display: Create DWB resource for DCN2Charlene Liu2-0/+20
2019-06-20drm/amdgpu: add DCN 2.0 register headersHawking Zhang2-0/+85539
2019-04-24drm/amd/include: Add HUBPREQ_DEBUG register offsetsLeo Li1-0/+8
2018-04-11drm/amdgpu: Add CM_TEST_DEBUG regs for DCNHarry Wentland2-3/+24
2018-02-19drm/amd/display: Adding missing TMZ sh/mask entries for DCN1 SURFACE_CONTROLHarry Wentland1-0/+14
2017-12-06drm/amd/include:cleanup raven1 dcn header files.Feifei Xu2-0/+68414
generated by cgit v1.2.3 (git 2.39.0) at 2024-08-11 10:24:03 +0300