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path: root/drivers/gpu/drm/i915/display/intel_cdclk.c
AgeCommit message (Expand)AuthorFilesLines
2024-04-09drm/i915: move max_dotclk_freq to display substructJani Nikula1-3/+3
2024-04-09drm/i915: move skl_preferred_vco_freq to display substructJani Nikula1-9/+8
2024-04-04drm/i915: Use a plain old int for the cdclk/mdclk ratioVille Syrjälä1-3/+3
2024-04-04drm/i915: Use the correct mdclk/cdclk ratio in MBUS updatesVille Syrjälä1-0/+11
2024-04-04drm/i915: Use old mbus_join value when increasing CDCLKStanislav Lisovskiy1-0/+6
2024-04-04drm/i915/cdclk: Indicate whether CDCLK change happens during pre or post plan...Ville Syrjälä1-13/+6
2024-04-04drm/i915/cdclk: Drop tgl/dg2 cdclk bump hacksVille Syrjälä1-19/+0
2024-04-04drm/i915/cdclk: Fix voltage_level programming edge caseVille Syrjälä1-10/+27
2024-04-04drm/i915/cdclk: Fix CDCLK programming order when pipes are activeVille Syrjälä1-2/+5
2024-03-13drm/i915/xe2lpd: Support MDCLK:CDCLK ratio changesGustavo Sousa1-0/+31
2024-03-13drm/i915: Add mdclk_cdclk_ratio to intel_dbuf_stateGustavo Sousa1-0/+20
2024-03-13drm/i915/cdclk: Only compute squash waveform when necessaryGustavo Sousa1-3/+3
2024-03-13drm/i915/cdclk: Add and use mdclk_source_is_cdclk_pll()Gustavo Sousa1-1/+14
2024-03-13drm/i915/cdclk: Rename lnl_cdclk_table to xe2lpd_cdclk_tableGustavo Sousa1-2/+2
2024-03-11drm/i915: Reuse RPLU cdclk fns for MTL+Radhakrishna Sripada1-9/+2
2024-02-28drm/i915/cdclk: Document CDCLK componentsGustavo Sousa1-0/+26
2024-02-28drm/i915/cdclk: Rename intel_cdclk_needs_modeset to intel_cdclk_clock_changedGustavo Sousa1-7/+6
2024-02-23drm/i915: Fix doc build issue on intel_cdclk.cRodrigo Vivi1-0/+1
2024-02-16drm/i915/cdclk: Document CDCLK update methodsVille Syrjälä1-0/+9
2024-02-16drm/i915/cdclk: Remove the hardcoded divider from cdclk_compute_crawl_and_squ...Ville Syrjälä1-2/+16
2024-02-16drm/i915/cdclk: Squash waveform is 16 bitsVille Syrjälä1-1/+1
2024-02-16drm/i915/cdclk: Extract cdclk_divider()Ville Syrjälä1-14/+17
2024-01-08drm/i915/cdclk: Re-use bxt_cdclk_ctl() when sanitizingGustavo Sousa1-23/+3
2024-01-08drm/i915/cdclk: Reorder bxt_sanitize_cdclk()Gustavo Sousa1-12/+12
2024-01-08drm/i915/cdclk: Extract bxt_cdclk_ctl()Gustavo Sousa1-22/+35
2024-01-08drm/i915/xe2lpd: Update bxt_sanitize_cdclk()Gustavo Sousa1-1/+4
2024-01-03drm/i915/mtl: Add fake PCH for Meteor LakeHaridhar Kalvala1-3/+3
2023-12-20drm/i915/cdclk: Remove divider field from tablesGustavo Sousa1-135/+134
2023-12-13drm/i915/mtl: Fix voltage_level for cdclk==480MHzVille Syrjälä1-1/+1
2023-12-13drm/i915/cdclk: Rewrite cdclk->voltage_level selection to use tablesVille Syrjälä1-30/+57
2023-12-13drm/i915/cdclk: Remove the assumption that cdclk divider==2 when using squashingVille Syrjälä1-7/+5
2023-12-13drm/i915/cdclk: Give the squash waveform length a nameVille Syrjälä1-2/+4
2023-12-13drm/i915/cdclk: s/-1/~0/ when dealing with unsigned valuesVille Syrjälä1-2/+2
2023-11-29drm/i915: Clean up some DISPLAY_VER checksVille Syrjälä1-1/+1
2023-11-14drm/i915/display: Store compressed bpp in U6.4 formatAnkit Nautiyal1-2/+3
2023-11-04drm/i915: Bump GLK CDCLK frequency when driving multiple pipesVille Syrjälä1-0/+12
2023-09-28drm/i915: Rename intel_modeset_all_pipes() to intel_modeset_all_pipes_late()Imre Deak1-1/+1
2023-09-21drm/i915/lnl: Start using CDCLK through PLLStanislav Lisovskiy1-2/+7
2023-09-21drm/i915/lnl: Add CDCLK tableStanislav Lisovskiy1-1/+29
2023-09-21drm/i915/xe2lpd: Extend Wa_15010685871Lucas De Marchi1-3/+4
2023-08-22drm/i915/display: Eliminate IS_METEORLAKE checksMatt Roper1-2/+2
2023-08-18drm/i915/intel_cdclk: Add vdsc with bigjoiner constraints on min_cdlckAnkit Nautiyal1-14/+45
2023-08-08drm/i915/rplu: s/ADLP_RPLU/RAPTORLAKE_U in RPLU definesDnyaneshwar Bhadane1-1/+1
2023-08-08drm/i915/adlp: s/ADLP/ALDERLAKE_P for display and graphics stepDnyaneshwar Bhadane1-1/+1
2023-08-08drm/i915/jsl: s/JSL/JASPERLAKE for platform/subplatform definesDnyaneshwar Bhadane1-2/+2
2023-08-08drm/i915/bdw: s/BDW/BROADWELL for platform/subplatform definesDnyaneshwar Bhadane1-2/+2
2023-08-08drm/i915/hsw: s/HSW/HASWELL for platform/subplatform definesDnyaneshwar Bhadane1-1/+1
2023-07-10drm/i915: Don't rely that 2 VDSC engines are always enough for pixel rateStanislav Lisovskiy1-2/+10
2023-06-07drm/i915: annotate maybe unused but set intel_plane_state variablesJani Nikula1-1/+1
2023-06-03drm/i915/display: Set correct voltage level for 480MHz CDCLKChaitanya Kumar Borah1-4/+26
generated by cgit v1.2.3 (git 2.39.0) at 2024-08-07 22:38:43 +0300