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path: root/drivers/gpu/drm/nouveau/core/engine/graph
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2014-01-23drm/nv108/gr: enable acceleration with our chsw ucodeBen Skeggs1-1/+1
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2014-01-23drm/nvc0-/gr: handle fwmthd interrupts in ucodeBen Skeggs7-294/+308
Compute code in mesa triggers one of these, hanging the engine. Let's at least ack the request for now to avoid the hang. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2014-01-23drm/nvc0-/gr: fiddle some magic around strand initBen Skeggs7-1110/+1191
Fixes HUB_INIT timeout on GK110/GK208 when not using NVIDIA's ucode. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2014-01-23drm/nv108/gr: initial support (need external fuc)Ben Skeggs10-7/+3070
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2014-01-23drm/nvf0/gr: remove a copy+pasto in ctx reglistBen Skeggs1-1/+0
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2014-01-23drm/nvc0-/gr: bring in some macros to abstract falcon isa differencesBen Skeggs12-3943/+4431
Need. A. Compiler... Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2014-01-07drm/nvc0/gr: fix mthd data submissionKelly Doran1-1/+1
If the initial data element is 0, it will never be written, even though the value from the previous method may be there. Signed-off-by: Kelly Doran <kel.p.doran@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-11-14drm/nvc0-/gr: shift wrapping bug in nvc0_grctx_generate_r406800Dan Carpenter1-1/+1
We care about the upper 32 bits here so we have to use 1ULL instead of 1 to avoid a shift wrapping bug. Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Maarten Lankhorst <maarten.lankhorst@canonical.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-11-08drm/nouveau/perfmon: initial infrastructure to expose performance countersBen Skeggs1-1/+1
Internal use only at this point. Userspace later. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-11-08drm/nvc0-/gr: fix a number of missing explicit array terminators...Ben Skeggs3-0/+6
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-11-08drm/nv10: fix chipset checks, mostly for the benefit of nv1aIlia Mirkin1-5/+9
NV1A is numerically higher than NV17 but generationally lower. Use the new card type to help disambiguate. Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-09-04drm/nouveau: remove duplicate copy of nv44_graph_classIlia Mirkin1-0/+3
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-08drm/nvc0/gr: fix gpc firmware regressionMaarten Lankhorst2-20/+23
"drm/nve0-/gr: some new gpc registers can have multiple copies" 5ee86c4190f9e caused a regression for nvc0, because the bit indicating last transfer has occured was no longer set, resulting in random system lockups. Reported-by: Ronald Uitermark <ronald645@gmail.com> Tested-by: Ronald Uitermark <ronald645@gmail.com> Signed-off-by: Maarten Lankhorst <maarten.lankhorst@canonical.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-05drm/nvc0-/gr: remove some more of the hardcoded register writesBen Skeggs3-28/+6
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-05drm/nvc0-/gr: factor out yet more unknown magic into versioned functionsBen Skeggs9-14/+42
NVC1/NVD9 are the only chipsets that should have anything different happen on them after this. We previously weren't doing these register modifications, and NVIDIA do. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-05drm/nvf0-/gr: ctxsw scratch reg count got bumped to 16Ben Skeggs12-3034/+3303
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-05drm/nvc0-/gr: remove hardcoding of UNK count/mask in GPCCS ucodeBen Skeggs4-95/+129
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-05drm/nvf0/gr: build cs ucode for GK110Ben Skeggs6-0/+1431
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-05drm/nvc0-/gr: extend one of the magic calculations for >4 GPCsBen Skeggs1-6/+11
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-05drm/nvf0/gr: fix ddx shaders locking up on meBen Skeggs3-3/+54
This can be generalised and used on GK104 (probably even GF117), but lets just make it work for now. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-05drm/nvf0/gr: enable support, if external cs ucode is availableBen Skeggs2-1/+6
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-05drm/nvf0/gr: magic sequence that makes PGRAPH come out of hidingBen Skeggs1-2/+48
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-05drm/nvd7/gr: initial supportMaarten Lankhorst19-19/+1926
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@canonical.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-05drm/nvc0-/gr: generate cs register lists from grctx dataBen Skeggs11-2073/+1152
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-05drm/nvc0-/gr: tpc regs a subset of gpc, add separate list for gpc/unk regsBen Skeggs8-34/+52
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-05drm/nve0-/gr: some new gpc registers can have multiple copiesBen Skeggs4-180/+227
GK110 exposes more than one, and needs to be dealt with in the ctxsw ucode just like the TPC sets are. Broadcast is at +0xe00. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-05drm/nvc0-/gr: pull out a group of separately context-switched gpc regsBen Skeggs6-96/+68
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-05drm/nvc0-/gr: make register lists from initvals functionsBen Skeggs17-8406/+6092
Generated context verified to be the same for all supported chipsets. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01drm/gr/nvc0-: merge nvc0/nve0 ucode, and use cpp instead of m4Ben Skeggs14-2587/+1270
No code changes, proven by envyas producing identical binaries. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01drm/nvc0/gr: cleanup register lists, and add nvce/nvcf to switchesBen Skeggs6-600/+344
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01drm/nvc8/gr: update initial register/context valuesBen Skeggs6-10/+74
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01drm/nvc4/gr: update initial register/context valuesBen Skeggs6-9/+62
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01drm/nvc1/gr: update initial register/context valuesBen Skeggs6-35/+80
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01drm/nvc3/gr: update initial register/context valuesBen Skeggs6-12/+112
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01drm/nvc0/gr: update initial register/context valuesBen Skeggs6-544/+1042
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01drm/nvd9/gr: update initial register/context valuesBen Skeggs6-74/+482
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01drm/nve4/gr: update initial register/context valuesBen Skeggs4-157/+31
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01drm/nvc0-/gr: bump maximum gpc/tpc limitsBen Skeggs1-2/+4
Needed for GK110, separate commit to catch any unexpected breaks to other parts of the code. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01drm/nvf0/gr: initial register/context setupBen Skeggs6-482/+1057
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01drm/nve7/gr: update initial register/context valuesBen Skeggs4-3/+12
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01drm/nve6/gr: update initial register/context valuesBen Skeggs4-113/+383
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01drm/nv50/vm: remove explicit vm knowledge from enginesBen Skeggs1-12/+6
This reverses the lock ordering between VM and gr/nv84:nvc0. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01drm/nvc0/gr: port mp trap handling from calim's kepler codeBen Skeggs1-6/+38
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01drm/nve0/gr: attempt to resume after sm trapsBen Skeggs1-16/+6
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01drm/nve0/gr: s/tp/tpc/Ben Skeggs1-26/+27
NVIDIA's name... Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01drm/nve0/ce: link ce2 to its engine, rather than from graphicsBen Skeggs1-1/+0
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01drm/nouveau: pull in latest ucode builds from external treeBen Skeggs2-42/+45
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-04-26drm/nv20-nv30/gr: use parent as self for subobjectsBen Skeggs6-6/+6
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-04-26drm/nvc0-/gr: use self as parent for subobjectsBen Skeggs3-9/+13
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-04-26drm/nve0/gr: add handling for a bunch of PGRAPH trapsChristoph Bumiller1-0/+222
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
generated by cgit v1.2.3 (git 2.39.0) at 2024-09-20 02:03:00 +0300